DETAILED ACTION
This action is responsive to the application filed 22 Feb 2022 and the latest Information Disclosure Statement filed 30 Dec 2025. Claims 1-20 are pending. Claims 1, 9 and 17 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Foreign Priority Claim
Acknowledgment is made of applicant’s claim for foreign priority. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 30 Dec 2025 and 28 Feb 2022 are acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Application Title
The Examiner proposes the below Application Title change in accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the title. The Applicant can suggest an alternative title if desired. The Application Title should be changed to the following:
“SEMICONDUCTOR MEMORY DEVICE WITH MULTIPLE VERTICAL PASS TRANSISTORS REGIONS BORDERING THE MEMORY ARRAY”
No action is required by the applicant. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
Allowable Subject Matter
Claims 3 – 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Specifically, Baek teaches that the substrate can have multiple Pass Transistors as claimed in claim 1, but Baek is silent regarding the position of the row decoder circuits relative to the pass transistors for each side of the multiple memory blocks. While other reference might teach the location of the row decoder circuits relative to the memory array, it would not be obvious to combine the unusual location of the multiple pass transistors and the slightly unusual location of the row decoder in a single memory cell.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 2, and 9 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baek, et al, U.S. Patent Application Publication 2019/0319042 (“Baek”).
Regarding claim 1, Baek teaches:
A semiconductor memory device comprising: a first gate stack structure and a second gate stack structure, including a first conductive pattern and a second conductive pattern, the first conductive pattern spaced apart from the second conductive pattern, the first gate stack structure adjacent to the second gate stack structure; (Baek, fig 1, 5, 6, 7, 8, 12, “[0066] Referring to FIGS. 7, 8, 9 and 10, a peripheral logic structure PS may include peripheral logic circuits integrated on an entire top surface of a semiconductor substrate 10, and a peripheral buried insulating layer 50 covering the peripheral logic circuits. [0051] The electrode structure ST may include a cell electrode structure CST and a plurality of ground selection gate electrodes GGEla, GGElb, GGE2a and GGE2b provided between the cell electrode structure CST and the horizontal semiconductor layer 100. The plurality of ground selection gate electrodes GGEla, GGElb, GGE2a and GGE2b may include a plurality of first ground selection gate electrodes GGEla and GGElb disposed on the first cell array region CARl and a plurality of second ground selection gate electrodes GGE2a and GGE2b disposed on the second cell array region CAR2.”; a semiconductor memory device on a substrate arranged with a peripheral connection scheme; that the memory device comprises multiple gate layers stacked on the substate; in figure 8 and 12, at least two conductive, nearly identical, conductive patterns exist to control the two memory blocks using different bitlines and vertical structures for gate control, with perhaps a common source line. Note; applicant’s “first gate” and “second gate” could be two source line gates, or two drain gates, they are not limited to different functions, merely separated by geometry).
a vertical conductive line disposed adjacent to the first gate stack structure and the second gate stack structure; and (Baek, fig 8, 12, “[0071] A cell array structure CS may be disposed on the peripheral buried insulating layer 50 and may include a horizontal semiconductor layer 100, an electrode structure ST, vertical structures VSl and VS2, and through-interconnection structures TSl, TS2, TS3 and TS4 connecting the cell array structure CS and the peripheral logic structure PS.”; that the two memory blocks can each have their distance vertical structures with many similar control elements, such as similar TS1-TS4 structures to at least support the control gates).
a semiconductor substrate extending to overlap with the first gate stack structure, the second gate stack structure, and the vertical conductive line, (Baek, fig 8, 12, “[0066] Referring to FIGS. 7, 8, 9 and 10, a peripheral logic structure PS may include peripheral logic circuits integrated on an entire top surface of a semiconductor substrate 10, and a peripheral buried insulating layer 50 covering the peripheral logic circuits.”; that the substrate 50 extends across the device from peripheral to memory and back to peripheral regions).
wherein the semiconductor substrate includes a plurality of pass transistors connected to the first and second conductive patterns of at least one of the first gate stack structure and the second gate stack structure, and (Baek, fig 2, 11C, 12, “[0040] A row decoder 3a and 3b may include a plurality of pass transistors SPTl, SPT2, WPT, PTl and PT2 connected to the selection lines SSL0 to SSL2 and GSL0 to GSL2 and the word lines WL0 to WLn and DWL, respectively.”; that row decoders and other layers can comprise pass transistors to control memory blocks and cells).
wherein the vertical conductive line is connected to a plurality of gate electrodes of the plurality of pass transistors. (Baek, fig 8, 12, “[0068] In some embodiments, the peripheral logic structure PS may include first and second pass transistors PTl and PT2 for controlling first ground selection gate electrodes GGEla and GGElb, and third and fourth pass transistors PT3 and PT4 for controlling second ground selection gate electrodes GGE2a and GGE2b.”; that at least PT1-PT4 are located in the substrate 50 region to control the two memory blocks; that the PT1-4 cross from the bottom to top in insulator 150; that the PT1-4 then pass through the vertical regions again to the source region as needed).
Regarding claim 2, Baek teaches:
The semiconductor memory device of claim 1, wherein, on a plane parallel to the semiconductor substrate, the vertical conductive line extends in a first direction, and (Baek, fig 5, 6, 7, 8, “[0048] FIG. 5 is a schematic plan view illustrating an electrode structure [0064] FIG. 7 is a schematic plan view illustrating a 3D semiconductor memory device… FIGS. llA and 11B are enlarged views of portions ‘A’ and ‘B’ of FIG. 7, respectively.”; that connectors can run on a surface 100 on top of the memory device).
the first gate stack structure and the second gate stack structure are adjacent to each other in a second direction intersecting the vertical conductive line, (Baek, fig 5, 6, 7, 8, “[0049] Referring to FIGS. 5 and 6, the horizontal semiconductor layer 100 may include the first and second connection regions CNRl and CNR2, the first and second cell array regions CARl and CAR2, and/or the common connection region CNR3, as described above.”; that the connectors have multiple pads to connect each individual memory block, that each of the gate structures can be adjacent to each other on this surface to control the device).
wherein the first gate stack structure includes a first end portion and a second end portion spaced apart from the first end portion in the first direction, and wherein the plurality of pass transistors include a first pass transistor overlapping with the first end portion of the first gate stack structure and a second pass transistor overlapping with the second end portion of the first gate stack structure. (Baek, fig 5, 6, 7, 8, “[0071] A cell array structure CS may be disposed on the peripheral buried insulating layer 50 and may include a horizontal semiconductor layer 100, an electrode structure ST, vertical structures VSl and VS2, and through-interconnection structures TSl, TS2, TS3 and TS4 connecting the cell array structure CS and the peripheral logic structure PS.”; that each of the pass transistors have an associated vertical structure VS1/2 and through interconnection structure TS1-4, that these structures “overlap” at least a portion of the gate stack structure to connect with the controlling gates for each pillar).
Regarding claim 9, Baek teaches:
A semiconductor memory device, comprising: a semiconductor substrate including a peripheral circuit structure; (Baek, fig 1, “[0066] Referring to FIGS. 7, 8, 9 and 10, a peripheral logic structure PS may include peripheral logic circuits integrated on an entire top surface of a semiconductor substrate 10, and a peripheral buried insulating layer 50 covering the peripheral logic circuits.”; a semiconductor memory device on a substrate arranged with a peripheral connection scheme).
a vertical conductive line disposed over the semiconductor substrate, the vertical conductive line extending in a first direction on a plane parallel to the semiconductor substrate, the vertical conductive line being connected to the peripheral circuit structure; (Baek, fig 7, “[0064] FIG. 7 is a schematic plan view illustrating a 3D semiconductor memory device according to some embodiments of the inventive concepts.”; multiple vertical connectors, comprising at least XXX (see fig 12); the vertical connectors attached to corresponding horizontal connectors from the peripheral circuits to the interior memory cell blocks).
a vertical insulating layer extending on a sidewall of the vertical conductive line; and (Baek, fig 12, “[0079] An upper planarization insulating layer 150 may be disposed on the lower planarization insulating layer 120 to cover the stepped structures of the cell electrode structure CST.”; multiple layers of insulating layer 150 between each of the vertical columns).
a first gate stack structure and a second gate stack structure, adjacent to each other in a second direction intersecting the vertical conductive line, (Baek, fig 5, 6, 7, 8, “[0051] The electrode structure ST may include a cell electrode structure CST and a plurality of ground selection gate electrodes GGEla, GGElb, GGE2a and GGE2b provided between the cell electrode structure CST and the horizontal semiconductor layer 100. The plurality of ground selection gate electrodes GGEla, GGElb, GGE2a and GGE2b may include a plurality of first ground selection gate electrodes GGEla and GGElb disposed on the first cell array region CARl and a plurality of second ground selection gate electrodes GGE2a and GGE2b disposed on the second cell array region CAR2.”; a plurality of gate structures GGE1a-GGE2b which are connected to two arrays in a parallel manner to the substrate, that extend horizontally, and are connected to the periphery using vertical connectors. Note; applicant’s “first gate” and “second gate” could be two source line gates, or two drain gates, they are not limited to different functions, merely separated by geometry).
wherein the vertical conductive line and the vertical insulating layer are disposed between the first gate stack structure and the second gate stack structure, and (Baek, fig 8, 12, “[0071] A cell array structure CS may be disposed on the peripheral buried insulating layer 50 and may include a horizontal semiconductor layer 100, an electrode structure ST, vertical structures VSl and VS2, and through-interconnection structures TSl, TS2, TS3 and TS4 connecting the cell array structure CS and the peripheral logic structure PS.”; that vertical lines are typically used to connect almost all peripheral lines to each layer of control gates and cell gates in a memory).
wherein each of the first gate stack structure and the second gate stack structure includes a plurality of interlayer insulating layers and a plurality of conductive patterns, which are alternately stacked over the semiconductor substrate. (Baek, fig 8, 12, “[0076] A cell electrode structure CST of the electrode structure ST may be disposed on the lower planarization insulating layer 120. The cell electrode structure CST may include cell gate electrodes CGE and interlayer insulating layers ILD, which are alternately stacked on the lower planarization insulating layer 120. [0093] Since the cell electrode structure CST is formed to surround the opening OP in a plan view, the cell contact plugs CPLG may be connected to the cell pads of the cell gate electrodes CGE in substantially all directions in a plan view, and the cell connection lines CCL may be connected to the cell contact plugs CPLG in substantially all directions in a plan view.”; that gate structures, whether control or memory gates, typically contain alternating conductive and insulating layers; and are connected using a stepped vertical connectors as shown throughout figures 5-12).
Regarding claim 10, Baek teaches:
The semiconductor memory device of claim 9, wherein the peripheral circuit structure includes a first circuit group, a second circuit group, and a third circuit group, which are connected to the vertical conductive line and are spaced apart from each other, and (Baek, fig 8, 12, “[0089] Referring to FIGS. llA, 11B, llC and 12, according to some embodiments, gate separation regions penetrating the electrode structure ST may be provided on the first and second cell array regions CARl and CAR2. Common source regions CSR may be provided in the horizontal semiconductor layer 100 under the gate separation regions penetrating the electrode structure ST. [0090] The gate separation regions may extend in the first direction Dl, and some of the gate separation regions may have different lengths in the first direction Dl. Each of the cell gate electrodes CGE may have a portion that overlaps with an empty space between adjacent ground selection gate electrodes GGEla, GGElb, GGE2a and GGE2b when viewed in a plan view.”; that multiple types of circuits to include ground gates, common source lines, source gates, and at least memory gates, are all wired in the vertical from the peripheral region).
wherein the vertical conductive line is configured to transmit a signal output from the third circuit group to the first circuit group and the second circuit group. (Baek, fig 8, 12, “[0068] The peripheral logic circuits may include the row and column decoders, the page buffer and the control logic circuit described above and may include NMOS and PMOS transistors… In some embodiments, the peripheral logic structure PS may include first and second pass transistors PTl and PT2 for controlling first ground selection gate electrodes GGEla and GGElb, and third and fourth pass transistors PT3 and PT4 for controlling second ground selection gate electrodes GGE2a and GGE2b. [0084] The first through-interconnection structure TSl may include first contact plugs PLGl connected to the first pads Pl of the first ground selection gate electrodes GGEla and GGElb, first through-plugs THVl penetrating the upper and lower planarization insulating layers 150 and 120 and the peripheral buried insulating layer 50 so as to be connected to the peripheral interconnection lines 33,”; that a control circuit can out put the controls necessary to control source, ground, and memory cells using Through-interconnection structures, which are vertical in nature).
Regarding claim 11, Baek teaches:
The semiconductor memory device of claim 10, wherein the third circuit group is configured to output the signal corresponding to a block select signal, and (Baek, fig 8, 12, “[0112] According to the embodiments of the inventive concepts, the cell electrode structure may be provided in common in the first and second memory blocks, and the through-interconnection structure connecting the cell array structure and the peripheral logic structure may be provided in the common connection region between the first and second cell array regions.”; a memory device with at least two memory blocks, separated by control lines for the various controlling gates).
wherein the first circuit group and the second circuit group are configured to transmit operating voltages to the plurality of conductive patterns of one of the first gate stack structure and the second gate stack structure in response to the block select signal. (Baek, fig 8, 12, “[0089] Referring to FIGS. llA, 11B, llC and 12, according to some embodiments, gate separation regions penetrating the electrode structure ST may be provided on the first and second cell array regions CARl and CAR2. Common source regions CSR may be provided in the horizontal semiconductor layer 100 under the gate separation regions penetrating the electrode structure ST. [0090] The gate separation regions may extend in the first direction Dl, and some of the gate separation regions may have different lengths in the first direction Dl. Each of the cell gate electrodes CGE may have a portion that overlaps with an empty space between adjacent ground selection gate electrodes GGEla, GGElb, GGE2a and GGE2b when viewed in a plan view.”; the at least two memory blocks of figs 8 and 12, each with multiple types of circuits to include ground gates, common source lines, source gates, and at least memory gates, are all wired in the vertical from the peripheral region).
Regarding claim 12, Baek teaches:
The semiconductor memory device of claim 11, wherein the plurality of conductive patterns include a first local line and a second local line, which are spaced apart from each other in a direction intersecting a top surface of the semiconductor substrate, (Baek, fig 2, 11C, 12, “[0040] A row decoder 3a and 3b may include a plurality of pass transistors SPTl, SPT2, WPT, PTl and PT2 connected to the selection lines SSL0 to SSL2 and GSL0 to GSL2 and the word lines WL0 to WLn and DWL, respectively. [0092] Referring to FIGS. llC and 12, cell through interconnection structures CTS connecting the cell gate electrodes CGE to the peripheral logic structure PS may be provided.”; that each row decoder has a pass transistor to activate it’s particular vertical construction whether ground, source, or memory cell).
wherein the first circuit group includes a first pass transistor connected to the first local line, and the second circuit group includes a second pass transistor connected to the second local line, and wherein the vertical conductive line is commonly connected to a first gate electrode of the first pass transistor and a second gate electrode of the second pass transistor. (Baek, fig 11A-C, 12, “[0070] The peripheral buried insulating layer 50 may cover the first to fourth pass transistors PTl to PT4, the peripheral contact plugs 31 and the peripheral interconnection lines 33 on the semiconductor substrate 10. [0064] FIG. llC is a plan view illustrating a cell electrode structure and an interconnection structure. FIG. 12 is a cross-sectional view taken along a line I-I’ of FIG. 11A.”; that each of the rows, arranged in a vertical manner, has a vertical connector as shown by CCLs of figures 11A-C and 12, that each of the claimed gates have individual connectors from the pass transistors to the cells).
Regarding claim 13, Baek teaches:
The semiconductor memory device of claim 10, further comprising: a channel layer penetrating the first gate stack structure and the second gate stack structure; a memory layer surrounding a sidewall of the channel layer; (Baek, fig 5, 6, 7, 8, “[0051] The electrode structure ST may include a cell electrode structure CST and a plurality of ground selection gate electrodes GGEla, GGElb, GGE2a and GGE2b provided between the cell electrode structure CST and the horizontal semiconductor layer 100. The plurality of ground selection gate electrodes GGEla, GGElb, GGE2a and GGE2b may include a plurality of first ground selection gate electrodes GGEla and GGElb disposed on the first cell array region CARl and a plurality of second ground selection gate electrodes GGE2a and GGE2b disposed on the second cell array region CAR2.”; a plurality of gate structures GGE1a-GGE2b which are connected to two arrays in a parallel manner to the substrate, that extend horizontally, and are connected to the periphery using vertical connectors).
a bit line disposed between the peripheral circuit structure and the channel layer, the bit line being connected to the channel layer; and (Baek, fig 8, 12, “[0081] First bit lines BLl may extend in the second direction D2 on the second interlayer insulating layer 153 of the first cell array region CARl to intersect the electrode structure ST. The first bit lines BLl may be electrically connected to the first vertical structures VSl through bit line contact plugs.”; that bitlines are arranged to crisscross the other control lines and allow access to individual channels, different groups of bitlines BL1 and BL2 are arranged to address the two memory blocks).
a source layer extending to overlap with the first gate stack structure and the second gate stack structure, the source layer being in contact with the channel layer. (Baek, fig 8, 12, “Common source regions CSR may be provided in the horizontal semiconductor layer 100 under the gate separation regions penetrating the electrode structure ST. The common source regions CSR may extend in the first direction Dl. The common source regions CSR may include dopants of which a conductivity type is opposite to that of the horizontal semiconductor layer 100.”; that a common source region extends in the horizontal from the other control lines to control the associated gate function from the source, ground, and memory gates in vertical pillars).
Regarding claim 14, Baek teaches The semiconductor memory device of claim 13, wherein each of the channel layer and the vertical conductive line protrudes farther toward the source layer than the memory layer. (Baek, fig 8, 12, “[0088] The fourth through-interconnection structure TS4 may be provided on the common connection region CNR3 and may connect the second pads P2 of the second ground selection gate electrodes GGE2a and GGE2b to the fourth pass transistors PT4. The fourth through-interconnection structure TS4 may include fourth contact plugs PLG4 connected to the second pads P2 of the second ground selection gate electrodes GGE2a and GGE2b, fourth through-plugs THV4 penetrating the upper and lower planarization insulating layers 150 and 120 and the peripheral buried insulating layer 50 so as to be connected to the peripheral interconnection lines 33, and fourth connection lines CL4 connecting the fourth contact plugs PLG4 to the fourth through-plugs THV4.”; that the vertical conductive lines from the substrate extend farther through the structure to the PT1-4 to connect the ground and source gates to the channels; that the memory vertical connects pass only from the bit line to the depth of the individual memory layers).
Regarding claim 15, Baek teaches The semiconductor memory device of claim 13, wherein the vertical insulating layer extends between the source layer and the vertical conductive line. (Baek, fig 8, 12, “[0088] The fourth through-interconnection structure TS4 may be provided on the common connection region CNR3 and may connect the second pads P2 of the second ground selection gate electrodes GGE2a and GGE2b to the fourth pass transistors PT4. The fourth through-interconnection structure TS4 may include fourth contact plugs PLG4 connected to the second pads P2 of the second ground selection gate electrodes GGE2a and GGE2b, fourth through-plugs THV4 penetrating the upper and lower planarization insulating layers 150 and 120 and the peripheral buried insulating layer 50 so as to be connected to the peripheral interconnection lines 33, and fourth connection lines CL4 connecting the fourth contact plugs PLG4 to the fourth through-plugs THV4.”; the vertical lines to the PT-1-4 are surrounded by the insulating material 150 from the bottom of the substrate to the top, and then back down from the top of the structure to the control lines; see TS1 of fig 12).
Regarding claim 16, Baek teaches The semiconductor memory device of claim 13, wherein the vertical insulating layer is thicker than the memory layer. (Baek, fig 8, 12, “[0088] The fourth through-interconnection structure TS4 may be provided on the common connection region CNR3 and may connect the second pads P2 of the second ground selection gate electrodes GGE2a and GGE2b to the fourth pass transistors PT4. The fourth through-interconnection structure TS4 may include fourth contact plugs PLG4 connected to the second pads P2 of the second ground selection gate electrodes GGE2a and GGE2b, fourth through-plugs THV4 penetrating the upper and lower planarization insulating layers 150 and 120 and the peripheral buried insulating layer 50 so as to be connected to the peripheral interconnection lines 33, and fourth connection lines CL4 connecting the fourth contact plugs PLG4 to the fourth through-plugs THV4.”; the vertical lines to the PT-1-4 are surrounded by the insulating material 150 from the bottom of the substrate to the top, that the layer 150 is much thicker than the insulation between the individual memory layers).
Regarding claim 17, Baek teaches:
A semiconductor memory device comprising: a semiconductor substrate including a first circuit group and a second circuit group, which are spaced apart from each other; (Baek, fig 1, “[0066] Referring to FIGS. 7, 8, 9 and 10, a peripheral logic structure PS may include peripheral logic circuits integrated on an entire top surface of a semiconductor substrate 10, and a peripheral buried insulating layer 50 covering the peripheral logic circuits.”; a semiconductor memory device on a substrate arranged with a peripheral connection scheme).
a memory cell array overlapping with the semiconductor substrate; (Baek, fig 5, 6, 7, 8, “[0051] The electrode structure ST may include a cell electrode structure CST and a plurality of ground selection gate electrodes GGEla, GGElb, GGE2a and GGE2b provided between the cell electrode structure CST and the horizontal semiconductor layer 100. The plurality of ground selection gate electrodes GGEla, GGElb, GGE2a and GGE2b may include a plurality of first ground selection gate electrodes GGEla and GGElb disposed on the first cell array region CAR1 and a plurality of second ground selection gate electrodes GGE2a and GGE2b disposed on the second cell array region CAR2.”; a plurality of gate structures GGE1a-GGE2b which are connected to two arrays in a parallel manner to the substrate, that extend horizontally, and are connected to the periphery using vertical connectors. Note; applicant’s “first gate” and “second gate” could be two source line gates, or two drain gates, they are not limited to different functions, merely separated by geometry).
a vertical conductive line crossing the memory cell array, the vertical conductive line overlapping with the semiconductor substrate; (Baek, fig 7, “[0064] FIG. 7 is a schematic plan view illustrating a 3D semiconductor memory device according to some embodiments of the inventive concepts.”; multiple vertical connectors, comprising at least XXX (see fig 12); the vertical connectors attached to corresponding horizontal connectors from the peripheral circuits to the interior memory cell blocks).
a plurality of first conductive bonding patterns disposed at a level between the semiconductor substrate and the memory cell array, the plurality of first conductive bonding patterns being respectively connected to the first circuit group and the second circuit group; and (Baek, fig 5, 6, 7, 8, “[0084] The first through-interconnection structure TSl may include first contact plugs PLGl connected to the first pads Pl of the first ground selection gate electrodes GGEla and GGElb, first through-plugs THVl penetrating the upper and lower planarization insulating layers 150 and 120 and the peripheral buried insulating layer 50 so as to be connected to the peripheral interconnection lines 33, and first connection lines CLl connecting the first contact plugs PLGl to the first through-plugs THVl.”; a plurality of bonds passing through multiple layers of the substrate and memory levels; these lines 33 are attached to the PT1-4 to the memory cell columns).
a plurality of second conductive bonding patterns disposed at a level between the plurality of first conductive bonding patterns and the memory cell array, (Baek, fig 5, 6, 7, 8, “[0070] The peripheral buried insulating layer 50 may cover the first to fourth pass transistors PTl to PT4, the peripheral contact plugs 31 and the peripheral interconnection lines 33 on the semiconductor substrate 10. The peripheral buried insulating layer 50 may include a plurality of stacked insulating layers.”; a second set of connecting lines 31, each of the connecting lines 33 and 31 have multiple levels going from the PT1-4 connections to the top of the memory device).
the plurality of second conductive bonding patterns being connected to the vertical conductive line and the memory cell array, (Baek, fig 8, 12, “[0071] A cell array structure CS may be disposed on the peripheral buried insulating layer 50 and may include a horizontal semiconductor layer 100, an electrode structure ST, vertical structures VSl and VS2, and through-interconnection structures TSl, TS2, TS3 and TS4 connecting the cell array structure CS and the peripheral logic structure PS.”; the TS1-4 vertical lines are typically used to connect almost all peripheral lines to each layer of control gates and cell gates in a memory).
the plurality of second conductive bonding patterns being bonded to the plurality of first conductive bonding patterns, (Baek, fig 5, 6, 7, 8, “[0070] The peripheral buried insulating layer 50 may cover the first to fourth pass transistors PTl to PT4, the peripheral contact plugs 31 and the peripheral interconnection lines 33 on the semiconductor substrate 10. The peripheral buried insulating layer 50 may include a plurality of stacked insulating layers.”; each of the connecting lines 33 and 31 have multiple levels going from the PT1-4 connections to the top of the memory device).
wherein the vertical conductive line is commonly connected to the first circuit group and the second circuit group via parts of the plurality of first conductive bonding patterns and parts of the plurality of second conductive bonding patterns. (Baek, fig 8, 12, “[0071] A cell array structure CS may be disposed on the peripheral buried insulating layer 50 and may include a horizontal semiconductor layer 100, an electrode structure ST, vertical structures VSl and VS2, and through-interconnection structures TSl, TS2, TS3 and TS4 connecting the cell array structure CS and the peripheral logic structure PS.”; the TS1-4 vertical lines are typically used to connect almost all peripheral lines to each layer of control gates and cell gates in a memory; the TS lines each have their own conductive bonding pattern that is repeated to activate the memory cells).
Regarding claim 18, Baek teaches:
The semiconductor memory device of claim 17, wherein the memory cell array includes: a plurality of interlayer insulating layers and a plurality of conductive patterns, alternately stacked over the semiconductor substrate; (Baek, fig 1, 5, 6, 7, 8, 12, “[0066] Referring to FIGS. 7, 8, 9 and 10, a peripheral logic structure PS may include peripheral logic circuits integrated on an entire top surface of a semiconductor substrate 10, and a peripheral buried insulating layer 50 covering the peripheral logic circuits. [0051] The electrode structure ST may include a cell electrode structure CST and a plurality of ground selection gate electrodes GGEla, GGElb, GGE2a and GGE2b provided between the cell electrode structure CST and the horizontal semiconductor layer 100. The plurality of ground selection gate electrodes GGEla, GGElb, GGE2a and GGE2b may include a plurality of first ground selection gate electrodes GGEla and GGElb disposed on the first cell array region CARl and a plurality of second ground selection gate electrodes GGE2a and GGE2b disposed on the second cell array region CAR2.”; a semiconductor memory device on a substrate arranged with a peripheral connection scheme; that the memory device comprises multiple gate layers stacked on the substate; in figure 8 and 12, at least two conductive, nearly identical, conductive patterns exist to control the two memory blocks using different bitlines and vertical structures for gate control, with perhaps a common source line. Note; applicant’s “first gate” and “second gate” could be two source line gates, or two drain gates, they are not limited to different functions, merely separated by geometry).
a channel layer penetrating the plurality of interlayer insulating layers and the plurality of conductive patterns; and (Baek, fig 5, 6, 7, 8, “[0049] Referring to FIGS. 5 and 6, the horizontal semiconductor layer 100 may include the first and second connection regions CNRl and CNR2, the first and second cell array regions CARl and CAR2, and/or the common connection region CNR3, as described above.”; that the connectors have multiple pads to connect each individual memory block, that each of the gate structures can be adjacent to each other on this surface to control the device).
a memory layer surrounding a sidewall of the channel layer. (Baek, fig 5, 6, 7, 8, “[0071] A cell array structure CS may be disposed on the peripheral buried insulating layer 50 and may include a horizontal semiconductor layer 100, an electrode structure ST, vertical structures VSl and VS2, and through-interconnection structures TSl, TS2, TS3 and TS4 connecting the cell array structure CS and the peripheral logic structure PS.”; that each of the pass transistors have an associated vertical structure VS1/2 and through interconnection structure TS1-4, that these structures “overlap” at least a portion of the gate stack structure to connect with the controlling gates for each pillar).
Regarding claim 19, Baek teaches:
The semiconductor memory device of claim 18, further comprising: a source layer in contact with the channel layer, the source layer extending to overlap with the vertical conductive line; and (Baek, fig 8, 12, “[0089] Referring to FIGS. llA, 11B, llC and 12, according to some embodiments, gate separation regions penetrating the electrode structure ST may be provided on the first and second cell array regions CARl and CAR2. Common source regions CSR may be provided in the horizontal semiconductor layer 100 under the gate separation regions penetrating the electrode structure ST. [0090] The gate separation regions may extend in the first direction Dl, and some of the gate separation regions may have different lengths in the first direction Dl. Each of the cell gate electrodes CGE may have a portion that overlaps with an empty space between adjacent ground selection gate electrodes GGEla, GGElb, GGE2a and GGE2b when viewed in a plan view.”; the at least two memory blocks of figs 8 and 12, each with multiple types of circuits to include ground gates, common source lines, source gates, and at least memory gates, are all wired in the vertical from the peripheral region).
a vertical insulating layer extending along surfaces of the vertical conductive line, which face the plurality of interlayer insulating layers, the plurality of conductive patterns, and the source layer. (Baek, fig 5, 6, 7, 8, 12, “[0079] An upper planarization insulating layer 150 may be disposed on the lower planarization insulating layer 120 to cover the stepped structures of the cell electrode structure CST.”; multiple layers of insulating layer 150 between each of the vertical columns).
Regarding claim 20, Baek teaches The semiconductor memory device of claim 19, wherein the vertical insulating layer is thicker than the memory layer. (Baek, fig 8, 12, “[0088] The fourth through-interconnection structure TS4 may be provided on the common connection region CNR3 and may connect the second pads P2 of the second ground selection gate electrodes GGE2a and GGE2b to the fourth pass transistors PT4. The fourth through-interconnection structure TS4 may include fourth contact plugs PLG4 connected to the second pads P2 of the second ground selection gate electrodes GGE2a and GGE2b, fourth through-plugs THV4 penetrating the upper and lower planarization insulating layers 150 and 120 and the peripheral buried insulating layer 50 so as to be connected to the peripheral interconnection lines 33, and fourth connection lines CL4 connecting the fourth contact plugs PLG4 to the fourth through-plugs THV4.”; the vertical lines to the PT-1-4 are surrounded by the insulating material 150 from the bottom of the substrate to the top, that the layer 150 is much thicker than the insulation between the individual memory layers).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825