DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species of Figures 1-6, Claims 1-10 in the reply filed on 5/13/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakashiba [US 2010/0264515A1] in view of Sujan et al. [EP 3,503,417 A1].
Regarding claim 1, Nakashiba discloses a semiconductor device [figures 1-5] comprising:
- a first semiconductor chip including a first coil [302] that generates a magnetic field signal;
- a wiring board [602] including a second coil [304], a third coil [324], and a pair wiring connections connecting the second coil to the third coil [figure 3], the second coil being disposed to face the first coil and receiving the magnetic field signal generated by the first coil; and
- a second semiconductor chip including a fourth coil [322] disposed to face the third coil and receiving a magnetic field signal generated by the third coil.
Nakashiba disclose the instant claimed invention except for the wiring connections being twisted.
Sujan et al. discloses an electronic structure [figure 1] comprising a first coil [coil of node 10c] and a second coil [coil of node 20c], wherein the first coil and the second coil being connected a twisted pair [15] through which equivalent electric current flows in opposite directions.
It would have been an obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to use the twisted connection of Sujan et al. in Nakashiba for the purpose of facilitating/improving electromagnetic compatibility and reducing noise.
Claim(s) 2 and 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakashiba in view of Sujan et al. as applied to claim 1 above, and further in view of JPS58-142959U.
Regarding claim 2, Nakashiba in view of Sujan et al. disclose the instant claimed invention except for the specific of the twisted arrangement/connection.
JPS58-142959U discloses a wiring board [1, figures 1-3] comprising at least one electronic component [2], input/output terminals [3] and twisted connection wirings [6, 7/7’/7”/7”’/8/9], wherein the twisted connection wiring includes a first wiring layer including a plurality of first wiring patterns [8 or 9], a second wiring layer including a plurality of second wiring patterns [8 or 9], and a connection wiring layer formed between the first wiring layer and the second wiring layer, the connection wiring layer including a plurality of connection wiring patterns [7, 7’, 7”, 7”’] each of which connects each of the plurality of first wiring patterns with each of the plurality of second wiring patterns.
It would have been an obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to use the twisted connection wirings of JPS58-142959U in the wiring board of Nakagawa for the purpose of facilitating and/or improving connection.
Regarding claim 4, JPS58-142959U discloses the second wiring layer and the connection wiring layer formed an integral wiring layer.
Regarding claim 5, JPS58-142959U further discloses the first wiring layer [8] is formed on a first principal surface of a substrate [1], the second wiring layer [9] is formed on a second principal surface of the substrate on a side opposite to the first principal surface, and the connection wiring layer [7, 7’, 7”, 7”’] is formed of a plurality of through wirings formed in the substrate.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakashiba in view of Sujan et al. and JPS58-142959U as applied to claims 1-2 above, and further in view of Yen et al. [US 2019/0148479 A1].
Regarding claim 3, Nakagawa, as modified, disclose the instant claimed invention except for the specific of the second coil.
Yen et al. discloses an integrated structure [figures 1-3] comprising:
- a plurality of layers of a printed circuit board;
- first and second coils [500, 600] formed on the plurality of layers of the printed circuit board, wherein the first and second coils being connected by a twisted/crossed connection structure [A1, A2, B1, B2, figures 1-3].
It would have been an obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to use the coil’s arrangement of Yen et al. for the second/third coils of Nakagawa et al. for the purpose of facilitating manufacturing and/or connections.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa [WO 2010-101222 A1] in view of Sujan et al. [EP 3,503,417 A1].
Regarding claim 6, Nakagawa discloses a semiconductor device [figure 18] comprising:
- a first semiconductor chip [31] including a first coil [Lt] that generates a magnetic field signal;
- a wiring board [37] including a second coil [Lr] and a pair connection wiring [35, 36], the second coil being disposed to face the first coil and receiving the magnetic field signal generated by the first coil, the pair wiring being connected with the second coil; and
- a second semiconductor chip [32a] connected with the pair wiring.
Nakagawa disclose the instant claimed invention except for the pair connection wirings are twisted.
Sujan et al. discloses an electronic structure [figure 1] comprising a first coil [coil of node 10c] and a second coil [coil of node 20c], wherein the first coil and the second coil being connected a twisted pair [15] through which equivalent electric current flows in opposite directions.
It would have been an obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to use the twisted connection of Sujan et al. in Nakashiba for the purpose of facilitating/improving electromagnetic compatibility and reducing noise.
Claim(s) 7 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakashiba in view of Sujan et al. as applied to claim 6 above, and further in view of JPS58-142959U.
Regarding claim 7, Nakashiba in view of Sujan et al. disclose the instant claimed invention except for the specific of the twisted pair connection.
JPS58-142959U discloses the twisted pair connection wirings includes a first wiring layer including a plurality of first wiring patterns [8], a second wiring layer including a plurality of second wiring patterns [9], and a connection wiring layer formed between the first wiring layer and the second wiring layer, the connection wiring layer including a plurality of connection wiring patterns [7, 7’, 7”, 7”’] each of which connects each of the plurality of first wiring patterns with each of the plurality of second wiring patterns.
It would have been an obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to use the twisted pair connection and/or arrangement of JPS58-142959U in Nakashiba in view of Sujan et al., for the purpose of facilitating internal connection in semiconductor.
Regarding claim 9, JPS58-142959U the second wiring layer and the connection wiring layer form an integral wiring layer.
Regarding claim 10, JPS58-142959U further discloses the first wiring layer [8] is formed on a first principal surface of a substrate [1], the second wiring layer [9] is formed on a second principal surface of the substrate on a side opposite to the first principal surface, and the connection wiring layer [7, 7’, 7”, 7”’] is formed of a plurality of through wirings formed in the substrate.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa in view of Sujan et al. and JPS58-142959U as applied to claims 6-7 above, and further in view of Yen et al. [US 2019/0148479 A1].
Regarding claim 8, Nakagawa, as modified, disclose the instant claimed invention except for the specific of the second coil.
Yen et al. discloses an integrated structure [figures 1-3] comprising:
- a plurality of layers of a printed circuit board;
- first and second coils [500, 600] formed on the plurality of layers of the printed circuit board, wherein the first and second coils being connected by a twisted/crossed connection structure [A1, A2, B1, B2, figures 1-3].
It would have been an obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to use the coil’s arrangement of Yen et al. for the second/third coils of Nakagawa et al., as modified, for the purpose of facilitating manufacturing and/or connections.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TUYEN T NGUYEN/Primary Examiner, Art Unit 2837