DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments (Applicant’s Remarks pages 8-9) that the limitations “a first bit line is connected to one of the plurality of first columnar portions and between the first memory cell array and the second memory cell array, a second bit line is connected to one of the plurality of second columnar portions and between the second memory cell array and the second substrate” introduced in the most amendment to claim 1 are not taught by the prior art of record (specifically US 20220102334 A1 (Kim et al) in view of US 20230005862 A1 (Wang et al) and US 20220077126 A1 (Choi et al)).
While the examiner agrees that Kim et al, Wang et al, and Choi et al do not teach or obviously suggest the foregoing limitations, after further search and consideration it was found that US patent US 10283493 B1 (Nishida), particularly its FIG. 27 embodiment, would render those limitations obvious since it teaches a configuration of memory devices wherein two memory cell regions (FIG. 27, memory regions 100 and contact regions 200 in both of dies 1000 and 3000) are stacked atop each other, and both have the same orientation of their features, as opposed to the inverted orientation shown in Choi et al FIGS. 3-4.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-8, 11-12, 14-16, 18-19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publications US 20220102334 A1 (Kim et al hereinafter Kim) in view of US 20230005862 A1 (Wang et al hereinafter Wang) and US patent US 10283493 B1 (Nishida).
Regarding claim 1, Kim discloses a semiconductor device (FIGS. 4-6D semiconductor device 100 ¶ [0013-0016, 0052-0089]; also FIG. 1 semiconductor device 10, wherein FIG. 1’s memory cell 20 corresponds to the conductive plate and cell array structure of FIG. 4 ¶ [0053]), comprising: a first substrate (FIG. 5B, first peripheral circuit substrate 212 ¶ [0060]); a plurality of first electrode layers (FIG. 5B, gate lines 130 ¶ [0055]) above the first substrate in a first direction (FIG. 5B, the vertical/Z direction ¶ [0055]), the electrode layers separated from each other in the first direction (FIG. 5B, they are separated by insulating films 156 ¶ [0078]); a plurality of first plugs (FIG. 5B, each of a plurality of CTS2 include first contact plug 126A ¶ [0096) on upper surfaces or lower surfaces of the first plurality of electrode layers (FIG. 5B, upper surfaces of gate lines 130); a plurality of first columnar portions (FIG. 5B, channel structures 180, ¶ [0079]) extending in the first direction through the plurality of first electrode layers (FIG. 5B, channel structures 180 extend along the Z direction through the gate lines 130), each first columnar portion including a first semiconductor layer (FIG. 5B, channel region 184 ¶ [0080], which may be doped or undoped polysilicon) and a first charge storage layer (FIG. 6A, charge storage film CS of 182 ¶ [0084]) that is between the first semiconductor layer and the plurality of first electrode layers (FIG. 6A, CS film of 182 is between gate electrodes 130 and semiconductor layer 184);
a second substrate (FIG. 5B, second peripheral substrate 222 ¶ [0066]) above the plurality of first electrode layers in the first direction (FIG. 5B, second substrate 222 is above gate lines 130 along the Z direction); a plurality of first transistors (FIGS. 5A-5B, first transistors TR1 in the A2-A2’/CON region, ¶ [0061-0062]) on an upper surface of the first substrate and electrically connected to the plurality of first plugs (FIG. 5B, TR1 on upper surface of first substrate 212 are connected to plugs 126A through 126B in the A2-A2’ region, ¶ [0114-0115, 0118]); and a plurality of second transistors (FIGS. 5A-5B, second transistors TR2 in A1-A1’/MEC region, ¶ [0067-0068]) on a lower surface of the second substrate and electrically connected to the plurality of first columnar portions (FIG. 5B, TR2 on lower surface of second substrate 222 in A1-A1’ region connect to channel structures 180 ¶ [0114-0115]);
a first memory cell array including the plurality of first electrode layers (FIG. 5B, memory cell array MCA includes gate electrodes 130 ¶ [0072-0073]); a row decoder (FIG. 1, row decoder 32, ¶ [0031-0034]) including the first transistors and on the upper surface of the first substrate (row decoder 32 includes some first transistors TR1 in region PE1, ¶ [0118]); and a sense amplifier (FIG. 1, page buffer 34 may operate as a sense amplifier ¶ [0035]) including the second transistors on the lower surface of the second substrate (FIG. 5B, page buffer 34 is connected to channel structure 180 in second circuit region PE2 via some of second transistors TR2 in the A1-A1’ region ¶ [0115]); a first bit line (FIG. 5B, a bit line BL connected to a channel structure 180 ¶ [0115]) is connected to one of the plurality of first columnar portions; a film thickness of a gate insulating film of the first transistors is thicker than a film thickness of a gate insulating film of the second transistors (¶ [0116] describes operating voltages of first transistors TR1 and second transistors TR2 may differ, and that this may be achieved by having the first transistors TR1 in region PE1 to have a thicker oxide in their MOS structure than the corresponding oxide thickness in the second transistors TR2 in region PE2).
Kim does not explicitly teach that the first substrate is thicker than the second substrate, or that all row decoders connected to the plurality of electrode layers of the memory cell array are formed on the first substrate, and does not further disclose a plurality of second electrode layers above the plurality of first electrode layers in the first direction, the second electrode layers separated from each other in the first direction, a second memory cell array including the plurality of second electrode layers, wherein a first bonding surface is between the first memory cell array and the second memory cell array, a second bonding surface is between the second memory cell array and the plurality of second transistors, or a plurality of second columnar portions extending in the first direction through the plurality of second electrode layers, each second columnar portion including a second semiconductor layer and a second charge storage layer that is between the second semiconductor layer and the plurality of second electrode layers, wherein the first bit line is between the first memory cell array and the second memory cell array, a second bit line is connected to one of the plurality of second columnar portions and between the second memory cell array and the second substrate.
While Kim is silent regarding the relative thicknesses of the substrates underlying the transistors, Kim does teach that the operating voltages of the first transistors TR1 on the first substrate may differ from those of the second transistors TR2 on the second substrate, such as by having an oxide thickness of each MOS transistor on the first substrate in the PE1 region to be thicker than those of the MOS transistors on the second substrate in the PE2 region (¶ [0116-0117]). For the first transistors TR1 to have thicker gate oxide layers, a person of ordinary skill in the art would find that, since the higher voltage transistors TR1 on the first substrate have higher breakdown voltages due to their thicker oxide layers, a thicker substrate would be appropriate to accommodate the higher breakdown voltage. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Kim such that the first substrate is thicker than the second substrate, in order to accommodate the higher breakdown voltages of the transistors in the PE1 region.
Kim does not teach that all row decoders connected to the plurality of electrode layers of the memory cell array are formed on the first substrate.
However, Wang discloses a semiconductor device (the device of FIGS. 10-11B) comprising a row decoder (FIG. 11A, first peripheral circuit 1104 can include high voltage HV circuits such as a row decoder ¶ [0119]) and a page buffer (FIG. 11A, fourth peripheral circuit 1118 can include low voltage LV circuits such as a page buffer ¶ [0129]), wherein all row decoders connected to a plurality of electrode layers (row decoder 308 drives memory cells 206 by being coupled to word lines 218 of FIG. 2’s circuit diagram ¶ [0083]) of a memory cell array (FIG. 11A, memory stack 1127, noted to have the structure shown in FIG. 8 ¶ [0123]) are formed on a first substrate (FIG. 11A, semiconductor layer 1002, understood to constitute a substrate, includes all of the HV circuits of the row decoder by having HV peripheral circuit 1104 ¶ [0111, 0119]), and the page buffer may be formed on a second substrate (FIG. 11A, semiconductor layer 1004 may be a silicon substrate, and may include LV page buffer circuits in fourth peripheral circuit 1118 ¶ [0114, 0129]). Wang also teaches that the row decoder transistors may operate at a high voltage to function as driving circuits (¶ [0119]) and should be separated from low low voltage LLV circuits due to their significant difference in voltages and the resulting difference in device dimensions, such as different substrate thicknesses and different gate dielectric thicknesses, going so far as to mention that the HV circuits (including the row decoder) may be formed on a thicker substrate than the LLV circuits to achieve desirable electrical properties (¶ [0091]), to optimize the performance of the various peripheral circuits (e.g. HV driving circuits such as row decoders, LV circuits such as page buffers, and LLV circuits such as I/O circuits ¶ [0090]). Such an arrangement of separating high voltage transistors from low voltage transistors was also taught by Kim (Kim ¶ [0040-0041]). Since Wang has demonstrated that a configuration wherein all row decoders connected to the plurality of electrode layers of the memory cell array are formed on the first substrate, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found such a configuration an obvious design alternative in the context of the device of Kim, in order to optimize the performance of the various peripheral circuits having different voltage requirements (Kim ¶ [0040-0041, 0116-0117], Wang ¶ [0090]).
Kim and Wang both pertain to the field of memory devices including multiple substrates comprising logic circuitry, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Kim in view of Wang such that all row decoders connected to the plurality of electrode layers of the memory cell array are formed on the first substrate, as such a configuration is a known design alternative in the art which could optimize the performance of the various peripheral circuits having different voltage requirements.
Kim in view of Wang do not further disclose a plurality of second electrode layers above the plurality of first electrode layers in the first direction, the second electrode layers separated from each other in the first direction, a second memory cell array including the plurality of second electrode layers, a plurality of second columnar portions extending in the first direction through the plurality of second electrode layers, each second columnar portion including a second semiconductor layer and a second charge storage layer that is between the second semiconductor layer and the plurality of second electrode layers, wherein the first bit line is between the first memory cell array and the second memory cell array, a second bit line is connected to one of the plurality of second columnar portions and between the second memory cell array and the second substrate wherein a first bonding surface is between the first memory cell array and the second memory cell array, a second bonding surface is between the second memory cell array and the plurality of second transistors.
However, Nishida discloses a memory device (FIG. 27, dies 1000 and 3000 Col. 38 lines 25-44) wherein it is demonstrated that a plurality of memory cell structures may be stacked onto one another (FIG. 27, memory regions 100 in both of dies 1000 and 3000 Col. 9 lines 41-55), and those memory cell structures are each oriented in the same manner (FIG. 27 shows the memory regions 100 and contact regions 200 have the same configuration as they are stacked onto each other, as opposed to for example the embodiment of FIG. 29 in which have an inverted configuration). Stacking multiple cell array chips would also increase the density of the device’s functional elements, improving the compactness of the device, a recognized goal in the art (Col. 1 lines 15-17). Kim, Wang, and Nishida all pertain to the field of memory devices including multiple substrates comprising logic circuitry, placing them in the same field of endeavor as the claimed invention. Since Nishida has demonstrated such a stacking of cell arrays to be known in the art, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Kim in view of Wang further in view of Nishida by duplicating the cell region CELL of Kim and disposing it between the illustrated cell region CELL and peripheral circuit region PE 2 of Kim FIG. 5B; it has been found that a mere duplication of parts has no patentable significance unless a new and unexpected result is produced (MPEP 2144.04 VI. B).
Having done so, Kim in view of Wang and Nishida further discloses a plurality of second electrode layers (Kim FIG. 5B, the second instance of cell region CELL formed in view of Nishida FIG. 27’s stack of cell array structures comprises gate lines 130 ¶ [0055]; the gate lines 130 of the second instance of CELL being located above the gate lines of the illustrated instance of CELL) above the plurality of first electrode layers in the first direction, the second electrode layers separated from each other in the first direction (FIG. 5B, gate lines 130 are separated by insulating films 156 ¶ [0078]), a second memory cell array (Kim FIG. 5B in view of Nishida FIG. 27, the second instance of CELL includes its gate lines 130) including the plurality of second electrode layers, a plurality of second columnar portions (Kim FIG. 5B, in the second instance of CELL, channel structures 180 extend along the Z direction through the gate lines 130 ¶ [0079]) extending in the first direction through the plurality of second electrode layers, each second columnar portion including a second semiconductor layer (Kim FIG. 5B, channel region 184 in the second instance of CELL ¶ [0080]) and a second charge storage layer (Kim FIG. 6A, charge storage CS film of 182 is between gate electrodes 130 and semiconductor layer 184 in the second instance of CELL ¶ [0084]) that is between the second semiconductor layer and the plurality of second electrode layers, wherein the first bit line is between the first memory cell array and the second memory cell array (Kim FIG. 5B, bit line BL is between the illustrated cell region CELL and the second instance of CELL which is located above the illustrated CELL in view of Nishida FIG. 27), a second bit line (FIG. 5B, a bit line BL connected to a channel structure 180 in the second instance of CELL ¶ [0115]) is connected to one of the plurality of second columnar portions and between the second memory cell array and the second substrate (Kim FIG. 5B, the bit line BL in the second instance of CELL is between the same CELL’s channel structures 180 and substrate 222) wherein a first bonding surface (Kim FIG. 5B in view of Nishida FIG. 27, an interface between the two CELL regions is a first bonding surface) is between the first memory cell array and the second memory cell array, a second bonding surface (Kim FIG. 5B in view of Nishida FIG. 27, an interface between the second instance of CELL and peripheral circuit region PE2 is a second bonding surface) is between the second memory cell array and the plurality of second transistors, in order to provide an increased density of memory elements in the device.
Regarding claim 4, Kim in view of Wang and Nishida discloses the limitations of claim 1 as detailed above and Kim further discloses a plurality of third transistors on the upper surface of the first substrate (FIG. 5B, first transistors TR1 not in A2-A2’/CON region), wherein the third transistors are portions of a peripheral circuit other than the row decoder (some first transistors TR1 may connect to the CSL driver 39 when they are high-voltage ¶ [0060, 0114, 0117]).
Regarding claim 5, Kim in view of Wang and Nishida discloses the limitations of claim 4 as detailed above and Kim further discloses that a film thickness of a gate insulating film of the third transistors is thicker than the film thickness of the gate insulating film of the second transistors (the “third-transistors” grouping of the set of transistors TR1 may have a thicker oxide in their MOS structure than the corresponding oxide thickness in the second transistors TR2 in region PE2, ¶ [0116]).
Regarding claim 6, Kim in view of Wang and Nishida discloses the limitations of claim 4 as detailed above and Kim further discloses a plurality of fourth transistors on the lower surface of the second substrate (FIG. 5B, second transistors TR2 not in A1-A1’/MEC region), wherein the fourth transistors are portions of the peripheral circuit other than the sense amplifier (some second transistors TR2 may connect to the CSL driver 39 or the data I/O circuit 36 ¶ [0066, 0114, 0117]).
Regarding claim 7, Kim in view of Wang and Nishida discloses the limitations of claim 6 as detailed above and Kim further discloses that the film thickness of the gate insulating film of the first transistors is thicker than a film thickness of a gate insulating film of the fourth transistors (the “fourth-transistors” grouping of the set of transistors TR2 may have a thinner oxide in their MOS structure than the corresponding oxide thickness in the first transistors TR1 in region PE1, ¶ [0116]).
Regarding claim 8, Kim in view of Wang and Nishida discloses the limitations of claim 1 as detailed above and Kim further discloses a plurality of first pads (FIG. 5B, first bonding metal pads 178 between gate lines 130 and second substrate 222 ¶ [0059]) between the plurality of first electrode layers and the second substrate; and a plurality of second pads (FIG. 5B, second bonding metal pads 278 on first pads 178 ¶ [0059]) on the plurality of first pads, wherein the second transistors are electrically connected to the first columnar portions via a first pad and a second pad (FIG. 5B, bonding pads 178 and 278 connect to second transistors TR2 through conductive lines 228 and plugs 226, ¶ [0068-0070]).
Regarding claim 11, Kim in view of Wang and Nishida discloses the limitations of claim 1 as detailed above and Kim further discloses that the plurality of first electrode layers comprises a first portion (FIGS. 5A-5B, the memory cell region MEC including the A1-A1’ region ¶ [0057]) and a second portion (FIGS. 5A-5B, the connection region CON including the A2-A2’ region, ¶ [0057]) adjacent to the first portion in a second direction intersecting the first direction (FIGS. 5A-5B, the horizontal/X direction), the plurality of first columnar portions are in the first portion of the plurality of first electrode layers (FIGS. 5A-5B, channel structures 180 are in the MEC region), and the plurality of first plugs are on an upper surface or a lower surface of the second portion of the plurality of first electrode layers (FIGS. 5A-5B, plugs 126A are on upper surfaces of gate electrodes 130 in the CON region).
Regarding claim 12, Kim in view of Wang and Nishida discloses the limitations of claim 11 as detailed above and Kim further discloses that the plurality of first transistors includes at least one transistor positioned directly under the second portion in the first direction (FIG. 5B, the first transistor TR1 located on the right end of region A2-A2’ is directly under the second CON portion along the Z-direction).
Regarding claim 14, Kim in view of Wang and Nishida discloses the limitations of claim 12 as detailed above and Kim further discloses a plurality of third transistors on the upper surface of the first substrate (FIG. 5B, transistors TR1 not in A2-A2’ region; they are on upper surface of first substrate 212), wherein the plurality of third transistors includes at least one transistor positioned directly under the first portion in the first direction (FIG. 5B, the transistor TR1 located in region A1-A1’).
Regarding claim 15, Kim in view of Wang and Nishida discloses the limitations of claim 11 as detailed above and Kim further discloses that the plurality of second transistors includes a transistor positioned directly above the first portion in the first direction (FIG. 5B, second transistor TR2 in the A1-A1’ region is directly above the first MEC portion along the Z-direction).
Regarding claim 16, Kim in view of Wang and Nishida discloses the limitations of claim 15 as detailed above and Kim further discloses a plurality of fourth transistors on the lower surface of the second substrate (FIG. 5B, second transistors TR2 not in A1-A1’ region; they are on lower surface of second substrate 222), wherein the plurality of fourth transistors includes a transistor positioned directly above the second portion in the first direction (FIG. 5B, any of the three transistors TR2 in the A2-A2’ region).
Regarding claim 18, Kim in view of Wang and Nishida discloses the limitations of claim 11 as detailed above and Kim further discloses that the row decoder has a portion directly under the second portion in the first direction (FIG. 5B, any of the first transistors TR1 under the second portion in the A2-A2’ region may be part of row decoder 32, ¶ [0118]), and the sense amplifier includes a portion directly above the first portion in the first direction (FIG. 5B, second transistor TR2 in the A1-A1’/MEC region, directly above the first MEC portion along the Z-direction, may be connected to the page buffer/sense amplifier ¶ [0115]).
Regarding claim 19, Kim in view of Wang and Nishida discloses the limitations of claim 18 as detailed above, and Kim further discloses a plurality of first pads (FIG. 5B, lower conductive lines 218 ¶ [0061-0062]) between the first substrate and the plurality of first electrode layers (FIG. 5B, lower conductive lines 218 are between first peripheral circuit substrate 212 and gate lines 130); and a plurality of second pads (FIG. 5B, second bonding metal pads 278 are located on lower conductive lines 218, ¶ [0059]) on the plurality of first pads, wherein the plurality of first pads include: first pads directly above the row decoder and electrically connected to the row decoder, and first pads directly under the sense amplifier and electrically connected to the sense amplifier; and the plurality of second pads include: second pads directly above the row decoder and electrically connected to the row decoder, and second pads directly under the sense amplifier and electrically connected to the sense amplifier.
Kim does not explicitly disclose that the plurality of first pads include: first pads directly above the row decoder and electrically connected to the row decoder, and first pads directly under the sense amplifier and electrically connected to the sense amplifier; and the plurality of second pads include: second pads directly above the row decoder and electrically connected to the row decoder, and second pads directly under the sense amplifier and electrically connected to the sense amplifier.
However, regarding the limitations “first pads directly under the sense amplifier and electrically connected to the sense amplifier” and “second pads directly under the sense amplifier and electrically connected to the sense amplifier”, Kim does show that a first pad and second pad may be directly under a second transistor TR2 in the MEC/A1-A1’ region (FIG. 5B, the pad 278 and conductive line 218 over the middle channel structure 180). Further, Kim taught that some of the transistors TR2 may constitute part of the page buffer/sense amplifier (¶ [0035, 0114-0115]), and that the view of the A1-A1’ region shown in FIG. 5B may be repeated several times (FIGS. 5A-5B, the A1-A1’ region shown in FIG. 5B represents a cross-section of three channel structures 180, but FIG. 5A shows many more than three channel structures 180).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the disclosed device of Kim to ensure that a plurality of sets of first pads (FIG. 5B, 218) and second pads (FIG. 5B, 278) are directly under a plurality of second transistors TR2 in the memory cell region MEC (FIGS. 5A-5B), and for that plurality of transistors TR2 to partially constitute the sense amplifier (¶ [0035, 0114-0115), in order to configure sufficient connections to enable the sense amplifier’s functionality in keeping with the interconnection details taught by Kim; such modifications constitute an obvious design alternative achievable by a person of ordinary skill in the art. In so doing, the plurality of first pads includes first pads directly under the sense amplifier and electrically connected to the sense amplifier, and the plurality of second pads includes second pads directly under the sense amplifier and electrically connected to the sense amplifier.
Furthermore, “The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.” KSR International Co. v. Teleflex Inc., 550 U.S. 398, 420, 82 USPQ2d 1385, 1397 (2007).
The foregoing modification did not disclose that the plurality of first pads include: first pads directly above the row decoder and electrically connected to the row decoder and the plurality of second pads include: second pads directly above the row decoder and electrically connected to the row decoder.
However, Kim teaches a related embodiment of their invention (FIG. 7, semiconductor device 400, ¶ [0125-0132]) substantially similar to previously discussed FIGS. 5A-5B embodiment (¶ [0125-0126]). This embodiment further comprises a plurality of first pads between the first substrate and the plurality of electrode layers (FIG. 7, first bonding metal pads 478 between first substrate 212 and electrode layers 130, ¶ [0127]); and a plurality of second pads on the plurality of first pads (FIG. 7, second bonding metal pads 488 are on first pads 478, ¶ [0128]). These first and second pads 478/488 form bonding structures (FIG. 7, bonding structures BS4, ¶ [0129]) which are used to connect the first peripheral circuit region PE1 to the cell region CELL4 (¶ [0132]). Kim further teaches that a plurality of sets of pads 478/488 may be disposed directly above first transistors TR1 in the CON/A2-A2’ region (FIG. 7, the two rightmost bonding structures BS4/478/488 shown in the A2-A2’ cross-section region), and that first transistors TR1 may be included in the row decoder (¶ [0118]).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the disclosed device of Kim in view of the embodiment of FIG. 7 to further include pads 478 among the plurality of first pads and pads 488 among the plurality of second pads; this allows separate manufacturing of the cell region and the first peripheral region, and their subsequent bonding to form a chip to chip structure (¶ [0130]). A person of ordinary skill in the art before the effective filing date of the claimed invention would have further found it obvious to ensure that the plurality of first pad 478 – second pad 488 pairs are electrically connected to first transistors TR1 that partially constitute the row decoder (¶ [0132], BS4 structures provide connection to lower circuits CT1 comprising TR1), and that the first transistors TR1 that they are directly above also partially constitute the row decoder, in order to configure sufficient connections to enable the row decoder’s functionality in keeping with the interconnection details taught by Kim; such modifications constitute an obvious design alternative achievable by a person of ordinary skill in the art. In so doing, the plurality of first pads includes: first pads directly above the row decoder and electrically connected to the row decoder and the plurality of second pads includes: second pads directly above the row decoder and electrically connected to the row decoder.
Furthermore, “The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.” KSR International Co. v. Teleflex Inc., 550 U.S. 398, 420, 82 USPQ2d 1385, 1397 (2007).
Regarding claim 21, Kim in view of Wang and Nishida discloses the limitations of claim 1 as detailed above, and Kim further discloses a third bonding surface (FIG. 5B, a bonding surface between interlayer insulating film 219 and lower surfaces of cell structure 102 and insulating plugs 104 ¶ [0057, 0062-0063, 0101]; while bonding pads are not present, that surface bonds cell region CELL to first peripheral circuit region PE1; furthermore, the embodiment of FIG. 7 of Kim demonstrates that a configuration which uses bonding pads 478 and 488 between the first substrate 212 and cell region CELL is known and compatible with their disclosure ¶ [0127-0128]) is between the first memory cell array and the plurality of first transistors (FIG. 5B, the bonding surface interface of interlayer insulating film 219 and lower surfaces of cell structure 102 and insulating plugs 104 is between the first transistors TR1 and first memory cell array in cell region CELL).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD RHETT CHEEK whose telephone number is (571)272-3461. The examiner can normally be reached Monday - Thursday 7:30am - 5pm, Every other Friday 8:30am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights