Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 8, 2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 and 9 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding Claims 1 and 9, the instant application shows a gate layer comprising a conductive material extending continuous over a first semiconductor region and a second semiconductor region (interpreted as the gate electrode material extending over a first fin and second fin respectively, as shown in the intermediate stage of Fig. 4B) and subsequently being interrupted by an isolation structure (shown Fig. 9B). It is unclear how the conductive material of the final structure is intended to be interpreted as continuous as at least a portion of the conductive material is interrupted to form the isolation feature (902 and 1002, see also Fig. 10B).
For examination purposes, it is understood that “a conductive material extending continuous over a first semiconductor region and a second semiconductor region” is interpreted to mean a conductive material extends over a first semiconductor region and a second semiconductor region.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 6-7, 9, 11 and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ng (DE 102020115785 A1). Ng (US 20220359506 A1) is deemed an equivalent disclosure and is cited herein for clarity.
Regarding Claim 1, Ng teaches an integrated circuit (see device of Figs. 14-1 and 14-2, see also [0002] describing the semiconductor device shown being applied to low-power integrated circuits) comprising:
a semiconductor device (30) having a first subfin region (region between STIs 124 under second fin 120, shown Fig. 14-2) and a first semiconductor region (120) above the first subfin region and a second subfin (region under fin 118) and a second semiconductor region (118) above the second subfin region, the first and second semiconductor regions extending in a first direction (x-direction, shown Fig. 14-1, see also [0021]) between a source region and a drain region (see [0021]);
a dielectric layer (124, an STI region) adjacent to the first subfin region and the second subfin region (shown Fig. 14-2);
a gate structure (shown Fig. 14-3 including layers 162, 164 and 166) comprising a gate dielectric (162) and a gate layer(166), the gate layer comprising a conductive material (see [0073] describing a metal gate electrode) extending continuous over the first semiconductor region and the second semiconductor region (see Fig. 2I-1) in a second direction (y-direction) different from the first direction;
spacer structures (164) on sidewalls of the gate structure (shown Fig. 14-3); and
an isolation structure (148, 150 and 174A, shown Fig. 14-2) between the spacer structures (shown Fig. 14-1) and interrupting the gate layer (shown Fig. 14-1), the isolation structure extending through at least a portion of the dielectric layer (shown Fig. 14-2), wherein the isolation structure abuts a third semiconductor region (portion of 118, shown Fig. 14-1) extending parallel to the first semiconductor region and the second semiconductor region (shown Fig. 14-1) in the first direction, and wherein the gate layer abuts at least a portion of the isolation structure (shown Fig. 14-1).
Regarding Claim 3, Ng teaches the integrated circuit of claim 1, wherein the isolation structure comprises silicon and nitrogen or comprises silicon and oxygen (see described in [0060]).
Regarding Claim 4, Ng teaches the integrated circuit of claim 1, further comprising a gate cut adjacent to the isolation structure, wherein the gate cut interrupts the gate layer and the spacer structures (174, shown Fig. 14-1).
Regarding Claim 6, Ng teaches the integrated circuit of claim 1, wherein the isolation structure extends through an entire thickness of the dielectric layer (shown Fig. 14-2).
Regarding Claim 7, Ng teaches the integrated circuit of claim 1, wherein no dielectric layers are present between the gate layer and the isolation structure (shown Fig. 14-1).
Regarding Claim 9, Ng teaches an electronic device, comprising:
a chip package (see described in [0017]) comprising one or more dies, at least one of the one or more dies comprising:
a semiconductor device (30) having a first subfin region (region between STIs 124 under second fin 120, shown Fig. 14-2) and a first semiconductor region (120) above the first subfin region and a second subfin (region under fin 118) and a second semiconductor region (118) above the second subfin region, the first and second semiconductor regions extending in a first direction (x-direction, shown Fig. 14-1, see also [0021]) between a source region and a drain region (see [0021]);
a dielectric layer (124, an STI region) adjacent to the first subfin region and the second subfin region (shown Fig. 14-2);
a gate structure (shown Fig. 14-3 including layers 162, 164 and 166) comprising a gate dielectric (162) and a gate layer(166), the gate layer comprising a conductive material (see [0073] describing a metal gate electrode) extending continuous over the first semiconductor region and the second semiconductor region (see Fig. 2I-1) in a second direction (y-direction) different from the first direction;
spacer structures (164) on sidewalls of the gate structure (shown Fig. 14-3); and
an isolation structure (148, 150 and 174A, shown Fig. 14-2) between the spacer structures (shown Fig. 14-1) and interrupting the gate layer (shown Fig. 14-1), the isolation structure extending through at least a portion of the dielectric layer (shown Fig. 14-2), wherein the isolation structure abuts a third semiconductor region (portion of 118, shown Fig. 14-1) extending parallel to the first semiconductor region and the second semiconductor region (shown Fig. 14-1) in the first direction, and wherein the gate layer abuts at least a portion of the isolation structure (shown Fig. 14-1).
Regarding Claim 11, Ng teaches the electronic device of claim 9, wherein the at least one or more dies further comprises a gate cut (174) adjacent to the isolation structure, wherein the gate cut interrupts the gate layer and the spacer structures (shown Fig. 14-1).
Regarding Claim 13, Ng teaches the electronic device of claim 9, wherein the isolation structure extends through an entire thickness of the dielectric layer (shown Fig. 14-2).
Regarding Claim 14, Ng teaches the electronic device of claim 9, wherein no dielectric layers are present between the gate layer and the isolation structure.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 8 and 10 are rejected under 35 U.S.C. 103 as being obvious over Ng (DE 102020115785 A1). Ng (US 20220359506 A1) is deemed an equivalent disclosure and is cited herein for clarity.
Regarding Claim 2, Ng teaches the integrated circuit of claim 1, wherein the second region comprises a plurality of semiconductor nanoribbons (see Fig. 1) and the first region is a single-channel fin structure. Ng does not explicitly teach both the first region and the second region comprising a plurality of semiconductor nanoribbons.
However, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the first semiconductor region or Ng to additionally be configured as a nanosheet FET structure as these are a known advantageous design choice owing to their higher speed, lower power consumption and reduced footprint compared to FinFETs (see also evidenced by Slovick, From FinFETs to Nanosheets: ICs Evolve to Keep Pace with ‘Moore’s Law’, 2021).
Specifically, this modification would teach a first semiconductor region comprising a first plurality of semiconductor nanoribbons and the second semiconductor region comprising a second plurality of semiconductor nanoribbons.
Regarding Claim 8, Ng teaches the integrated circuit of claim 1, but does not explicitly describe the integrated circuit being implemented on a printed circuit board.
However, printed circuit boards are well known in the art as being implemented as part of a compete chip package (see also [0017] of Ng which discloses the integrated circuit being implemented on a chip). Thus, it would be obvious to one of ordinary skill in the art prior to the effective fling date of the instant application to incorporate the integrated circuit described by Ng on a printed circuit board.
Regarding Claim 10, Ng teaches the electronic device of claim 9, wherein the second region comprises a plurality of semiconductor nanoribbons (see Fig. 1) and the first region is a single-channel fin structure. Ng does not explicitly teach both the first region and the second region comprising a plurality of semiconductor nanoribbons.
However, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the first semiconductor region or Ng to additionally be configured as a nanosheet FET structure as these are a known advantageous design choice owing to their higher speed, lower power consumption and reduced footprint compared to FinFETs (see also evidenced by Slovick, From FinFETs to Nanosheets: ICs Evolve to Keep Pace with ‘Moore’s Law’, 2021).
Specifically, this modification would teach a first semiconductor region comprising a first plurality of semiconductor nanoribbons and the second semiconductor region comprising a second plurality of semiconductor nanoribbons.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ng (DE 102020115785 A1) in further view of Hong (US 20190348414 A1). Ng (US 20220359506 A1) is deemed an equivalent disclosure to Ng (DE 102020115785 A1) and is cited herein for clarity.
Regarding Claim 5, Ng teaches the integrated circuit of claim 1, but does not explicitly teach at least a portion of the gate layer being present between a sidewall of the isolation structure and one of the spacer structures.
Hong teaches a similar integrated circuit comprising:
a semiconductor device (see Figs. 24-26) having a subfin region (105b) and a first semiconductor region (105a) above the subfin region and extending in a first direction between a source region and a drain region (190);
a dielectric layer (120, an STI region) adjacent to the subfin region (shown Fig. 24);
a gate structure (280, shown Fig. 26) comprising a gate dielectric (250) and a gate layer (260 and 270), the gate layer comprising a conductive material (see [0057]) and extending over the semiconductor region in a second direction (shown Fig. 26) different from the first direction;
spacer structures (170) on sidewalls of the gate structure (shown Fig. 26); and
an isolation structure (230) between the spacer structures (shown Fig. 26) and interrupting the gate layer (shown Fig. 26).
As described in paragraphs [0075-0077], the isolation structure may have an elliptical shape because of the way an etching gas inflows to form a trench opening, which enables an integrated circuit wherein a distance between neighboring fins may be small while a contact area between the gate electrode and active fins is maintained such that a threshold voltage distribution does not disadvantageously increase and the isolation structure completes isolation of the gate electrode along the second direction (see also [0061], [0070] and[0099]).
Thus, it would be obvious to one of ordinary skill in the art to modify the isolation structure of Ng to be formed in an elliptical shape when viewed in plan as suggested by the isolation structure of Hong to implement a dielectric isolation having relatively small width while maintaining a gate electrode interruption and further downsizing the integrated circuit.
Specifically, this modification would teach at least a portion of the gate layer being present between a sidewall of the isolation structure and one of the spacer structures (as shown along the first direction of Fig. 26 of Hong).
Regarding Claim 12, Ng teaches the electronic device of claim 9, but does not explicitly teach at least a portion of the gate layer being present between a sidewall of the isolation structure and one of the spacer structures.
Hong teaches a similar integrated circuit comprising:
a semiconductor device (see Figs. 24-26) having a subfin region (105b) and a first semiconductor region (105a) above the subfin region and extending in a first direction between a source region and a drain region (190);
a dielectric layer (120, an STI region) adjacent to the subfin region (shown Fig. 24);
a gate structure (280, shown Fig. 26) comprising a gate dielectric (250) and a gate layer (260 and 270), the gate layer comprising a conductive material (see [0057]) and extending over the semiconductor region in a second direction (shown Fig. 26) different from the first direction;
spacer structures (170) on sidewalls of the gate structure (shown Fig. 26); and
an isolation structure (230) between the spacer structures (shown Fig. 26) and interrupting the gate layer (shown Fig. 26).
As described in paragraphs [0075-0077], the isolation structure may have an elliptical shape because of the way an etching gas inflows to form a trench opening, which enables an integrated circuit wherein a distance between neighboring fins may be small while a contact area between the gate electrode and active fins is maintained such that a threshold voltage distribution does not disadvantageously increase and the isolation structure completes isolation of the gate electrode along the second direction (see also [0061], [0070] and[0099]).
Thus, it would be obvious to one of ordinary skill in the art to modify the isolation structure of Ng to be formed in an elliptical shape when viewed in plan as suggested by the isolation structure of Hong to implement a dielectric isolation having relatively small width while maintaining a gate electrode interruption and further downsizing the integrated circuit.
Specifically, this modification would teach at least a portion of the gate layer being present between a sidewall of the isolation structure and one of the spacer structures (as shown along the first direction of Fig. 26 of Hong).
Allowable Subject Matter
Claims 15-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 15, Ng (US 20220359506 A1) being the most relevant prior art of record teaches an integrated circuit (see device of Figs. 14-1 and 14-2, see also [0002] describing the semiconductor device shown being applied to low-power integrated circuits) comprising:
a semiconductor device (30) having a subfin region (region between STIs 124 under second fin 120, shown Fig. 14-2) and a first semiconductor region (120) above the subfin region and extending in a first direction (x-direction, shown Fig. 14-1, see also [0021]) between a source region and a drain region (see [0021]);
a dielectric layer (124, an STI region) adjacent to the subfin region (shown Fig. 14-2);
a gate structure (shown Fig. 14-3 including layers 162, 164 and 166) comprising a gate dielectric (162) and a gate layer(166), the gate layer comprising a conductive material (see [0073] describing a metal gate electrode) and extending over the semiconductor region in a second direction (y-direction, shown Fig. 14-1) different from the first direction;
spacer structures (164) on sidewalls of the gate structure (shown Fig. 14-3); and
an isolation structure (148, 150 and 174A, shown Fig. 14-2) between the spacer structures (shown Fig. 14-1) and interrupting the gate layer (shown Fig. 14-1), the isolation structure extending through at least a portion of the dielectric layer (shown Fig. 14-2), wherein the isolation structure abuts a second semiconductor region (118, shown Fig. 14-1) extending parallel to the first semiconductor region (shown Fig. 14-1) in the first direction.
Hong (US 20190348414 A1) further suggest that an isolation structure may have an elliptical shape because of the way an etching gas inflows to form a trench opening, which enables an integrated circuit wherein a distance between neighboring fins may be small while a contact area between the gate electrode and active fins is maintained such that a threshold voltage distribution does not disadvantageously increase and the isolation structure completes isolation of the gate electrode along the second direction (see also [0061], [0070] and[0099]).
However, the prior art does not teach or suggest in any combination that a portion of the gate layer being present between a sidewall of the isolation structure and one of the spacer structures along an entire length of the isolation structure along the second direction (as suggested by Fig. 9C of the instant application, thus requiring gate cut 1002 to achieve a final gate isolation).
Thus, claim 15 is deemed patentable over the prior art. Claims 16-20 are further deemed patentable as they require all limitations of claim 15.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 9 have been considered but are not persuasive. Applicant argues that Ng does not explicitly teach a gate electrode being continuous over a first fin (120) and a second fin (118). Examiner notes that the instant application shows an intermediate stage (shown Fig. 4B) wherein a gate electrode (404) is formed continuous over a first fin (204 left) and a second fin (204 right), which is similar to an intermediate structure (shown Fig. 2I-1) of Ng, wherein the continuous conductive material is interrupted by an isolation structure (as further cited in claim 1). As such, examiner respectfully disagrees that Ng fails to teach the cited features in claims 1 and 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Park (US 20160133632 A1) teaches an integrated circuit comprising a gate cut dielectric (IGR2, shown Fig. 2B) wherein the entirety of the dielectric is between gate spacers (G2B).
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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