DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s response to the Non-final Office Action dated 10/01/2025, filed with the office on 12/31/2025, has been entered and made of record.
Status of Claims
Claims 1 and 3-15 are pending. Claims 1, 9 and 10 are amended. Claim 2 is cancelled.
Response to Amendment
In light of Applicant’s amendment of claim 9, the claim objection with respect to claim 9 has been withdrawn.
In light of Applicant’s amendment of the claims, the 35 U.S.C. 112(b) rejections of record with respect to claims 3, 6 and 11 for insufficient antecedent basis have been withdrawn.
Response to Arguments
Applicant's arguments filed on December 31, 2025 with respect to rejection of claims under 35 U.S.C. 103 has been fully considered; but they are not found persuasive. Specifically, in page 9 of its reply, Applicant argues in third paragraph that Lim stipulates that the images are generated based on “symbols and shapes” therefore, the images are not based on predetermined image configuration parameters. Examiner respectfully disagrees. Lim specifically discloses generating “any definable patten that can be used to test the performance” (Lim, ¶0055). The broadest reasonable interpretation of generating a test image based on preset image configuration parameters includes generating a test image with a definable shape. Therefore, Applicant’s arguments are not found persuasive.
Applicant further argues in page 10, first paragraph that Lim does not explicitly disclose or anticipate generating the test image during a power-on reset because the claimed power-on reset occurs before any normal image is provided to the image signal processor. Examiner respectfully disagrees. Lim clearly discloses that the testing may occur either before or after the normal image is read— Lim, ¶0034: “digital test row data 102A may be generated before the image pixel data 101 is read out, or digital test row data 102B may be generated after the image pixel data 101 is read out”. Additionally, the test data (generated noise patterns) may be reset every frame to ensure a stable checksum— Lim, ¶0056: “Noise generator 425 may be reset every frame to ensure that the noise patterns it produces enable stable checksums at checksum generator”. Therefore, Lim generates a test pattern at every frame, and uses it to tests the performance of the image processing blocks before image pixel data (normal image) is read. Therefore, Applicant’s arguments are not found persuasive.
Applicant continues to argue in page 10, fourth paragraph that image generation is distinguishable from a noise pattern generation and the power-on reset is a material distinction. Examiner respectfully disagrees. As disclosed in Lim, ¶0055: “definable pattern generator 423 may generate a cartoon of a simple stop sign, a yield sign, any road sign, and generally any definable pattern that can be used to test the performance of any of the image processing blocks”, it is clearly apparent that the generation of test image is equivalent to generation of a definable patten which is used to test image processing performance. Additionally, Applicant defines the duration of power-on reset is the time before which a normal image is provided to the image signal processor and “one frame of test image can be generated after each frame of normal image and before the next frame of normal image” (Applicant’s specification, ¶0019). Lim discloses such practice of generating one testing image before/after each frame of normal image is readout— ¶0034: “digital test row data 102A may be generated before the image pixel data 101 is read out or digital test row data 102B may be generated after the image pixel data 101 is read out”. Therefore, Applicant’s arguments are not found persuasive.
Consequently, THIS ACTION IS MADE FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-6, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al. (US 2016/0295205 A1).
Regarding claim 1, Lim teaches, A method (Lim, ¶0062: “the method 500 of FIG. 5 may be used”) for detecting anomaly of image signal processor, (Lim, ¶0004: “the functionality of image processing blocks may tested or verified”) comprising: generating a test image, (Lim, ¶0038: “TPG 197 may generate test patterns”) wherein generating the test image comprises generating the test image based on predetermined image configuration parameters (Lim, ¶0055: “pattern generator 423 may generate preset patterns”) during a power-on reset of the image signal processor, (Lim, ¶0056: “Noise generator 425 may be reset every frame to ensure that the noise patterns it produces enable stable checksums”) and wherein the test image follows a predetermined image configuration rule; (Lim, ¶0055: “definable pattern generator 423 may generate preset patterns”) providing the test image to an image signal processor for anomaly detection, (Lim, ¶0035: “digital test row data may be generated for any region of the readout frame 100 to test or verify the functionality of the output processing blocks”) wherein the test image is inserted between two normal input images, (Lim, ¶0090: “Test patterns may be generated to verify the proper functioning of image processing blocks and more generally an imaging system, before, after, or before and after the imaging system captures and processes image”) wherein one frame of the test image is generated after each frame of normal image processing and before the next frame of the normal image; (Lim, ¶0090: “Test patterns may be generated… before and after the imaging system captures and processes image pixel data”) providing first image processing parameters for processing the test image to the image signal processor, (Lim, ¶0072: “Data read out from digital test rows 102A may be processed by… test blocks”; therefore, for test image data, the test blocks are provided) wherein the first image processing parameters are predetermined (Lim, ¶0051: “a known test pattern that has passed through a known subset of image processing blocks”) and stored in a corresponding register; (Lim, ¶0052: “values stored at various registers, such as those in control circuitry 17 that correspond to the settings and parameters”) and detecting processed test images to determine whether there are anomalies in the image signal processor; (Lim, ¶0089: “A first test pattern that has been processed by the first subset of image processing blocks may be used to indicate whether or not the image processing blocks in the first subset of image processing blocks is functioning properly”) wherein the processed test images are images output after the test image being processed by the image signal processor based on the first image processing parameters. (Lim, ¶0067: “The selected test or check blocks/stages and selected image processing blocks/stages through which a given test pattern has been routed may produce an output result”).
Regarding claim 3, Lim teaches, The method of claim 1, wherein the step of generating the test image comprises generating the test image based on the image configuration parameters when a first normal image has been processed by the image signal processor while a second normal image has not yet reached the image signal processor; (Lim, ¶0090: “Test patterns… before, after, or before and after the imaging system captures and processes image pixel data”) wherein the image configuration parameters are configured according to the predetermined image configuration rule and a time interval between an arrival time at which the first normal image reaches the image signal processor (Lim, ¶0024: “A frame time may be related to the operating frames per second at which an image pixel array 15 is configured to capture images”) and an expected arrival time at which the second normal image reaches the image signal processor; (Lim, ¶0024: “capture images at 30 frame per second”) and the step of providing first image processing parameter for processing the test image to the image signal processor comprises switching the image processing parameters of the image signal processor (Lim, ¶0073: “test rows 104A may be processed by a second subset”) from second image processing parameters for processing the first normal image (Lim, ¶0073: “Data read out from embedded data rows 103A may be processed by a first subset”) to the first image processing parameters. (Lim, ¶0049: “TPG 201 may be passed through any subset of the image processing blocks”).
Regarding claim 4, Lim teaches, The method of claim 2, wherein the image configuration parameters comprise a horizontal size and a vertical size of the test image, (Lim, ¶0002: “a two-dimensional array of image pixels that convert incident photons (light) into electrical signals”; ¶0064: “test pattern is generated… that is similar in content to the data that would be read out from the corresponding region of readout frame 100 in normal imaging operations”) positions of a start of frame flag and an end of frame flag of the test image, (Lim, ¶0072: “The frame time of the frame readout 600 may be defined by the time from the start of frame to the end of frame”) a horizontal blank of the processed test images, (Lim, ¶0054: “Standard pattern generator 421 may, for example, generate color bars, color gradients, black and white gradients, horizontal gradients, diagonal gradients, and generally any type of test pattern that can be used to verify or test the performance”) and an initial value associated with a data stream of the test image. (Lim, ¶0030: “CRC values for rows of digital test rows 102, embedded data rows 103, and analog test rows 104 may also be generated. Data in the rows of CRC/test columns 105 may additionally include meta-data from analog circuitry on image sensor”).
Regarding claim 5, Lim teaches, The method of claim 1, wherein the step of detecting processed test images comprises: checking whether the processed test images violate the predetermined image configuration rule, (Lim, ¶0051: “a known test pattern that has passed through a known subset of image processing blocks in the processing blocks of FIG. 3 does not match the stored checksum for the expected data”) and determining that there are anomalies in the image signal processor (Lim, ¶0051: “Checksum generator 211 may output an error flag”) in a case where the processed test images violate the predetermined image configuration rule. (Lim, ¶0051: “discrepancy between the generated checksum and the expected checksum”).
Regarding claim 6, Lim teaches, The method of claim 1, wherein the image configuration parameters comprise a horizontal size and a vertical size of the test image, (Lim, ¶0002: “a two-dimensional array of image pixels that convert incident photons (light) into electrical signals”; ¶0064: “test pattern is generated… that is similar in content to the data that would be read out from the corresponding region of readout frame 100 in normal imaging operations”) positions of a start of frame flag and an end of frame flag of the test image, (Lim, ¶0072: “from the start of frame to the end of frame”) a horizontal blank of the processed test images, (Lim, ¶0054: “Standard pattern generator 421 may, for example, generate color bars, color gradients, black and white gradients, horizontal gradients, diagonal gradients, and generally any type of test pattern that can be used to verify or test the performance) and an initial value associated with a data stream of the test image; (Lim, ¶0030: “CRC values for rows of digital test rows 102, embedded data rows 103, and analog test rows 104 may also be generated. Data in the rows of CRC/test columns 105 may additionally include meta-data from analog circuitry on image sensor”) and wherein the predetermined image configuration rule comprises: the start of frame flag of the image being set before the end of frame flag of the image, (Lim, ¶0072: “from the start of frame to the end of frame”) the horizontal size and the vertical size of the image being an integer multiple of 8 or 16, (Lim, ¶0016: “each image sensor may be a Video Graphics Array (VGA) sensor with a resolution of 480×640 image sensor pixels”) and the horizontal blank of the image remaining unchanged. (Lim, ¶0024: “image pixel array 15 is configured to capture images at 30 frame per second, the frame time for image pixel array 15 may be 1/30 second”; and ¶00therefore, since the images are captured at a constant rate, the blank/interval between image data remain constant).
Regarding claim 8, Lim teaches, The method of claim 1, wherein the step of detecting processed test images comprises: calculating a cyclic redundancy check value of the processed test images; (Lim, ¶0030: “Data in the rows of CRC/test columns 105 may correspond to invisible data, or meta-data that represents a repeatable cyclic redundancy check value”) comparing the cyclic redundancy check value with an expected cyclic redundancy check value, (Lim, ¶0069: “compare the checksum for the given test pattern output result to a checksum for an expected test pattern output”) wherein the expected cyclic redundancy check value is determined based on the test image and the first image processing parameters; (Lim, ¶0050: “checksums corresponding to expected outputs corresponding to known test patterns that have passed through a known subset of image processing blocks”) and determining there are anomalies in the image signal processor when the cyclic redundancy check value is inconsistent with the expected cyclic redundancy check value. (Lim, ¶0051: “does not match the stored checksum for the expected data corresponding to the known test pattern that has passed through the known subset of image processing blocks”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over
Lim et al. (US 2016/0295205 A1) in further view of Ruikar et al. (US 2020/0242240 A1).
Regarding claim 7, Lim teaches, The method of claim 1, wherein the image signal processor comprises (Lim, ¶0070: “If the two checksums do not match, it can indicate that one of the blocks through which the test pattern was routed is not functioning properly”). However, Lim does not explicitly teach, a plurality of parallel processing units; the step of providing the test image to an image signal processor comprises providing the test image to each parallel processing unit of the image signal processor; the processed test images comprise a plurality of processed test images obtained after being processed via each parallel processing unit.
In an analogous field of endeavor, Ruikar teaches, a plurality of parallel processing units; the step of providing the test image to an image signal processor comprises providing the test image to each parallel processing unit of the image signal processor; (Ruikar, ¶0035: “processing engines 330 simultaneously perform anomaly detection processing on up to N data streams instances in parallel”; also see fig. 3) the processed test images comprise a plurality of processed test images obtained after being processed via each parallel processing unit; (Ruikar, ¶0038: “At processing block 460, data sets are processed for anomaly detection in parallel”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lim using the teachings of Ruikar to introduce parallel processing units. A person skilled in the art would be motivated to combine the known elements as described above and achieve the predictable result of efficiently evaluating processed images to detect anomalies. Therefore, it would have been obvious to combine the analogous arts Lim and Ruikar to obtain the invention in claim 7.
Claims 9-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US 2016/0295205 A1), in view of Shimizu et al. (US 5,778,008 A) and in view of Ruikar et al. (US 2020/0242240 A1).
Regarding claim 9, Lim teaches, An anomaly detection system (Lim, ¶0001: “imaging systems with real time digital testing and verification capabilities”) for an image signal processor, (Lim, ¶0018: “processing circuitry 16 may include… digital signal processors”) comprising a test image generation circuit, (Lim, ¶0038: “TPG 197 may generate test patterns”) (Lim, ¶0047: “An enable control signal 208B may be deasserted by control circuitry 17… When enable control signal 208B is asserted, the data input to second ASIL check block 207 may be checked according to a second ASIL standard”) and an anomaly detection; (interpreted as an anomaly detection circuit) (Lim, ¶0071: “circuitry 17 may assert an error flag/signal”) wherein the test image generation circuit is configured to generate a test image, (Lim, ¶0038: “TPG 197 may generate test patterns”) and the test image follows a predetermined image configuration rule (Lim, ¶0055: “definable pattern generator 423 may generate preset patterns”) and the test image is inserted between two normal input images; (Lim, ¶0090: “Test patterns may be generated to verify the proper functioning of image processing blocks and more generally an imaging system, before, after, or before and after the imaging system captures and processes image”) wherein the test image generation circuit is configured to generate the test image based on predetermined image configuration parameters during power-on reset of the image signal processor, (Lim, ¶0056: “Noise generator 425 may be reset every frame to ensure that the noise patterns it produces enable stable checksums”) the (Lim, ¶0003: “data that is read out from a digital image sensor during normal imaging operations”) and the test image generated by the test image generation circuit, and is configured to (Lim, ¶0087: “configured to process image data and/or a digital test pattern”) select to provide the normal image or the test image to the image signal processor, (Lim, ¶0035: “digital test row data may be generated for any region of the readout frame 100 to test or verify the functionality of the output processing blocks”) wherein one frame of the test image is generated after each frame of normal image processing and before the next frame of the normal image; (Lim, ¶0090: “Test patterns may be generated… before and after the imaging system captures and processes image pixel data”) the image processing parameter selection circuit is configured to receive first image processing parameters for processing the test image (Lim, ¶0072: “Data read out from digital test rows 102A may be processed by… test blocks”) and second image processing parameters for processing the normal image, (Lim, ¶0003: “image processing blocks that are used to process data that is read out from a digital image sensor during normal imaging operations”) and is configured to select to provide the first image processing parameters (Lim, ¶0072: “Data read out from digital test rows 102A may be processed by… test blocks”; therefore, for test image data, the test blocks are provided) or the second image processing parameters to the image signal processor, (Lim, ¶0003: “image processing blocks that perform image processing operations on the data that is read out from a digital image sensor”; therefore, for the sensor image data, the processing blocks are provided) wherein the first image processing parameters are predetermined, (Lim, ¶0051: “a known test pattern that has passed through a known subset of image processing blocks”) wherein the second image processing parameters for processing the first normal image (Lim, 0003: “multiple image processing blocks that perform image processing operations on the data that is read out from a digital image sensor”) and the first image processing parameters can be stored in different registers; (Lim, ¶0052: “values stored at various registers, such as those in control circuitry 17 that correspond to the settings and parameters”) the anomaly detection circuit is configured to receive the processed test images from the image signal processor, (Lim, ¶0089: “A first test pattern that has been processed by the first subset of image processing blocks may be used to indicate whether or not the image processing blocks in the first subset of image processing blocks is functioning properly”) and is configured to detect the processed test images to determine whether any anomalies exist in the image signal processor; (Lim, ¶0089: “When the checksum of the processed test pattern does not match the predetermined checksum, an error signal may be asserted”) wherein the processed test images are images output by the image signal processor after processing the test image based on the first image processing parameters. (Lim, ¶0067: “The selected test or check blocks/stages and selected image processing blocks/stages through which a given test pattern has been routed may produce an output result”). Although Lim teaches the function of alternating image, Lim does not explicitly recite an image selection circuit.
In an analogous field of endeavor, Shimizu teaches, an image selection circuit (Shimizu, col. 1, lines 25-27: “a circuit for switching an image signal from an imaging device and the test signal”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lim using the teachings of Shimizu to introduce separate circuit for image selection. A person skilled in the art would be motivated to combine the known elements as described above and achieve the predictable result of efficiently employing a dedicated component that switches to a test image for diagnosing anomalies. Therefore, it would have been obvious to combine the analogous arts Lim and Shimizu to obtain the invention in claim 9.
Regarding claim 10, Lim in view of Shimizu teaches, The system of claim 9, wherein the image selection circuit is configured to provide the generated test image to the image signal processor (Lim, ¶0087: “produce an output data frame that includes digital test pattern data during a given frame time”) during a power-on reset of the image signal processor. (Lim, ¶0056: “Noise generator 425 may be reset every frame to ensure that the noise patterns it produces enable stable checksums”).
Regarding claim 11, Lim in view of Shimizu teaches, The system of claim 9, wherein the test image generation circuit is configured to generate the test image based on the image configuration parameters when a first normal image has been processed by the image signal processor but a second normal image has not yet reached the image signal processor, (Lim, ¶0090: “Test patterns… before, after, or before and after the imaging system captures and processes image pixel data”) wherein the image configuration parameters are configured according to the predetermined image configuration rule and a time interval between an arrival time at which the first normal image reaches the image signal processor (Lim, ¶0024: “A frame time may be related to the operating frames per second at which an image pixel array 15 is configured to capture images”) and an expected arrival time at which the second normal image reaches the image signal processor; (Lim, ¶0024: “capture images at 30 frame per second”) the image selection circuit is configured to provide the test image to the image signal processor between the first normal image and the second normal image; (Lim, ¶0090: “image processing blocks may be tested once per frame time, twice per frame time, or any number of times per frame time”) and the image processing parameter selection circuit is configured to switch the image processing parameters of the image signal processor (Lim, ¶0049: “TPG 201 may be passed through any subset of the image processing blocks”) from second image processing parameters for processing the first normal image (Lim, ¶0073: “Data read out from embedded data rows 103A may be processed by a first subset of image processing and/or test blocks”) to the first image processing parameters while the test image is provided to the image signal processor. (Lim, ¶0073: “test rows 104A may be processed by a second subset of image processing and/or test blocks”).
Regarding claim 12, Lim in view of Shimizu teaches, The system of claim 9, wherein the anomaly detection circuit comprises an image configuration rule violation detection circuit, (Lim, ¶0051: “Checksum generator 211 may output an error flag”) and the image configuration rule violation detection circuit is configured to check whether the processed test images violate the predetermined image configuration rule, (Lim, ¶0051: “a known test pattern that has passed through a known subset of image processing blocks in the processing blocks of FIG. 3 does not match the stored checksum for the expected data”) and determine that there are anomalies (Lim, ¶0051: “Checksum generator 211 may output an error flag”) in the image signal processor in a case where the processed test images violate the predetermined image configuration rule. (Lim, ¶0051: “does not match the stored checksum for the expected data corresponding to the known test pattern”).
Regarding claim 13, Lim in view of Shimizu teaches, The system of claim 9, wherein the predetermined image configuration rule comprises: a start of frame flag of the image being set before an end of frame flag of the image, (Lim, ¶0072: “The frame time of the frame readout 600 may be defined by the time from the start of frame to the end of frame”) a horizontal size and a vertical size of the image being an integer multiple of 8 or 16, (Lim, ¶0016: “each image sensor may be a Video Graphics Array (VGA) sensor with a resolution of 480×640 image sensor pixels”) and a horizontal blank of the image remaining unchanged. (Lim, ¶0024: “image pixel array 15 is configured to capture images at 30 frame per second, the frame time for image pixel array 15 may be 1/30 second”; and ¶0064: “test pattern that has data that is similar in content to the data that would be read out from the corresponding region of readout frame” therefore, the blank/interval remain constant).
Regarding claim 15, Lim in view of Shimizu teaches, The system of claim 9, wherein the anomaly detection circuit comprises a cyclic redundancy check value (Lim, ¶0030: “Data in the rows of CRC/test columns 105 may correspond to invisible data, or meta-data that represents a repeatable cyclic redundancy check value”) detection circuit, and the cyclic redundancy check value detection circuit (Lim, ¶0030: “rows of CRC/test columns 105 may additionally include meta-data from analog circuitry”) is configured to: calculate a cyclic redundancy check value of the processed test image; (Lim, ¶0030: “cyclic redundancy check value for a corresponding row of imaging pixel data 101”) compare the cyclic redundancy check value with an expected cyclic redundancy check value, (Lim, ¶0069: “compare the checksum for the given test pattern output result to a checksum for an expected test pattern output”) wherein the expected cyclic redundancy check value is determined based on the test image and the first image processing parameters; (Lim, ¶0050: “checksums corresponding to expected outputs corresponding to known test patterns that have passed through a known subset of image processing blocks”) and determine that anomalies exist (Lim, ¶0051: “output an error flag”) in the image signal processor when the cyclic redundancy check value is inconsistent with the expected cyclic redundancy check value. (Lim, ¶0051: “does not match the stored checksum for the expected data corresponding to the known test pattern that has passed through the known subset of image processing blocks”).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over
Lim et al. (US 2016/0295205 A1), in view of Shimizu et al. (US 5,778,008 A) and in further view of Ruikar et al. (US 2020/0242240 A1).
Regarding claim 14, Lim in view of Shimizu teaches, The system of claim 9, wherein the image signal processor comprises (Lim, ¶0089: “processed test pattern may be compared to a predetermined checksum”) and determine that anomalies exist in the image signal processor when the plurality of processed test images are inconsistent. (Lim, ¶0089: “When the checksum of the processed test pattern does not match the predetermined checksum, an error signal may be asserted”). However, the combination of Lim and Shimizu does not explicitly teach, a plurality of parallel processing units: the image selection circuit is configured to provide the test image to each parallel processing unit; the image processing parameter selection circuit is configured to provide the first image processing parameters to each parallel processing unit; the processed test images comprise a plurality of processed test images respectively obtained after being processed via each parallel processing unit; and the anomaly detection circuit comprises parallel detection circuit, and the parallel detection circuit are configured.
In an analogous field of endeavor, Ruikar teaches, a plurality of parallel processing units: the image selection circuit is configured to provide the test image to each parallel processing unit; the image processing parameter selection circuit is configured to provide the first image processing parameters to each parallel processing unit; (Ruikar, ¶0035: “processing engines 330 simultaneously perform anomaly detection processing on up to N data streams instances in parallel”; also see fig. 3) the processed test images comprise a plurality of processed test images respectively obtained after being processed via each parallel processing unit; and the anomaly detection circuit comprises parallel detection circuit, and the parallel detection circuit are configured. (Ruikar, ¶0038: “At processing block 460, data sets are processed for anomaly detection in parallel”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lim in view of Shimizu using the teachings of Ruikar to introduce parallel processing units. A person skilled in the art would be motivated to combine the known elements as described above and achieve the predictable result of efficiently evaluating processed images to detect anomalies. Therefore, it would have been obvious to combine the analogous arts Lim, Shimizu and Ruikar to obtain the invention in claim 14.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MEHRAZUL ISLAM/Examiner, Art Unit 2662
/AMANDEEP SAINI/Supervisory Patent Examiner, Art Unit 2662