DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is FINAL and is in response to the amendment filed February 7th, 2026. Claims 1-20 are pending, of which 1-20 are currently rejected.
Response to Arguments
The amendment filed February 7th, 2026 has been entered. Claims 1-20 remain pending in the application. Applicant’s amendments to the Claims have overcome each and every specification and claim objection as previously set forth in the Non-Final Office Action mailed November 18th, 2025.
Specification Objections
Applicant has amended the specification to address the objections as previously set forth in the Office Action mailed November 18th, 2025. Therefore, the previous objection to the Specification has been withdrawn.
Claim Objections
Applicant has amended the claims to address the objections as previously set forth in the Office Action mailed November 18th, 2025. Therefore, the previous objections to Claims 8 and 18 have been withdrawn. New claim objections of claims 4 and 14 have been made however. See Claim Objections.
Prior Art Rejections
Applicant’s arguments regarding the previously cited art have been fully considered and are not persuasive.
Applicant alleges that N. Challapalle et al. ("GaaS-X: Graph Analytics Accelerator Supporting Sparse Data Representation using Crossbar Architectures," 2020) (hereinafter "Challapalle") fails to teach the TCAM crossbar matrix storing a plurality of edges directed toward an identical vertex (Applicant Remarks Pg. 10).
Examiner respectfully disagrees. Challapalle discusses dense and sparse mapping of values to the CAMs, specifically storing and computations with respect to a single node i.e., vertex through gather operations (Challapalle: Pg. 436 Col. 1 Section D and Col. 2 Lines 1-15). More specifically Challapalle says “GaaS-X supports gather and apply operations only on a single vertex [i.e., the identical vertex] per crossbar array”. This process is also depicted in Fig. 4 on Pg. 436 where the storing of edges is done with respect to edges with destination vertex 1. Challapalle very clearly teaches how this ideal mapping is carried out in order to make calculations more efficient. Additionally, Examiner points out that in the Fig. 7 of Challapalle (Challapalle: Pg. 437) pointed out by Applicant, there are a plurality of edges being stored with the identical vertex as destination vertex. Specifically (1,2,6), (3,2,5), (4,2,8) is a plurality of edges, all of which have a destination vertex of 2 (another grouping within Fig. 7 would be (2,4,4),(3,4,2),(5,4,7) all of which are edges with identical destination vertex of 4). Although in this instance there are more edges being stored with other destination vertices, no where in the claims is it recited that the edges stored must exclusively have a single destination vertex.
Thus, Challapalle does in fact teach the limitation of storing a plurality of edges directed towards an identical vertex.
New reasons of rejection have been established as necessitated by amendments.
See Claim Rejections - 35 USC § 102 and 35 USC § 103.
Claim Objections
Claims 4 and 14 are objected to:
Claim 4 line 3 “another one vertex” should be “another identical vertex” in order to avoid confusion.
Claims 14 line 2 “another one vertex” should be “another identical vertex” in order to avoid confusion.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-15 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated N. Challapalle et al. ("GaaS-X: Graph Analytics Accelerator Supporting Sparse Data Representation using Crossbar Architectures", 2020) (hereinafter “Challapalle”).
Regarding claim 11, Challapalle teaches:
A memory device, comprising:
a controller (Challapalle: Pg. 437 Fig. 6 GaaS-X controller); and
a memory array, connected to the controller, wherein in the memory array, one Ternary Content Addressable Memory (TCAM) crossbar matrix stores a plurality of edges directed toward an identical matrix (Challapalle: Pg. 437 Fig. 6 top crossbars CAM crossbar, CAM crossbars being ternary CAMs as shown in Pg. 435 Fig. 3 TCAM cells and Pg. 438 Col. 2 Lines Section IV Lines 16-21 discusses the usage of ternary CAMs i.e., TCAMs; Pg. 437 Col. 1 Lines 10-13 parallel searches of stored edges in TCAM and generation of hit vector; Pg. 437 Fig. 6 TCAM crossbars search of TCAM cells outputting hit vectors; Challapalle Pg. 436 Col. 1 Section D and Col. 2 Lines 1-15 storing and computations with respect to a single node i.e., vertex through gather operations, more specifically Challapalle says “GaaS-X supports gather and apply operations only on a single vertex [i.e., the identical vertex] per crossbar array”; Pg. 436 Fig. 4 this process is also depicted where the storing of edges is done with respect to edges with destination vertex 1) and outputs a hit vector for selecting some of the edges (Challapalle: Pg. 437 Col. 1 Lines 10-13 parallel searches of stored edges in TCAM and generation of hit vector), and a Multiply Accumulate (MAC) crossbar matrix stores a plurality of features in the edges for performing a multiply accumulate operation according to the hit vector (Challapalle: Pg. 437 Fig. 6 bottom crossbars MAC crossbars; Pg. 437 Col. 1 Lines 25-37 storing plurality of edge features, upon which MAC operations are carried out using hit vector from TCAM crossbar).
Regarding claim 12, Challapalle teaches:
The memory device according to claim 11, wherein the TCAM crossbar matrix stores a source node and a destination node of each of the edges (Challapalle: Pg. 437 Col. 1 Lines 2-5 storing of source and destination pairs of edges i.e., source and destination nodes of graph; Pg. 435 Fig. 2 shows storage of source and destination nodes relating to each of the edges; Fig. 7 shows storage of source-destination pairs and corresponding weights into crossbars).
Regarding claim 13, Challapalle teaches:
The memory device according to claim 12, wherein the TCAM crossbar matrix further stores a layer of each of the edges (Challapalle: Pg. 440 Col. 1 Lines 25-27 during data loading phase a layer of edges are stored in the TCAM crossbars).
Regarding claim 14, Challapalle teaches:
The memory device according to claim 12, wherein the TCAM crossbar matrix further stores a plurality of edges corresponding to another one vertex (Challapalle: Pg. 439 Col. 1 Lines 3-20 computations carried out with respect to each source vertex before moving onto the computations for the next source vertex and similar process of storing current set of edges as well as computations are carried out).
Regarding claim 15, Challapalle teaches:
The memory device according to claim 11, wherein one of the features is stored in two rows of the MAC crossbar matrix (Challapalle: Pg. 437 Col. 1 Lines 27-32 in TCAM crossbar feature of vertex are stored across rows to determine the hit vector which is fed to the MAC crossbar, the MAC crossbar that stores edge weights has 2+ rows corresponding to hit vector, hence vertex feature through edge weights is stored across 2 or more rows), and the controller is configured to execute an aggregation phase and an update phase via pipeline (Challapalle: Pg. 438 Fig. 8 CAM search and MAC operation as aggregation phase and special function i.e., update phase, output of aggregation used as input of special function in order to update the edges or vertex properties; Pg. 438 Col. 1 Lines 40-47 update phase takes as input the outputs from the aggregation phase in order to further process and update values).
Regarding claim 18, Challapalle teaches:
The memory device according to claim 11, wherein the controller is configured to sample data from a dataset, and segment a graph into more than one partition (Challapalle: Pg. 435 Col. 1 Lines 2-8 partitioning of graph to prepare for random accesses i.e., sampling and subsequent processing; Pg. 437 Col. 2 Section B Lines 4-7 controller stores parameters for the graph algorithm; Pg. 438 Col. 1 Lines 6-17 controller partitions the graph for processing).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Z. Jia et al. (“Improving the Accuracy, Scalability, and Performance of Graph Neural Networks with ROC”, 2020) (hereinafter “Jia”) in view of Challapalle.
Regarding claim 1, Jia teaches graph neural network training method by sampling from a dataset, and the method having a feature extraction phase, an aggregation phase, and an update phase (Jia: Abstract; Pg. 2 Col. 1 Lines 14-30; Pg. 2 Col. 2 Lines 1-10; Pg. 3 Col. 1 Section 2.1 and Equations (1) and (2) discussing aggregate and update phase for the GNN layer, with feature extraction as taking input feature v; Pg. 3 Col. 1 Sampling in GNNs section discussing sampling of dataset for the GNN training).
Jia does not explicitly teach
wherein in the aggregation phase, one TCAM crossbar matrix stores a plurality of edges corresponding to one vertex and outputs a hit vector for selecting some of the edges, and a Multiply-Accumulate (MAC) crossbar matrix stores a plurality of features in the edges for performing a multiply accumulate operation according to the hit vector.
However, Challapalle teaches:
wherein in the aggregation phase, one TCAM crossbar matrix stores a plurality of edges directed toward an identical vertex (Challapalle: Pg. 437 Fig. 6 blue crossbars CAM crossbar, CAM crossbars being ternary CAMs as shown in Pg. 435 Fig. 3 TCAM cells and Pg. 438 Col. 2 Lines Section IV Lines 16-21; Pg. 437 Col. 1 Lines 11-14 parallel searches of stored edges in TCAM and generation of hit vector; Pg. 437 Fig. 6 TCAM crossbars search of TCAM cells outputting hit vectors; Challapalle Pg. 436 Col. 1 Section D and Col. 2 Lines 1-15 storing and computations with respect to a single node i.e., vertex through gather operations, more specifically Challapalle says “GaaS-X supports gather and apply operations only on a single vertex [i.e., the identical vertex] per crossbar array”; Pg. 436 Fig. 4 this process is also depicted where the storing of edges is done with respect to edges with destination vertex 1) and outputs a hit vector for selecting some of the edges (Challapalle: Pg. 437 Col. 1 Lines 11-14 parallel searches of stored edges in TCAM and generation of hit vector), and a Multiply-Accumulate (MAC) crossbar matrix stores a plurality of features in the edges for performing a multiply accumulate operation according to the hit vector (Challapalle: Pg. 437 Fig. 6 purple crossbars MAC crossbars; Pg. 437 Col. 1 Lines 25-37 storing plurality of edge features, upon which MAC operations are carried out using hit vector from TCAM crossbar).
It would be obvious to combine the TCAM crossbar matrix and MAC crossbar matrix and outputting of a hit vector as taught by Challapalle with the GNN training as taught by Jia as both teachings are directed towards graph-based processing. One with ordinary skill in the art would be motivated to combine the teachings as Challapalle provides the improvement of a reduction in write operations since graph processing computations occur in memory-based crossbars (Challapalle: Pg. 434 Col. 2 Lines 26-29).
Jia in view of Challapalle therefore teaches:
A Ternary Content Addressable Memory (TCAM)-based training method for Graph Neural Network, comprising:
sampling data from a dataset; and
training the Graph Neural Network according to the data from the dataset, wherein the step of training the Graph Neural Network includes:
a feature extraction phase;
an aggregation phase; and
an update phase;
wherein in the aggregation phase, one TCAM crossbar matrix stores a plurality of edges directed toward an identical vertex and outputs a hit vector for selecting some of the edges, and a Multiply Accumulate (MAC) crossbar matrix stores a plurality of features in the edges for performing a multiply accumulate operation according to the hit vector.
Regarding claim 2, Jia in view of Challapalle further teaches:
The TCAM-based training method for the Graph Neural Network according to claim 1, wherein the TCAM crossbar matrix stores a source node and a destination node of each of the edges (Challapalle: Pg. 437 Col. 1 Lines 2-5 storing of source and destination pairs of edges i.e., source and destination nodes of graph; Pg. 435 Fig. 2 shows storage of source and destination nodes relating to each of the edges; Fig. 7 shows storage of source-destination pairs and corresponding weights into crossbars).
The motivation to combine with respect to claim 1 applies equally to claim 2.
Regarding claim 3, Jia in view of Challapalle further teaches:
The TCAM-based training method for the Graph Neural Network according to claim 2, wherein the TCAM crossbar matrix further stores a layer of each of the edges (Challapalle: Pg. 440 Col. 1 Lines 24-26 during data loading phase a layer of edges are stored in the TCAM crossbars).
The motivation to combine with respect to claim 1 applies equally to claim 3.
Regarding claim 4, Jia in view of Challapalle further teaches:
The TCAM-based training method for the Graph Neural Network according to claim 2, wherein the TCAM crossbar matrix further stores a plurality of edges corresponding to another one vertex (Challapalle: Pg. 439 Col. 1 Lines 3-20 computations carried out with respect to each source vertex before moving onto the computations for the next source vertex).
The motivation to combine with respect to claim 1 applies equally to claim 4.
Regarding claim 5, Jia in view of Challapalle further teaches:
The TCAM-based training method for tl1e Graph Neural Network according to claim 1, wherein one of the features is stored in two rows of the MAC crossbar matrix (Challapalle: Pg. 437 Col. 1 Lines 27-32 in TCAM crossbar feature of vertex are stored across rows to determine the hit vector which is fed to the MAC crossbar, the MAC crossbar that stores edge weights has 2+ rows corresponding to hit vector, hence vertex feature through edge weights is stored across 2 or more rows), and the aggregation phase and the update phase are executed via pipeline (Challapalle: Pg. 438 Fig. 8 CAM search and MAC operation as aggregation phase and special function i.e., update phase, output of aggregation used as input of special function in order to update the edges or vertex properties; Pg. 438 Col. 1 Lines 40-47 update phase takes as input the outputs from the aggregation phase in order to further process and update values).
The motivation to combine with respect to claim 1 applies equally to claim 5.
Regarding claim 8, Jia in view of Challapalle further teaches:
The TCAM-based training method for the Graph Neural Network according to claim 1, wherein in the step of sampling the data from the dataset, a graph is segmented into more than one partition (Challapalle: Pg. 435 Col. 1 Lines 2-9 partitioning of graph to prepare for random accesses i.e., sampling and subsequent processing; Pg. 437 Col. 2 Section B Lines 4-7 controller stores parameters for the graph algorithm; Pg. 438 Lines 6-17 controller partitions the graph for processing).
The motivation to combine with respect to claim 1 applies equally to claim 8.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Jia in view of Challapalle, further in view of Darvish Rouhani et al. (US 2020/0193274 A1) (hereinafter “Darvish”).
While Jia in view of Challapalle teaches the TCAM-based training method for the Graph Neural Network according to claim 1, Jia in view of Challapalle does not explicitly teach each of the features having a mantissa and an exponent, the exponents being classified into groups, or the mantissas being shifted according to the exponents.
However, Darvish teaches:
wherein each of the features or each of a plurality of weightings has a mantissa and an exponent (Darvish: ¶ 0050 edge weights i.e., feature values are floating point values, floating point values having mantissa and exponent bits as further discusses in ¶ 0070), each of the exponents is classified into one of two groups, and each of the mantissas is shifted according to each of tl1e exponents (Darvish: ¶ 0073 mantissas are shifted according to the exponent; ¶ 0075 exponents are shared i.e., classified into groups the number of groups being two as discussed in ¶ 0078; Fig. 4 shows the two groups, the first group being a lighter shade and the second group being a darker shade).
It would be obvious to combine the mantissa and exponent bits of the feature values as well as exponent groupings and shifting of the mantissa according to the exponent bits as taught by Darvish with the TCAM-based training method as taught by Jia in view of Challapalle as all teachings are directed towards graph-based processing. One with ordinary skill in the art would be motivated to combine the teachings because this would lead to an increase in accuracy of computations, while also providing reduced computational complexity (Darvish: ¶ 0062).
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Jia in view of Challapalle, further in view of Shi et al. (US 2023/0049817 A1) (hereinafter “Shi”).
Regarding claim 7, while Jia in view of Challapalle teaches the TCAM-based training method for the Graph Neural Network according to claim 1 as well as a step of sampling the data (Jia: Pg. 3 Col. 1 Sampling in GNNs section discussing sampling of dataset for the GNN training), Jia in view of Challapalle does not explicitly teach sampling the data of at least one node and the data being repeated within two batches.
However, Shi teaches:
wherein the step of sampling the data from the dataset, data of at least one node is repeated within two batches (Shi: ¶ 0066 given a vertex, sampling of other vertices i.e., nodes is carried out, first sampling with respect to v3, v8 is sampled i.e., first batch and then sampling with respect to v4 is carried out and once again v8 is sampled i.e., second batch).
It would be obvious to combine the sampling of node data being repeated within two batches as taught by Shi with the TCAM-based training method for the Graph Neural Network of Jia in view of Challapalle as all teachings are directed towards graph-based processing. One with ordinary skill in the art would be motivated to combine the teachings because doing so would help with loss reduction (Shi: ¶ 0077).
Regarding claim 9, while Jia in view of Challapalle teaches the TCAM-based training method for the Graph Neural Network according to claim 1 as well as a step of sampling the data (Jia: Pg. 3 Col. 1 Sampling in GNNs section discussing sampling of dataset for the GNN training), Jia in view of Challapalle does not explicitly teach a plurality of sampling probabilities of a plurality of nodes being non-uniform.
However, Shi teaches:
wherein in the step of sampling the data from the dataset, a plurality of sampling probabilities of a plurality of nodes are non-uniform (Shi: ¶ 0077 sampling probabilities of each node are distinct, some nodes having higher sampling probabilities than others).
It would be obvious to combine the non-uniform sampling probabilities as taught by Shi with the TCAM-based training method as taught by Jia in view of Challapalle as all teachings are directed towards graph-based processing. One with ordinary skill in the art would be motivated to combine the teachings because doing so would help with loss reduction (Shi: ¶ 0077).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jia in view of Challapalle, further in view of Panigrahy et al. (US 2014/00104278 A1) (hereinafter “Panigrahy”).
While Jia in view of Challapalle teaches the TCAM-based training method for a Graph Neural Network according to claim 9 as well as a step of sampling the data (Jia: Pg. 3 Col. 1 Sampling in GNNs section discussing sampling of dataset for the GNN training), Jia in view of Challapalle does not explicitly teach reducing a sampling probability when it is out of a boundary.
However, Panigrahy teaches:
wherein in the step of sampling the data from the dataset, the sampling probability of one of the nodes whose sampling times is out of a boundary is reduced (Panigrahy: ¶ 0023 sampling probability reduced if over a sampling probability threshold i.e., boundary).
It would be obvious to combine reducing a sampling probability as taught by Panigrahy as with the TCAM-based training method as taught by Jia in view of Challapalle as all teachings are directed towards graph-based processing. One with ordinary skill in the art would be motivated to combine the teachings because this would further allow computations across all nodes i.e., vertices and edges of the graph (Panigrahy: ¶ 0018).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Challapalle, further in view of Darvish.
While Challapalle teaches the memory device according to claim 11, Challapalle does not explicitly teach each of the features having a mantissa and an exponent, the exponents being classified into groups, or the mantissas being shifted according to the exponents.
However, Darvish teaches:
wherein each of the features or each of a plurality of weightings has a mantissa and an exponent (Darvish: ¶ 0050 edge weights i.e., feature values are floating point values, floating point values having mantissa and exponent bits as further discusses in ¶ 0070), each of the exponents is classified into one of two groups, and each of the mantissas is shifted according to each of tl1e exponents (Darvish: ¶ 0073 mantissas are shifted according to the exponent; ¶ 0075 exponents are shared i.e., classified into groups the number of groups being two as discussed in ¶ 0078; Fig. 4 shows the two groups, the first group being a lighter shade and the second group being a darker shade).
It would be obvious to combine the mantissa and exponent bits of the feature values as well as exponent groupings and shifting of the mantissa according to the exponent bits as taught by Darvish with the memory device as taught by Challapalle as all teachings are directed towards graph-based processing. One with ordinary skill in the art would be motivated to combine the teachings because this would lead to an increase in accuracy of computations, while also providing reduced computational complexity (Darvish: ¶ 0062).
Claims 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Challapalle, further in view of Shi.
Regarding claim 17, while Challapalle teaches the memory device according to claim 11, as well as a step for sampling the data (Challapalle: Pg. 435 Col. 1 Section C Lines 1-9 and Col. 2 Lines 1-7 discusses sample and hold units to sample from a dataset, to then provide these values to the crossbars), Challapalle does not explicitly teach sampling the data of at least one node and the data being repeated within two batches.
However, Shi teaches:
wherein the step of sampling the data from the dataset, data of at least one node is repeated within two batches (Shi: ¶ 0066 given a vertex, sampling of other vertices i.e., nodes is carried out, first sampling with respect to v3, v8 is sampled i.e., first batch and then sampling with respect to v4 is carried out and once again v8 is sampled i.e., second batch).
It would be obvious to combine the sampling of node data being repeated within two batches as taught by Shi with the memory device of Challapalle as all teachings are directed towards graph-based processing. One with ordinary skill in the art would be motivated to combine the teachings because doing so would help with loss reduction (Shi: ¶ 0077).
Regarding claim 19, while Challapalle teaches the memory device according to claim 11 as well as a step of sampling the data (Challapalle: Pg. 435 Col. 1 Section C Lines 1-9 and Col. 2 Lines 1-7 discusses sample and hold units to sample from a dataset, to then provide these values to the crossbars), Challapalle does not explicitly teach a plurality of sampling probabilities of a plurality of nodes being non-uniform.
wherein in the step of sampling the data from the dataset, a plurality of sampling probabilities of a plurality of nodes are non-uniform (Shi: ¶ 0077 sampling probabilities of each node are distinct, some nodes having higher sampling probabilities than others).
The motivation to combine with respect to claim 17 applies equally to claim 19.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Challapalle, further in view of Panigrahy.
While Challapalle teaches the memory device according to claim 19 as well as a step of sampling the data (Challapalle: Pg. 435 Col. 1 Section C Lines 1-9 and Col. 2 Lines 1-7 discusses sample and hold units to sample from a dataset, to then provide these values to the crossbars), Challapalle does not explicitly teach reducing a sampling probability when it is out of a boundary.
However, Panigrahy teaches:
wherein in the step of sampling the data from the dataset, the sampling probability of one of the nodes whose sampling times is out of a boundary is reduced (Panigrahy: ¶ 0023 sampling probability reduced if over a sampling probability threshold i.e., boundary).
It would be obvious to combine reducing a sampling probability as taught by Panigrahy with the memory device as taught by Challapalle as all teachings are directed towards graph-based processing. One with ordinary skill in the art would be motivated to combine the teachings because this would further allow computations across all nodes i.e., vertices and edges of the graph (Panigrahy: ¶ 0018).
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Appel et al. (12572592) teaches a method for graph data analysis for evaluation and task management using a machine learning algorithm.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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