DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Specification Objections
Applicant has amended the specification at issue and the previous objections have therefore been withdrawn.
Claim Objections
Applicant has amended the claims at issue and the previous objections have therefore been withdrawn.
Claim Rejections – 35 USC 112
Applicant's arguments filed 12/2/2025 have been fully considered.
Applicant asserts “one of ordinary skill in the art would understand that data may be received in a number of different fashions by the ALU”, citing applicant paragraph 20, and thus “there is no requirement to explicitly disclose the transistor level circuitry and structure that enables the computation to be performed.” Examiner respectfully disagrees. While transistor-level circuitry may not be required for sufficient corresponding structure, “"[a] bare statement that known techniques or methods can be used does not disclose structure" in the context of a means plus function limitation”. See MPEP 2181.II.A. Furthermore, the Federal Circuit has consistently required that the structure be more than simply a general purpose computer or microprocessor. See MPEP 2181.II.B. The ALU disclosed in Applicant’s specification seems to be a general floating-point arithmetic unit ([0018]). Therefore, disclosure of corresponding structure at some level is still necessary for a means plus function limitation. Furthermore, claim 31 recites a means for receiving and a means for performing. Based on Applicant’s remarks, Examiner interprets both means to be within the ALU, however Applicant’s specification does not seem to draw clear bounds as to the portion of the ALU that performs the means for receiving and the portion of the ALU that performs the means for performing a floating point arithmetic operation.
Applicant asserts the logic engine is the sufficient corresponding structure for the means for generating of claims 32 and 33. Examiner respectfully disagrees. The corresponding structure for the means for determining in claim 31 is interpreted as the logic engine. If the logic engine were also the corresponding structure for the means for generating of claims 32 and 33, then the specification does not seem to draw clear bounds as to the portion of the logic engine that performs the means for determining and the portion of the logic engine that performs the means for generating. Furthermore, the specification states the logic engine may be implemented in software or hardware ([0018]), which furthers the lack of clarity for the boundaries of both means plus function limitations.
In regards to the rejection of indefiniteness of claim 31’s “the floating point operating unit”, Applicant has amended the claim at issue and the corresponding rejection has been withdrawn.
Double Patenting
Applicant requests the double patenting rejection is held in abeyance. The Examiner notes that “A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims, or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional.” See MPEP 804.I.B(1). Thus, a complete response to this Office Action must include either an argument explaining why the double patenting rejection is incorrect, or filing a terminal disclaimer. Failure to respond in the manner specified in the MPEP may result in Applicant’s response to be considered non-responsive. The double patenting rejection is maintained.
Prior Art Rejections
Applicant’s arguments, filed 12/2/20225, with respect to the rejection(s) of claim(s) 1, 4-5, 7-9, 12, 15-16, 20, 23-24, 26-28, and 31 under 35 USC 102 have been fully considered and are persuasive.
While the Not a Number Detection Circuit of Witek (Fig. 2 element 204) does not need the floating-point computation having been performed, the exception detection circuit as a whole obtains some exception information from the value calculation circuit (col 7 lines 36-38). However, the Examiner notes the output circuit 114 of Witek is taught to be capable of modifying a value of the arithmetic result (col 6 lines 56-60), and thus outputting a converted result.
Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view different interpretation or prior art of record.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
As to claim 31’s means for receiving, no corresponding structure is found in the disclosure.
As to claim 31’s means for performing, the examiner interprets the means plus function limitation to the corresponding structure: the floating point arithmetic unit (ALU) as disclosed in [0020] of the applicant’s specification.
As to claim 31’s means for determining, the examiner interprets the means plus function limitation to the corresponding structure: the logic engine as disclosed in [0020] of the applicant’s specification.
As to claim 31’s means for converting, the examiner interprets the means plus function limitation to the corresponding structure: the convertor engine as disclosed in [0020] of the applicant’s specification.
As to claim 32’s means for generating, no corresponding structure is found in the disclosure.
As to claim 33’s means for generating, no corresponding structure is found in the disclosure.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 31-33 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim limitation “means for receiving” of Claim 31 invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The claim recites “means for receiving at a floating point arithmetic operating unit”, the word “at” is interpreted to show an exact position or a particular place, as per the Cambridge dictionary, and thus the “means for receiving” is interpreted to be within the floating point arithmetic unit. The specification fails to disclose clear bounds of such a structure within the floating point ALU. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Claim limitation “means for generating” of Claim 32 invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification fails to disclose a structure for generating an out-of-bound flag such that one of ordinary skill in the art would understand how the means for generating an out-of-bounds flag would be carried out. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Claim limitation “means for generating” of Claim 33 invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification fails to disclose a structure for generating a divide-by-zero flag such that one of ordinary skill in the art would understand how the means for generating a divide-by-zero flag would be carried out. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 31-33 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As described above, the disclosure does not provide adequate structure to perform the claimed function of receiving inputs, generating an out-of-bounds flag, and generating a divide-by-zero flag. The specification does not demonstrate the applicant has made an invention that achieves the claimed functions because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor has possession of the claimed invention
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Double Patenting Rejection #1
Claims 1, 7-9, 12, 20, 26-28 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 5-6, 20-21, 30-31 of U.S. Patent No. 11301247, hereinafter “the ‘247 patent”. Although the claims at issue are not identical, they are not patentably distinct from each other because application claims 1, 7-9, 12, 20, 26-28 are anticipated by patent claims 5-6, 20-21, 30-31. Claim 1 in the instant application recite merely generic converting the output result to a modified value that eliminates the floating point exception, while claims 5-6 of the ‘247 patent recite in essence a “species” of the generic output modification to eliminate a floating point exception. Furthermore, Claim 1 in the instant application recite merely performing a floating point operation on input data to generate an output result, while claims 5-6 of the ‘247 patent recite modifying the input data before performing the floating point operation, which is in essence a “species” of input data for floating point operation. The same analysis applies for Claim 12 in the instant application with claims 20-21 in the ‘247 patent. The same analysis applies for Claim 20 in the instant application with claims 30-31 in the ‘247 patent.
Current Application: 17/686676
U.S. Patent No. 11,307,247
Claim 1
Claim 5
A computer-implemented method comprising: receiving an input data at a floating point arithmetic operating unit, wherein the floating point arithmetic operating unit is configured to perform a floating point arithmetic operation on the input data to generate an output result;
Claim 1: A computer-implemented method comprising: receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data;
determining whether the received input data generates a floating point hardware exception responsive to the floating point arithmetic operation on the input data, wherein the determining occurs prior to performing the FP arithmetic operation; and converting a value of the received input data to a modified value responsive to the determining that the received input data generates the floating point hardware exception, wherein the converting eliminates generation of the floating point hardware exception responsive to the floating point arithmetic operation on the input data, wherein the modified value for the input data is a maximum supported value if the input data is positive infinity and wherein the modified value for the input data is a minimum supported value if the input data is negative infinity.
Claim 2: The method of Claim 1 further comprising performing the floating point arithmetic operation on the input data with modified value to generate an output result.
determining whether the output result is going to cause a floating point hardware exception responsive to the floating point arithmetic operation on the input data;
Claim 4: The method of Claim 2 further comprising determining whether the output result of the FP arithmetic operation generates a floating point hardware exception.
and converting a value of the output result to a modified value responsive to the determining that the output result is going to cause the floating point hardware exception, wherein the modified value eliminates the floating point hardware exception responsive to the floating point arithmetic operation on the input data.
Claim 5: The method of Claim 4 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 7
Claim 5
The method of Claim 1, wherein the converting comprises setting a value of the output result to zero if a value of the output result is a denormal number.
The method of Claim 4 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 8
Claim 6
The method of Claim 1, wherein the converting comprises setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity.
The method of Claim 4 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim 9
Claim 6
The method of Claim 1, wherein the converting comprises setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
The method of Claim 4 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Double Patenting Rejection #2
Claims 1, 7-9, 12, 20, 26-28 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 5-6, 15-16, 31-32 of co-pending U.S. Patent Application No. 17/686682, hereinafter “the ‘682 application”. Although the claims at issue are not identical, they are not patentably distinct from each other because application claims 1, 7-9, 12, 20, 26-28 of the instant application are anticipated by claims 5-6, 15-16, 31-32 of the co-pending ‘682 application. Claim 1 in the instant application recite merely generic converting the output result to a modified value that eliminates the floating point exception, while claims 5-6 of the ‘682 co-pending application recite in essence a “species” of the generic output modification to eliminate a floating point exception. Furthermore, Claim 1 in the instant application recite merely performing a floating point operation on input data to generate an output result, while claims 5-6 of the co-pending ‘682 application recite modifying the input data before performing the floating point operation, which is in essence a “species” of input data for floating point operation. The same analysis applies for Claim 12 in the instant application with claims 15-16 in the ‘682 co-pending application. The same analysis applies for Claim 20 in the instant application with claims 31-32 in the ‘682 co-pending application.
This is a provisional non-statutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Current Application: 17/686676
U.S. Patent Application No. 17/686682
Claim 1
Claim 5
A computer-implemented method comprising: receiving an input data at a floating point arithmetic operating unit, wherein the floating point arithmetic operating unit is configured to perform a floating point arithmetic operation on the input data to generate an output result;
Claim 1: A computer-implemented method comprising: receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data;
determining whether the received input data is a quiet not-a-number (qnan) or whether the received input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; and converting a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is either the qnan or the snan, wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the input data is either the qnan or the snan.
Claim 2: The method of Claim 1 further comprising performing the floating point arithmetic operation on the input data with modified value to generate an output result.
determining whether the output result is going to cause a floating point hardware exception responsive to the floating point arithmetic operation on the input data;
Claim 4: The method of Claim 2 further comprising determining whether the output result of the FP arithmetic operation generates a floating point hardware exception.
and converting a value of the output result to a modified value responsive to the determining that the output result is going to cause the floating point hardware exception, wherein the modified value eliminates the floating point hardware exception responsive to the floating point arithmetic operation on the input data.
Claim 5: The method of Claim 4 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 7
Claim 5
The method of Claim 1, wherein the converting comprises setting a value of the output result to zero if a value of the output result is a denormal number.
The method of Claim 4 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 8
Claim 6
The method of Claim 1, wherein the converting comprises setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity.
The method of Claim 4 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim 9
Claim 6
The method of Claim 1, wherein the converting comprises setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
The method of Claim 4 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 7-9, 12-13, 15-16, 20-21, 23-24, 26-28, 31 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard et al (US 5748516 A, hereinafter “Goddard” from IDS filed 07/14/2025) in view of Witek et al. (US 10564931 B1).
As per claim 1, Goddard teaches A computer-implemented method comprising: receiving an input data at a floating point arithmetic operating unit, wherein the floating point arithmetic operating unit is configured to perform a floating point arithmetic operation on the input data to generate an output result (Goddard: Fig. 2; col 5 lines 50-57);
determining whether the output result is going to cause a floating point hardware exception responsive to the floating point arithmetic operation on the input data (Goddard: Fig. 2 element 220; col 8 lines 18-26; col 8 lines 52-61; in particular, the predetect unit characterizes the operands to determine whether the arithmetic result will cause an exception and force the FPU output to a different value based on the exception);
However, while Goddard teaches selecting the final floating-point result if an exception should occur (Fig. 5 element 556; col 15 lines 15-26), Goddard does not teach conversion that is modifying the arithmetic output result. Thus, Goddard does not teach and converting a value of the output result to a modified value responsive to the determining that the output result is going to cause the floating point hardware exception, wherein the modified value eliminates the floating point hardware exception responsive to the floating point arithmetic operation on the input data.
Witek teaches and converting a value of the output result to a modified value responsive to the determining that the output result is going to cause the floating point hardware exception, wherein the modified value eliminates the floating point hardware exception responsive to the floating point arithmetic operation on the input data (Witek: Fig. 1 element 114; col 6 lines 43-48; col 6 lines 55-60, wherein the output circuit of Witek may modify the arithmetic result with the selection signals).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the output multiplexer of Goddard with the output circuitry of Witek. One would have been motivated to combine these references because both references disclose exception handling for floating-point arithmetic units, and combining prior art elements according to known methods to yield predictable results (modifying the result to prevent outputting an exception).
As per claim 2, Goddard/Witek further teaches The method of Claim 1, wherein the floating point arithmetic operation is selected from one of an addition operation, or a subtraction operation, (Goddard: Fig. 2 elements 230; Table 1 showing operations).
As per claim 4, Goddard/Witek further teaches The method of Claim 1, wherein the floating point arithmetic operation is selected from one of multiplication or divisional operation (Goddard: Fig. 2 element 241; Table 1 showing operations).
As per claim 5, Goddard/Witek further teach The method of Claim 1, wherein the floating point arithmetic operation is converting from a first floating point to a second floating point if the input data is less than a threshold and from a third floating point to a fourth floating point if the input is greater than the threshold (Goddard: col 18 lines 50-60).
As per claim 7, while Goddard teaches detecting denormal numbers (col 15 lines 15-26) and changing the final result to 0 when conditions are met (Table 1), Goddard does not explicitly teach how denormal numbers are handled. Thus, Goddard does not teach wherein the converting comprises setting a value of the output result to zero if a value of the output result is a denormal number.
Witek teaches wherein the converting comprises setting a value of the output result to zero if a value of the output result is a denormal number (Witek: Fig. 3; col 9 lines 22-26).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the predetect and output circuitry of Goddard with the threshold processing of the detection circuit and output circuit of Witek. One would have been motivated to combine these references because both references disclose exception handling for arithmetic units performing floating-point operations, and combining prior art elements according to known methods to yield predictable results (handling denormal results).
As per claim 8, While Goddard teaches handling overflow and underflow, Goddard does not explicitly teach the handling sets the result to a maximum value. Thus, Goddard does not teach wherein the converting comprises setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity.
Witek teaches wherein the converting comprises setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity (Witek: Fig. 3; col 9 lines 11-17; The Examiner interprets “largest value in the specified range… may correspond to the sign” to mean a most positive value in the range corresponding to a positive sign, and a most negative value in the range corresponding to a negative sign.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the the predetect and output circuitry of Goddard with the threshold processing of the detection circuit and output circuit of Witek. . One would have been motivated to combine these references because both references disclose exception handling for arithmetic units performing floating-point operations, and combining prior art elements according to known methods to yield predictable results (handling overflow results).
As per claim 9, While Goddard teaches handling overflow and underflow, Goddard does not explicitly teach the handling sets the result to a minimum value. Thus, Goddard does not teach wherein the converting comprises setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Witek teaches wherein the converting comprises setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity (Witek: Fig. 3; col 9 lines 11-17; The Examiner interprets “largest value in the specified range… may correspond to the sign” to mean a most positive value in the range corresponding to a positive sign, and a most negative value in the range corresponding to a negative sign.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the the predetect and output circuitry of Goddard with the threshold processing of the detection circuit and output circuit of Witek. One would have been motivated to combine these references because both references disclose exception handling for arithmetic units performing floating-point operations, and combining prior art elements according to known methods to yield predictable results (handling underflow results).
As per claim 12, it is directed to a system that implements the same features as the method of claim 1, and is therefore rejected for at least the same reasons therein. Furthermore, Goddard/Witek teaches setting a value of the output result to zero if a value of the output result is a denormal number (Witek: Fig. 3; col 9 lines 22-26);
setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity (Witek: Fig. 3; col 9 lines 11-17; The Examiner interprets “largest value in the specified range… may correspond to the sign” to mean a most positive value in the range corresponding to a positive sign.);
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity (Witek: Fig. 3; col 9 lines 11-17; The Examiner interprets “largest value in the specified range… may correspond to the sign” to mean a most negative value in the range corresponding to a negative sign.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the the predetect and output circuitry of Goddard with the threshold processing of the detection circuit and output circuit of Witek for at least the same reasons as claims 7-8.
As per claims 13, 15-16, the claims are directed to a method that implements the same features as the method of claims 2, 4-5, respectively, and is therefore rejected for at least the same reasons therein.
As per claim 20, it is directed to a system that implements the same features as the method of claim 1, and is therefore rejected for at least the same reasons therein. Furthermore, Goddard/Witek teaches a logic engine (Goddard: Fig. 2 element 220; col 8 lines 18-26); and a convertor engine (Witek: Fig. 1 element 114; col 6 lines 43-60).
As per claim 21, 23-24, the claims are directed to a system that implements the same features as the method of claims 2, 4-5, respectively, and is therefore rejected for at least the same reasons therein.
As per claim 26-28, the claims are directed to a system that implements the same features as the method of claims 7-9, respectively, and is therefore rejected for at least the same reasons therein.
As per claim 31, it is directed to a system that implements the same features as the method of claim 1, and is therefore rejected for at least the same reasons therein.
Claims 3, 10, 14, 18, 22, 29, 32 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard/Witek in further view of Siu et al. (US 20060101244 A1, hereinafter “Siu”).
As per claim 3, while Goddard teaches the FPU may comprise multiple arithmetic units (col 6 line 65- col 7 line 7), Goddard does not explicitly teach arithmetic units for floating-point maximum or minimum. Thus, Goddard does not teach wherein the floating point arithmetic operation is selected from one of maximum, minimum, max-reduce, or min-reduce.
Siu teaches wherein the floating point arithmetic operation is selected from one of maximum, minimum, max-reduce, or min-reduce (Siu: Fig. 3; [0053] of note FMAX and FMIN operations).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the FPU of Goddard with the floating-point unit of Siu. One would have been motivated to combine these references because both references disclose arithmetic units performing floating-point operations, and the combination renders an improved method that allows for a more robust processing technique that allows for more useful applications within the field (being capable of performing more floating-point operations).
As per claim 10, while Goddard teaches exception control may be operated by flags (Goddard: col 13 lines 9-16), Goddard does not explicitly disclose generating the flag. Thus, Goddard/Witek does not teach raising an out-of-bound flag if the output result is a positive infinity, a negative infinity, or a denormal number.
Siu teaches further comprising raising an out-of-bound flag if the output result is a positive infinity, a negative infinity, or a denormal number (Siu: [0300]; [0050], wherein special numbers include denormal and infinity).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the FPU of Goddard with the special flag number generation of Siu. One would have been motivated to combine these references because both references disclose arithmetic units performing floating-point operations, and combining prior art elements according to known methods to yield predictable results (generating the overflow flag).
As per claims 14 and 18, the claims are directed to a method that implements the same features as the method of claims 3 and 10, respectively, and is therefore rejected for at least the same reasons therein.
As per claims 22 and 29, the claims are directed to a system that implements the same features as the method of claims 3 and 10, respectively, and is therefore rejected for at least the same reasons therein.
As per claim 32, it is directed to a system that implements the same features as the method of claim 10 and is therefore rejected for at least the same reasons therein.
Claims 6, 17, 25 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard/in further view of Hinds et al. (US 5339266 A, hereinafter “Hinds”).
As per claim 6, while Goddard teaches the FPU may comprise multiple arithmetic units (col 6 line 65- col 7 line 7), Goddard does not explicitly teach arithmetic units for floating-point to integer conversion. Thus, Goddard does not teach wherein the floating arithmetic operation is converting the input data from a floating point to an integer value.
Hinds teaches wherein the floating arithmetic operation is converting the input data from a floating point to an integer value (Hinds: Fig. 1 element 18; col 3 lines 51-53).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the FADD of Goddard with the floating-point adder of Hinds. One would have been motivated to combine these references because both references disclose arithmetic units performing floating-point operations, and the combination renders an improved method that allows for a more robust processing technique that allows for more useful applications within the field (being capable of performing more floating-point operations).
As per claim 17, the claim is directed to a method that implements the same features as the method of claim 6, and is therefore rejected for at least the same reasons therein.
As per claim 25, the claim is directed to a system that implements the same features as the method of claim 6, and is therefore rejected for at least the same reasons therein.
Claims 11, 19, 30, 33 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard/in further view of Wilkins (US 20140195581 A1, hereinafter “Wilkins”).
As per claim 11, while Goddard teaches division-by-zero handling (Goddard: Table 1) and exception control may be operated by flags (Goddard: col 13 lines 9-16), Goddard does not explicitly disclose generating a divide-by-zero flag. Thus, Goddard does not teach raising a divide-by-zero flag when the floating point arithmetic operation is a division and wherein a dividend is a nonzero number and divisor is a zero number.
Wilkins teaches further comprising raising a divide-by-zero flag when the floating point arithmetic operation is a division and wherein a dividend is a nonzero number and divisor is a zero number (Wilkins: [0027]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the FPU of Goddard with the floating-point architecture of Wilkins. One would have been motivated to combine these references because both references disclose circuits capable of performing floating-point operations, and the combination renders an improved method that allows for a more robust processing technique that allows for more useful applications within the field (being capable of performing floating-point division operations).
As per claim 19, it is directed to a method that implements the same features as the method of claim 11 and is therefore rejected for at least the same reasons therein.
As per claim 30, it is directed to a system that implements the same features as the method of claim 11 and is therefore rejected for at least the same reasons therein.
As per claim 33, it is directed to a system that implements the same features as the method of claim 11 and is therefore rejected for at least the same reasons therein.
Conclusion
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182