DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claim Rejections – 35 USC 112
Applicant’s arguments, filed 5/22/2026, with respect to 112(a) and 112(b) have been fully considered and are persuasive. The 112(a) and 112(b) rejections of claims 31-33 have been withdrawn.
However, the Examiner notes new 112(b) rejections are made in view of the amendments.
Double Patenting Rejections
Applicant's arguments filed 5/22/2026 have been fully considered but they are not persuasive.
Applicant asserts “claims 5-6, 20-21, and 30-31 of the ‘247 patent and claims 5-6, 15-16, 31-32 of the ‘682 application do not expressly recite these features” on pg. 11 of remarks. However, whether a claim “expressly recites” features is not the correct standard of analysis for nonstatutory double patenting, which is instead determining whether the claim is patentably distinct. See MPEP 804(II)(B).
Prior Art Rejections
Applicant's arguments filed 5/22/2026 have been fully considered.
Applicant asserts Goddard teaches an input side detection block used together with the mathematical operation and thus, Goddard does not teach whether output data is going to cause a floating point hardware exception. Examiner agrees. Goddard does not teach a single unit that determines whether input data would cause a floating point hardware exception and uses output data to determine whether the output data is going to cause a floating point hardware exception.
Applicant asserts Witek does not remedy the deficiencies of Goddard because Witek merely discloses an output side detection block. Examiner respectfully disagrees. The FPDET unit of Goddard may be modified with the teachings of the Range Exception Detection Circuit of Witek such that the circuits of MRANGEDET (element 553) and EXRANGDET (element 552) of Goddard may be combined with the FPDET of Goddard to correspond to the claimed logic engine. Thus, the combination allows the FPDET unit of Goddard to be used for both the input side determination and the output side determination. Therefore, the prior art rejections of the claims are maintained.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
As to claim 31’s means for performing, the examiner interprets the means plus function limitation to the corresponding structure: the floating point arithmetic unit (ALU) as disclosed in [0020] of the applicant’s specification.
As to claim 31’s means for determining, the examiner interprets the means plus function limitation to the corresponding structure: the logic engine as disclosed in [0020] of the applicant’s specification.
As to claim 31’s means for converting, the examiner interprets the means plus function limitation to the corresponding structure: the convertor engine as disclosed in [0020] of the applicant’s specification.
As to claim 32’s means for generating, the examiner interprets the means plus function limitation to the corresponding structure: the logic engine as disclosed in [0038], [0040], [0042] of the applicant’s specification.
As to claim 33’s means for generating, the examiner interprets the means plus function limitation to the corresponding structure: the logic engine as disclosed in [0038], [0040], [0042] of the applicant’s specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 20-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites the limitation “arithmetic logic unit” It is unclear whether the “arithmetic logic unit” is a component within the claimed system, or is external to the system and merely acted upon. That is, it is not clear whether the “arithmetic logic unit” is inferentially citing a structural element of the claim, as the element has not been positively recited within a claimed structure.
Claims 21-30 are rejected based on inheriting the deficiencies of claim 20 without correcting the issue.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Double Patenting Rejection #1
Claims 1, 7-9, 12, 20, 26-28 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 5-6, 20-21, 30-31 of U.S. Patent No. 11301247, hereinafter “the ‘247 patent”. Although the claims at issue are not identical, they are not patentably distinct from each other because application claims 1, 7-9, 12, 20, 26-28 would have been obvious over patent claims 5-6, 20-21, 30-31 in view of Witek et al. (US 10564931 B1, hereinafter “Witek”).
Claim 1 in the instant application merely recites generic converting of the output data to a modified value that eliminates the floating point exception, while claims 5-6 of the ‘247 patent recite in essence a “species” of the generic output modification to eliminate a floating point exception. The same analysis applies for Claim 12 in the instant application with claims 20-21 in the ‘247 patent. The same analysis applies for Claim 20 in the instant application with claims 30-31 in the ‘247 patent.
As to Claim 1, claim 5 of the ‘247 patent does not explicitly recite a logic engine, arithmetic logic unit, and converter engine.
However, in the same field of endeavor, Witek discloses a logic engine, arithmetic logic unit, and converter engine (Witek: Fig. 1 elements 112, 102, 114).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify Claim 5 of the ‘247 patent using Witek and configure the floating point operating unit to comprise a logic engine, arithmetic logic unit, and converter engine to yield predictable results of defining sections of the floating point operating unit.
Therefore, the combination of the ‘247 patent in view of Witek teaches a method that receives and determines by a logic engine, perform floating point arithmetic by an arithmetic logic unit, and convert by a converter engine. Similar analysis applies for Claim 12 in the instant application with claims 20-21 in the ‘247 patent. Similar analysis applies for Claim 20 in the instant application with claims 30-31 in the ‘247 patent.
Current Application: 17/686676
U.S. Patent No. 11,307,247
Claim 1
Claim 5
A computer-implemented method comprising: receiving,
Claim 1: A computer-implemented method comprising: receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data;
determining whether the received input data generates a floating point hardware exception responsive to the floating point arithmetic operation on the input data, wherein the determining occurs prior to performing the FP arithmetic operation; and converting a value of the received input data to a modified value responsive to the determining that the received input data generates the floating point hardware exception, wherein the converting eliminates generation of the floating point hardware exception responsive to the floating point arithmetic operation on the input data, wherein the modified value for the input data is a maximum supported value if the input data is positive infinity and wherein the modified value for the input data is a minimum supported value if the input data is negative infinity.
Claim 2: The method of Claim 1 further comprising performing the floating point arithmetic operation on the input data with modified value to generate an output result.
determining,
Claim 1: determining whether the received input data generates a floating point hardware exception responsive to the floating point arithmetic operation on the input data,
Claim 4: The method of Claim 2 further comprising determining whether the output result of the FP arithmetic operation generates a floating point hardware exception.
and converting, a value of the output data to a modified value responsive to the determining that the output data is going to cause the floating point hardware exception, wherein the modified value eliminates the floating point hardware exception responsive to the floating point arithmetic operation on the input data.
Claim 5: The method of Claim 4 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 7
Claim 5
The method of Claim 1, wherein the converting comprises setting a value of the output data to zero if a value of the output data is a denormal number.
The method of Claim 4 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 8
Claim 6
The method of Claim 1, wherein the converting comprises setting a value of the output data to a maximum supported number if a value of the output data is a positive infinity.
The method of Claim 4 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim 9
Claim 6
The method of Claim 1, wherein the converting comprises setting a value of the output data to a minimum supported number if a value of the output data is a negative infinity.
The method of Claim 4 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Double Patenting Rejection #2
Claims 1, 7-9, 12, 20, 26-28 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 5-6, 15-16, 31-32 of co-pending U.S. Patent Application No. 17/686682, hereinafter “the ‘682 application”. Although the claims at issue are not identical, they are not patentably distinct from each other because application claims 1, 7-9, 12, 20, 26-28 of the instant application would have been obvious over claims 5-6, 15-16, 31-32 of the co-pending ‘682 application 31 in view of Witek et al. (US 10564931 B1, hereinafter “Witek”).
Claim 1 in the instant application merely recites generic converting the output data to a modified value that eliminates the floating point exception, while claims 5-6 of the ‘682 co-pending application recite in essence a “species” of the generic output modification to eliminate a floating point exception. The same analysis applies for Claim 12 in the instant application with claims 15-16 in the ‘682 co-pending application. The same analysis applies for Claim 20 in the instant application with claims 31-32 in the ‘682 co-pending application.
As to Claim 1, claim 5 of the ‘682 co-pending application does not explicitly recite a logic engine, arithmetic logic unit, and converter engine.
However, in the same field of endeavor, Witek discloses a logic engine, arithmetic logic unit, and converter engine (Witek: Fig. 1 elements 112, 102, 114).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify Claim 5 of the ‘682 co-pending application using Witek and configure the floating point operating unit to comprise a logic engine, arithmetic logic unit, and converter engine to yield predictable results of defining sections of the floating point operating unit.
Therefore, the combination of the ‘682 co-pending application in view of Witek teaches a method that receives and determines by a logic engine, perform floating point arithmetic by an arithmetic logic unit, and convert by a converter engine. Similar analysis applies for Claim 12 in the instant application with claims 20-21 in the ‘682 co-pending application. Similar analysis applies for Claim 20 in the instant application with claims 30-31 in the ‘682 co-pending application.
This is a provisional non-statutory double patenting rejection because the patentably indistinct claims have not in fact been published as a patent as of 8/11/2026.
Current Application: 17/686676
U.S. Patent Application No. 17/686682
Claim 1
Claim 5
A computer-implemented method comprising: receiving,
Claim 1: A computer-implemented method comprising: receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data;
determining whether the received input data is a quiet not-a-number (qnan) or whether the received input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; and converting a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is either the qnan or the snan, wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the input data is either the qnan or the snan.
Claim 2: The method of Claim 1 further comprising performing the floating point arithmetic operation on the input data with modified value to generate an output result.
determining,
Claim 1: determining whether the received input data is a quiet not-a-number (qnan) or whether the received input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
Claim 4: The method of Claim 2 further comprising determining whether the output result of the FP arithmetic operation generates a floating point hardware exception.
and converting, a value of the output data to a modified value responsive to the determining that the output data is going to cause the floating point hardware exception, wherein the modified value eliminates the floating point hardware exception responsive to the floating point arithmetic operation on the input data.
Claim 5: The method of Claim 4 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 7
Claim 5
The method of Claim 1, wherein the converting comprises setting a value of the output data to zero if a value of the output data is a denormal number.
The method of Claim 4 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 8
Claim 6
The method of Claim 1, wherein the converting comprises setting a value of the output data to a maximum supported number if a value of the output data is a positive infinity.
The method of Claim 4 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim 9
Claim 6
The method of Claim 1, wherein the converting comprises setting a value of the output data to a minimum supported number if a value of the output data is a negative infinity.
The method of Claim 4 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 7-9, 12-13, 15-16, 20-21, 23-24, 26-28, 31 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard et al (US 5748516 A, hereinafter “Goddard” from IDS filed 07/14/2025) in view of Witek et al. (US 10564931 B1, hereinafter “Witek”).
As per claim 1, Goddard teaches A computer-implemented method comprising: receiving, by a logic engine (Goddard: Fig. 2 element 220), an input data for a floating point arithmetic operation to be performed by an arithmetic logic unit to generate an output data (Goddard: Fig. 2; col 5 lines 50-57);
Determining, by the logic engine, whether the input data would cause a floating point hardware exception once operated on by the arithmetic logic unit (Goddard: Fig. 2 element 220; col 8 lines 18-26; col 8 lines 52-61; in particular, the predetect unit characterizes the operands to determine whether the arithmetic result will cause an exception and force the FPU output to a different value based on the exception);
However, while Goddard teaches selecting the final floating-point result if an exception should occur (Fig. 5 element 556; col 15 lines 15-26) and detecting whether the resulting exponent and mantissas are out of range (Fig. 5 elements 552, 553; col 17 lines 34-37, 52-55), Goddard does not teach conversion that is modifying the arithmetic output result nor the range detecting as part of the FPDET unit. Thus, Goddard does not teach and whether the output data generated by the arithmetic logic unit is going to cause a floating point hardware exception responsive to the floating point arithmetic operation on the input data; and converting a value of the output result to a modified value responsive to the determining that the output result is going to cause the floating point hardware exception, wherein the modified value eliminates the floating point hardware exception responsive to the floating point arithmetic operation on the input data.
Witek teaches and whether the output data generated by the arithmetic logic unit is going to cause a floating point hardware exception responsive to the floating point arithmetic operation on the input data (Witek: Fig. 2);
and converting a value of the output result to a modified value responsive to the determining that the output result is going to cause the floating point hardware exception, wherein the modified value eliminates the floating point hardware exception responsive to the floating point arithmetic operation on the input data (Witek: Fig. 1 element 114; col 6 lines 43-48; col 6 lines 55-60, wherein the output circuit of Witek may modify the arithmetic result with the selection signals).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the output multiplexer of Goddard with the output circuitry of Witek; and modify the FPDET, EXRANGEDET, and MRANGEDET of Goddard with the Range Exception Detection Circuit of Witek. One would have been motivated to combine these references because both references disclose exception handling for floating-point arithmetic units, and combining prior art elements according to known methods to yield predictable results (modifying the result to prevent outputting an exception, and show an arrangement of the floating-point exception detection circuits).
As per claim 2, Goddard/Witek further teaches The method of Claim 1, wherein the floating point arithmetic operation is selected from one of an addition operation, or a subtraction operation, (Goddard: Fig. 2 elements 230; Table 1 showing operations).
As per claim 4, Goddard/Witek further teaches The method of Claim 1, wherein the floating point arithmetic operation is selected from one of multiplication or divisional operation (Goddard: Fig. 2 element 241; Table 1 showing operations).
As per claim 5, Goddard/Witek further teach The method of Claim 1, wherein the floating point arithmetic operation is converting from a first floating point to a second floating point if the input data is less than a threshold and from a third floating point to a fourth floating point if the input data is greater than the threshold (Goddard: col 18 lines 50-60).
As per claim 7, while Goddard teaches detecting denormal numbers (col 15 lines 15-26) and changing the final result to 0 when conditions are met (Table 1), Goddard does not explicitly teach how denormal numbers are handled. Thus, Goddard does not teach wherein the converting comprises setting a value of the output data to zero if a value of the output data is a denormal number.
Witek teaches wherein the converting comprises setting a value of the output data to zero if a value of the output data is a denormal number (Witek: Fig. 3; col 9 lines 22-26).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the predetect and output circuitry of Goddard with the threshold processing of the detection circuit and output circuit of Witek. One would have been motivated to combine these references because both references disclose exception handling for arithmetic units performing floating-point operations, and combining prior art elements according to known methods to yield predictable results (handling denormal results).
As per claim 8, While Goddard teaches handling overflow and underflow, Goddard does not explicitly teach the handling sets the result to a maximum value. Thus, Goddard does not teach wherein the converting comprises setting a value of the output data to a maximum supported number if a value of the output data is a positive infinity.
Witek teaches wherein the converting comprises setting a value of the output data to a maximum supported number if a value of the output data is a positive infinity (Witek: Fig. 3; col 9 lines 11-17; The Examiner interprets “largest value in the specified range… may correspond to the sign” to mean a most positive value in the range corresponding to a positive sign, and a most negative value in the range corresponding to a negative sign.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the the predetect and output circuitry of Goddard with the threshold processing of the detection circuit and output circuit of Witek. One would have been motivated to combine these references because both references disclose exception handling for arithmetic units performing floating-point operations, and combining prior art elements according to known methods to yield predictable results (handling overflow results).
As per claim 9, While Goddard teaches handling overflow and underflow, Goddard does not explicitly teach the handling sets the result to a minimum value. Thus, Goddard does not teach wherein the converting comprises setting a value of the output data to a minimum supported number if a value of the output data is a negative infinity.
Witek teaches wherein the converting comprises setting a value of the output data to a minimum supported number if a value of the output data is a negative infinity (Witek: Fig. 3; col 9 lines 11-17; The Examiner interprets “largest value in the specified range… may correspond to the sign” to mean a most positive value in the range corresponding to a positive sign, and a most negative value in the range corresponding to a negative sign.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the the predetect and output circuitry of Goddard with the threshold processing of the detection circuit and output circuit of Witek. One would have been motivated to combine these references because both references disclose exception handling for arithmetic units performing floating-point operations, and combining prior art elements according to known methods to yield predictable results (handling underflow results).
As per claim 12, it is directed to a system that implements the same features as the method of claim 1, and is therefore rejected for at least the same reasons therein. Furthermore, Goddard/Witek teaches setting a value of the output data to zero if a value of the output data is a denormal number (Witek: Fig. 3; col 9 lines 22-26);
setting a value of the output data to a maximum supported number if a value of the output data is a positive infinity (Witek: Fig. 3; col 9 lines 11-17; The Examiner interprets “largest value in the specified range… may correspond to the sign” to mean a most positive value in the range corresponding to a positive sign.);
and setting a value of the output data to a minimum supported number if a value of the output data is a negative infinity (Witek: Fig. 3; col 9 lines 11-17; The Examiner interprets “largest value in the specified range… may correspond to the sign” to mean a most negative value in the range corresponding to a negative sign.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the the predetect and output circuitry of Goddard with the threshold processing of the detection circuit and output circuit of Witek for at least the same reasons as claims 7-8.
As per claims 13, 15-16, the claims are directed to a method that implements the same features as the method of claims 2, 4-5, respectively, and is therefore rejected for at least the same reasons therein.
As per claim 20, it is directed to a system that implements the same features as the method of claim 1, and is therefore rejected for at least the same reasons therein.
As per claim 21, 23-24, the claims are directed to a system that implements the same features as the method of claims 2, 4-5, respectively, and is therefore rejected for at least the same reasons therein.
As per claim 26-28, the claims are directed to a system that implements the same features as the method of claims 7-9, respectively, and is therefore rejected for at least the same reasons therein.
As per claim 31, it is directed to a system that implements the same features as the method of claim 1, and is therefore rejected for at least the same reasons therein.
Claims 3, 10, 14, 18, 22, 29, 32 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard/Witek in further view of Siu et al. (US 20060101244 A1, hereinafter “Siu”).
As per claim 3, while Goddard teaches the FPU may comprise multiple arithmetic units (col 6 line 65- col 7 line 7), Goddard does not explicitly teach arithmetic units for floating-point maximum or minimum. Thus, Goddard does not teach wherein the floating point arithmetic operation is selected from one of maximum, minimum, max-reduce, or min-reduce.
Siu teaches wherein the floating point arithmetic operation is selected from one of maximum, minimum, max-reduce, or min-reduce (Siu: Fig. 3; [0053] of note FMAX and FMIN operations).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the FPU of Goddard with the floating-point unit of Siu. One would have been motivated to combine these references because both references disclose arithmetic units performing floating-point operations, and the combination renders an improved method that allows for a more robust processing technique that allows for more useful applications within the field (being capable of performing more floating-point operations).
As per claim 10, while Goddard teaches exception control may be operated by flags (Goddard: col 13 lines 9-16), Goddard does not explicitly disclose generating the flag. Thus, Goddard/Witek does not teach raising an out-of-bound flag if the output data is a positive infinity, a negative infinity, or a denormal number.
Siu teaches further comprising raising an out-of-bound flag if the output data is a positive infinity, a negative infinity, or a denormal number (Siu: [0300]; [0050], wherein special numbers include denormal and infinity).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the FPU of Goddard with the special flag number generation of Siu. One would have been motivated to combine these references because both references disclose arithmetic units performing floating-point operations, and combining prior art elements according to known methods to yield predictable results (generating the overflow flag).
As per claims 14 and 18, the claims are directed to a method that implements the same features as the method of claims 3 and 10, respectively, and is therefore rejected for at least the same reasons therein.
As per claims 22 and 29, the claims are directed to a system that implements the same features as the method of claims 3 and 10, respectively, and is therefore rejected for at least the same reasons therein.
As per claim 32, it is directed to a system that implements the same features as the method of claim 10 and is therefore rejected for at least the same reasons therein.
Claims 6, 17, 25 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard/in further view of Hinds et al. (US 5339266 A, hereinafter “Hinds”).
As per claim 6, while Goddard teaches the FPU may comprise multiple arithmetic units (col 6 line 65- col 7 line 7), Goddard does not explicitly teach arithmetic units for floating-point to integer conversion. Thus, Goddard does not teach wherein the floating point arithmetic operation is converting the input data from a floating point to an integer value.
Hinds teaches wherein the floating point arithmetic operation is converting the input data from a floating point to an integer value (Hinds: Fig. 1 element 18; col 3 lines 51-53).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the FADD of Goddard with the floating-point adder of Hinds. One would have been motivated to combine these references because both references disclose arithmetic units performing floating-point operations, and the combination renders an improved method that allows for a more robust processing technique that allows for more useful applications within the field (being capable of performing more floating-point operations).
As per claim 17, the claim is directed to a method that implements the same features as the method of claim 6, and is therefore rejected for at least the same reasons therein.
As per claim 25, the claim is directed to a system that implements the same features as the method of claim 6, and is therefore rejected for at least the same reasons therein.
Claims 11, 19, 30, 33 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard/in further view of Wilkins (US 20140195581 A1, hereinafter “Wilkins”).
As per claim 11, while Goddard teaches division-by-zero handling (Goddard: Table 1) and exception control may be operated by flags (Goddard: col 13 lines 9-16), Goddard does not explicitly disclose generating a divide-by-zero flag. Thus, Goddard does not teach raising a divide-by-zero flag when the floating point arithmetic operation is a division and wherein a dividend is a nonzero number and divisor is a zero number.
Wilkins teaches further comprising raising a divide-by-zero flag when the floating point arithmetic operation is a division and wherein a dividend is a nonzero number and divisor is a zero number (Wilkins: [0027]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the FPU of Goddard with the floating-point architecture of Wilkins. One would have been motivated to combine these references because both references disclose circuits capable of performing floating-point operations, and the combination renders an improved method that allows for a more robust processing technique that allows for more useful applications within the field (being capable of performing floating-point division operations).
As per claim 19, it is directed to a method that implements the same features as the method of claim 11 and is therefore rejected for at least the same reasons therein.
As per claim 30, it is directed to a system that implements the same features as the method of claim 11 and is therefore rejected for at least the same reasons therein.
As per claim 33, it is directed to a system that implements the same features as the method of claim 11 and is therefore rejected for at least the same reasons therein.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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