Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is non-final and is in response to claims filed on 04/22/2026 via RCE. Claims 1, 3-11, 13-18, 20-28, and 30-33 are pending for examination. Claims 1, 4, 11, 14, 18, 21, 28, and 30 are currently amended. Claims 3, 5-10, 13, 15-17, 20, 22-27, and 31-33 are as previously filed.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/22/2026 has been entered.
Response to Arguments
Double Patenting
The rejections of the claims under double patenting are maintained and will be held in abeyance until such time as claims are deemed allowable over the cited art.
Rejections Under 35 U.S.C. 101
Applicant’s arguments, see Remarks, filed 04/22/2026, with respect to claims 1, 3-11, 13-18, 20-28, and 30-33 have been fully considered and are persuasive. The rejections of the claims has been withdrawn.
Rejections Under 35 U.S.C. 112
Applicant’s arguments, see Remarks 1-17, with respect to the rejections under 35 U.S.C. 112(b) of claims 1, 3-11, 13-18, 20-28, and 30-33 have been fully considered and are persuasive. The rejections of claims 1, 3-11, 13-18, 20-28, and 30-33 has been withdrawn.
Claim interpretation
Applicant argues “The Specification discloses corresponding structures for the recited features, including a hardware embodiment in which a logic engine 120 and a convertor engine 130 are coupled with a floating point arithmetic operating unit/ALU 140 (see, e.g., Specification at [0018]-[0024], FIGS. 1-3), and a software embodiment in which a processor 1104 executes instructions stored in memory 1106 implementing a logic engine 1138 and a convertor engine 1141”. See Remarks 10.
Examiner notes under 35 U.S.C. 112(f), the state requires the means to include the hardware. and furthermore, the courts have held that the hardware alone is not sufficient. so the claim is actually hardware plus the disclosed algorithm. See MPEP 2181(II)(B).
Rejections Under 35 U.S.C. 103
Applicant’s arguments with respect to claims 1, 3-11, 13-18, 20-28 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 04/29/2026 is in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3-11, 13-18, 20-28, and 30-33 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-11, 14-18, 21-28, 30-33 of copending Application No. 17/686,682 (hereinafter, “the ‘682 application”) in view of Goddard et al. (US 5748516 A) hereinafter Goddard.
Current Application
The ‘682 Application
Claim 1
Claim 1
A computer-implemented method comprising: receiving a first input data and a second input data at a floating point arithmetic operating unit,
A computer-implemented method comprising: receiving an input data at a floating point arithmetic operating unit,
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively,
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data;
wherein the floating point operating unit is configured to perform a floating point arithmetic operation on each received input data using a single processing path;
determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
determining whether the input data is a quiet not-a-number (qnan) or whether the input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
and converting a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan,
and converting a value of the input data to a modified value prior to performing the floating point arithmetic operation if the input data is either the qnan or the snan,
wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the first input data is either the qnan or the snan.
wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the input data is either the qnan or the snan.
by using a same data path of the floating point arithmetic operating unit to perform the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result.
by causing the floating point arithmetic operation to be performed on the input data using the single processing path to generate an output result
Claim 3
The method of Claim 1, wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation.
Claim 4
Claim 4
The method of Claim 1 further comprising determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
The method of claim 1 further comprising determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
Claim 5
Claim 5
The method of Claim 4 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
The method of claim 4 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 6
Claim 6
The method of Claim 4 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
The method of claim 4 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim 7
Claim 7
The method of Claim 1, wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the qnan.
The method of claim 1, wherein the converting of the value of the input data to the modified value is setting a value of the input data to zero if the input data is the qnan.
Claim 8
Claim 8
The method of Claim 7 further comprising generating an un-initialized flag associated with the first input data being the qnan.
The method of claim 7 further comprising generating an un-initialized flag associated with the input data.
Claim 9
Claim 9
The method of Claim 1, wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the snan.
The method of claim 1, wherein the converting of the value of the input data to the modified value is setting a value of the input data to zero if the input data is the snan.
Claim 10
Claim 10
The method of Claim 9 further comprising generating an un-initialized flag associated with the first input data being the snan.
The method of claim 9 further comprising generating an un-initialized flag associated with the converting.
Claim 11
Claim 11
A computer-implemented method comprising: receiving a first input data and a second input data at a floating point arithmetic operating unit,
A computer-implemented method comprising: receiving an input data at a floating point arithmetic operating unit,
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively,
wherein the floating point arithmetic operating unit is configured to perform a floating point arithmetic operation on the first input data and the second input data;
wherein the floating point operating unit is configured to perform a floating point arithmetic operation on each received input data using a single processing path;
determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
determining whether the received input data is a quiet not-a-number (qnan) or whether the received input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation
and setting the first input data to zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation.
setting the input data to value zero if the input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation on the input data by the floating point operating unit.
And performing, using a same data path of the floating point arithmetic operating unit, the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result.
and wherein the setting causes the floating point arithmetic operation to be performed on the input data using the single processing path to generate an output result
Claim 13
The method of Claim 11, wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation.
Claim 14
Claim 14
The method of Claim 11 further comprising determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
The method of claim 11 further comprising determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
Claim 15
Claim 15
The method of Claim 14 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
The method of claim 14 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 16
Claim 16
The method of Claim 14 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
The method of claim 14 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim 17
Claim 17
The method of Claim 11 further comprising generating an un-initialized flag associated with the first input data being the qnan or snan.
The method of claim 11 further comprising generating an un-initialized flag associated with the input data in response to the setting.
Claim 18
Claim 18
A system comprising: a logic engine configured to receive a first input data and a second input data at a floating point arithmetic operating unit,
A system comprising: a logic engine configured to receive an input data at a floating point arithmetic operating unit,
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively,
wherein the floating point arithmetic operating unit is configured to perform a floating point arithmetic operation on the first input data and the second input data,
wherein the floating point operating unit is configured to perform a floating point arithmetic operation on each received input data using a single processing path,
determine whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
determine whether the received input data is a quiet not-a-number (qnan) or whether the received input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
and a convertor engine configured to convert a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan, wherein the converting eliminates special handling by the floating point arithmetic operating unit on the first input data being either the qnan or the snan;
and a convertor engine configured to convert a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is either the qnan or the snan, wherein the converting eliminates special handling
and an arithmetic logic unit configured to perform, using a same data path, the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result
by causing the floating point arithmetic operation to be performed on the input data using the single processing path to generate an output result.
Claim 20
The system of Claim 18, wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation.
Claim 21
Claim 21
The system of Claim 18, wherein the logic engine is configured to determine whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
The system of claim 18, wherein the logic engine is configured to determine whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
Claim 22
Claim 22
The system of Claim 21, wherein the logic engine is configured to set a value of the output result to zero if a value of the output result is a denormal number.
The system of claim 21, wherein the logic engine is configured to set a value of the output result to zero if a value of the output result is a denormal number.
Claim 23
Claim 23
The system of Claim 21, wherein the logic engine is configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
The system of claim 21, wherein the logic engine is configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim 24
Claim 24
The system of Claim 18, wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the qnan.
The system of claim 18, wherein the convertor engine is configured to set a value of the input data to zero if the input data is the qnan.
Claim 25
Claim 25
The system of Claim 24, wherein the logic engine is configured to generate an un- initialized flag associated with the first input data being qnan.
The system of claim 24, wherein the logic engine is configured to generate an un-initialized flag associated with the input data being qnan.
Claim 26
Claim 26
The system of Claim 18, wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the snan.
The system of claim 18, wherein the convertor engine is configured to set a value of the input data to zero if the input data is the snan.
Claim 27
Claim 27
The system of Claim 26, wherein the logic engine is configured to generate an un- initialized flag associated with the input data being snan.
The system of claim 26, wherein the logic engine is configured to generate an un-initialized flag associated with the input data being snan.
Claim 28
Claim 28
A system comprising: a means for receiving a first input data and a second input data at a floating point arithmetic operating unit,
A system comprising: a means for receiving an input data at a floating point arithmetic operating unit,
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively,
wherein the floating point arithmetic operating unit is configured to perform a floating point arithmetic operation on the first input data and the second input data;
wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data;
a means for determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
a means for determining whether the received input data is a quiet not-a-number (qnan) or whether the received input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
and a means for setting the first input data to zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation
and a means for setting the input data to value zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation on the input data by the floating point operating unit
and a means for performing, using a same data path, the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result, wherein the performing occurs after the setting.
wherein the setting occurs prior to performing the floating point arithmetic operation on the input data by the floating point operating unit, and wherein the setting causes the floating point arithmetic operation to be performed on the input data using the single processing path to generate an output result
Claim 30
Claim 30
The system of Claim 28 further comprising a means for determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
The system of claim 28 further comprising a means for determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
Claim 31
Claim 31
The system of Claim 30 further comprising a means for setting a value of the output result to zero if a value of the output result is a denormal number.
The system of claim 30 further comprising a means for setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 32
Claim 32
The system of Claim 30 further comprising a means for setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
The system of claim 30 further comprising a means for setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim 33
Claim 33
The system of Claim 28 further comprising a means for generating an un-initialized flag associated with the first input data being the qnan or snan.
The system of claim 28 further comprising a means for generating an un-initialized flag associated with the input data in response to determining that the received input data is a qnan or a snan
As per claim 1, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach multiple inputs, wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, or wherein the floating point operating arithmetic unit is configured to perform the floating point arithmetic operation on the first input data and the second input data. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the multiple inputs, the inputs being associated with floating point arithmetic operations, and performing arithmetic operations on the input data as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 3, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation. Goddard teaches wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283; Goddard Tables 1-3: show multiplication, division, addition, and subtraction can be performed).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the operations as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 11, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach multiple inputs, wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, or wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the multiple inputs, the inputs being associated with floating point arithmetic operations, and performing arithmetic operations on the input data as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 13, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min- reduce operation, a multiplication operation, or a division operation. Goddard teaches wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min- reduce operation, a multiplication operation, or a division operation (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283; Goddard Tables 1-3: show multiplication, division, addition, and subtraction can be performed).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the operations as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 18, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach multiple inputs, wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, or wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the multiple inputs, the inputs being associated with floating point arithmetic operations, and performing arithmetic operations on the input data as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 20, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min- reduce operation, a multiplication operation, or a division operation. Goddard teaches wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min- reduce operation, a multiplication operation, or a division operation (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283; Goddard Tables 1-3: show multiplication, division, addition, and subtraction can be performed).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the operations as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 28, the ‘682 application teaches the language as shown in the table above. However Patent ‘247 does not teach multiple inputs, wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, or wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the multiple inputs, the inputs being associated with floating point arithmetic operations, and performing arithmetic operations on the input data as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim 28 recites “a means for receiving a first input data and a second input data”, “a means for determining whether the first input data is a”, and “a means for setting the first input data to zero”.
Claim 29 recites “a means for performing the floating point arithmetic operation”.
Claim 30 recites “a means for determining whether the output result”.
Claim 31 recites “a means for setting a value of the output result”.
Claim 32 recites “a means for setting a value of the output result to a”.
Claim 33 recites “a means for generating an un-initialized”.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a logic engine” and “a convertor engine” in claim 18.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
The specification recites “it is appreciated that the logic engine 120 may be implemented in hardware” in paragraph [0018].
The specification recites “the convertor engine 130 may be integrated within a same processing block” in paragraph [0021].
If applicant prefers the claims to be interpreted as software per se, applicant should amend the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 7, 9, 11, 13-14, 18, 20-21, 24, 26,28, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard et al. (US 5748516 A) hereinafter Goddard in view of Harada et al. (US 20070257824 A1) hereinafter Harada further in view of Lutz et al. (US 20200257499 A1), as provided in the IDS filed 04/29/2026, hereinafter Lutz.
With regards to claim 1 Goddard teaches A computer-implemented method comprising: receiving a first input data and a second input data at a floating point arithmetic operating unit, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: table 3 shows that qnan and snan numbers can be detected)
[by using a same data path] of the floating point arithmetic operating unit to perform the floating point arithmetic operation on the second input data and the first input data [that has been modified] to generate an output result (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283).
Goddard fails to teach and converting a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan, wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the first input data is either the qnan or the snan, and by using a same data path [of the floating point arithmetic operating unit to perform the floating point arithmetic operation on the second input data and the first input data] that has been modified [to generate an output result].
However, Harada does teach and converting a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan, (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i))
wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the first input data is either the qnan or the snan (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i))
[by using a same data path of the floating point arithmetic operating unit to perform the floating point arithmetic operation on the second input data and the first input data] that has been modified [to generate an output result] (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with the converting of nans as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
Goddard in view of Harada fails to teach by using a same data path [of the floating point arithmetic operating unit to perform the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result].
However, Lutz teaches by using a same data path [of the floating point arithmetic operating unit to perform the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result] (Lutz [0007]: when the overflow or underflow is detected, restoring the checkpoint of architectural state, changing a format of the anchored-data value, and retrying said portion of the sequence of data processing operations based on the changed format and the restored checkpoint of architectural state; Lutz Fig. 1: shows the processing circuitry; Lutz Fig. 8: shows a detailed view of the processing circuitry).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with using one data path as taught by Lutz. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of the system as loading large quantities of FP numbers from memory reduces to simple and efficient contiguous vector loads as taught by Lutz (Lutz [0200]). This would also increase the efficiency of the system as the processing could continue without switching the data to a different path.
With regards to claim 3, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 1 above. Goddard further teaches wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283; Goddard Tables 1-3: show multiplication, division, addition, and subtraction can be performed).
With regards to claim 4, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 1 above. Goddard further teaches determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception (Goddard Col. 8 Lines 56-60: Depending on the floating point operation (e.g., add, multiply, divide, etc.) and the particular operand condition detected, arithmetic results may be forced by either FPDET 220 or FRND 250, thereby bypassing the normal flow through the arithmetic units; Goddard Tables 1-3: show determining if the output would be a qnan, snan, infinity, or an invalid operation).
With regards to claim 7, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 1 above. Goddard further teaches [wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the] qnan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the [qnan].
However, Harada does teach wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the [qnan] (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with setting the input to zero if it is a nan as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 9, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 1 above. Goddard further teaches [wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the] snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the [snan].
However, Harada does teach wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the [snan] (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with setting the input to zero if it is a nan as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 11, Goddard teaches A computer-implemented method comprising: receiving a first input data and a second input data at a floating point arithmetic operating unit, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: table 3 shows that qnan and snan numbers can be detected)
and performing, [by using a same data path] of the floating point arithmetic operating unit, the floating point arithmetic operation on the second input data and the first input data [that has been modified] to generate an output result (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283).
Goddard fails to teach and setting the first input data to zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation by [and performing,] using a same data path [of the floating point arithmetic operating unit, the floating point arithmetic operation on the second input data and the first input data] that has been modified [to generate an output result].
However, Harada does teach and setting the first input data to zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i))
[and performing, using a same data path of the floating point arithmetic operating unit, the floating point arithmetic operation on the second input data and the first input data] that has been modified [to generate an output result] (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with the converting of nans as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
Goddard in view of Harada fails to teach [and performing,] using a same data path [of the floating point arithmetic operating unit, the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result].
However, Lutz teaches [and performing,] using a same data path [of the floating point arithmetic operating unit, the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result] (Lutz [0007]: when the overflow or underflow is detected, restoring the checkpoint of architectural state, changing a format of the anchored-data value, and retrying said portion of the sequence of data processing operations based on the changed format and the restored checkpoint of architectural state; Lutz Fig. 1: shows the processing circuitry; Lutz Fig. 8: shows a detailed view of the processing circuitry).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with using one data path as taught by Lutz. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of the system as loading large quantities of FP numbers from memory reduces to simple and efficient contiguous vector loads as taught by Lutz (Lutz [0200]). This would also increase the efficiency of the system as the processing could continue without switching the data to a different path.
With regards to claim 13, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 11 above. Goddard further teaches wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283; Goddard Tables 1-3: show multiplication, division, addition, and subtraction can be performed).
With regards to claim 14, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 11 above. Goddard further teaches determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception (Goddard Col. 8 Lines 56-60: Depending on the floating point operation (e.g., add, multiply, divide, etc.) and the particular operand condition detected, arithmetic results may be forced by either FPDET 220 or FRND 250, thereby bypassing the normal flow through the arithmetic units; Goddard Tables 1-3: show determining if the output would be a qnan, snan, infinity, or an invalid operation).
With regards to claim 18 Goddard teaches A system comprising: a logic engine configured to receive a first input data and a second input data at a floating point arithmetic operating unit, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
determine whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: table 3 shows that qnan and snan numbers can be detected)
and an arithmetic logic unit configured to perform, [using a same data path,] the floating point arithmetic operation on the second input data and the first input data [that has been modified] to generate an output result (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283).
Goddard fails to teach a convertor engine configured to convert a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan, and wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the first input data is either the qnan or the snan, [and an arithmetic logic unit configured to perform,] using a same data path, [the floating point arithmetic operation on the second input data and the first input data] that has been modified [to generate an output result].
However, Harada does teach a convertor engine configured to convert a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan, (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i))
wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the first input data is either the qnan or the snan (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i))
[and an arithmetic logic unit configured to perform, using a same data path, the floating point arithmetic operation on the second input data and the first input data] that has been modified [to generate an output result] (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with the converting of nans as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
Goddard in view of Harada fails to teach [and an arithmetic logic unit configured to perform,] using a same data path, [the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result].
However, Lutz teaches [and an arithmetic logic unit configured to perform,] using a same data path, [the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result] (Lutz [0007]: when the overflow or underflow is detected, restoring the checkpoint of architectural state, changing a format of the anchored-data value, and retrying said portion of the sequence of data processing operations based on the changed format and the restored checkpoint of architectural state; Lutz Fig. 1: shows the processing circuitry; Lutz Fig. 8: shows a detailed view of the processing circuitry).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with using one data path as taught by Lutz. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of the system as loading large quantities of FP numbers from memory reduces to simple and efficient contiguous vector loads as taught by Lutz (Lutz [0200]). This would also increase the efficiency of the system as the processing could continue without switching the data to a different path.
With regards to claim 20, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 18 above. Goddard further teaches wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283; Goddard Tables 1-3: show multiplication, division, addition, and subtraction can be performed).
With regards to claim 21, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 18 above. Goddard further teaches wherein the logic engine is configured to determine whether the output result of the floating point arithmetic operation generates a floating point hardware exception (Goddard Col. 8 Lines 56-60: Depending on the floating point operation (e.g., add, multiply, divide, etc.) and the particular operand condition detected, arithmetic results may be forced by either FPDET 220 or FRND 250, thereby bypassing the normal flow through the arithmetic units; Goddard Tables 1-3: show determining if the output would be a qnan, snan, infinity, or an invalid operation).
With regards to claim 24, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 18 above. Goddard further teaches [wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the] qnan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the [qnan].
However, Harada does teach wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the [qnan] (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with setting the input to zero if it is a nan as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 26, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 18 above. Goddard further teaches [wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the] snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the [snan].
However, Harada does teach wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the [snan] (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with setting the input to zero if it is a nan as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 28 Goddard teaches A system comprising: a means for receiving a first input data and a second input data at a floating point arithmetic operating unit, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
a means for determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: table 3 shows that qnan and snan numbers can be detected)
and a means for performing, [using a same data path,] the floating point arithmetic operation on the second input data and the first input data [that has been modified] to generate an output result (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283).
Goddard fails to teach a means for setting the first input data to zero if the first input data is the qnan or the snan, [and a means for performing,] using a same data path, [the floating point arithmetic operation on the second input data and the first input data] that has been modified [to generate an output result], wherein the setting occurs prior to performing the floating point arithmetic operation.
However, Harada does teach a means for setting the first input data to zero if the first input data is the qnan or the snan, [and a means for performing, using a same data path, the floating point arithmetic operation on the second input data and the first input data] that has been modified [to generate an output result], wherein the setting occurs prior to performing the floating point arithmetic operation (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with the converting of nans as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
Goddard in view of Harada fails to teach [and a means for performing,] using a same data path, [the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result].
However, Lutz teaches [and a means for performing,] using a same data path, [the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result] (Lutz [0007]: when the overflow or underflow is detected, restoring the checkpoint of architectural state, changing a format of the anchored-data value, and retrying said portion of the sequence of data processing operations based on the changed format and the restored checkpoint of architectural state; Lutz Fig. 1: shows the processing circuitry; Lutz Fig. 8: shows a detailed view of the processing circuitry).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with using one data path as taught by Lutz. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of the system as loading large quantities of FP numbers from memory reduces to simple and efficient contiguous vector loads as taught by Lutz (Lutz [0200]). This would also increase the efficiency of the system as the processing could continue without switching the data to a different path.
With regards to claim 30, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 28 above. Goddard further teaches a means for determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception (Goddard Col. 8 Lines 56-60: Depending on the floating point operation (e.g., add, multiply, divide, etc.) and the particular operand condition detected, arithmetic results may be forced by either FPDET 220 or FRND 250, thereby bypassing the normal flow through the arithmetic units; Goddard Tables 1-3: show determining if the output would be a qnan, snan, infinity, or an invalid operation).
Claims 5, 15, 22, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard in view of Harada further in view of Lutz further in view of Valentine et al. (US 20190163474 A1) hereinafter Valentine.
With regards to claim 5, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 4 above. Goddard fails to teach setting a value of the output result to zero if a value of the output result is a denormal number.
However, Valentine does teach setting a value of the output result to zero if a value of the output result is a denormal number (Valentine [0182]: Bit 19, FZ16, when set, indicates that output FP16 denormal element results are flushed to zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada further in view of Lutz with setting the output to zero as taught by Valentine. One of ordinary skill in the art would be motivated to make this combination because the denormals-are-zeros FP16 mode improves processor performance as taught by Valentine (Valentine [0181]).
With regards to claim 15, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 14 above. Goddard fails to teach setting a value of the output result to zero if a value of the output result is a denormal number.
However, Valentine does teach setting a value of the output result to zero if a value of the output result is a denormal number (Valentine [0182]: Bit 19, FZ16, when set, indicates that output FP16 denormal element results are flushed to zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada further in view of Lutz with setting the output to zero as taught by Valentine. One of ordinary skill in the art would be motivated to make this combination because the denormals-are-zeros FP16 mode improves processor performance as taught by Valentine (Valentine [0181]).
With regards to claim 22, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 21 above. Goddard fails to teach wherein the logic engine is configured to set a value of the output result to zero if a value of the output result is a denormal number.
However, Valentine does teach wherein the logic engine is configured to set a value of the output result to zero if a value of the output result is a denormal number (Valentine [0182]: Bit 19, FZ16, when set, indicates that output FP16 denormal element results are flushed to zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada further in view of Lutz with setting the output to zero as taught by Valentine. One of ordinary skill in the art would be motivated to make this combination because the denormals-are-zeros FP16 mode improves processor performance as taught by Valentine (Valentine [0181]).
With regards to claim 31, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 30 above. Goddard fails to teach a means for setting a value of the output result to zero if a value of the output result is a denormal number.
However, Valentine does teach a means for setting a value of the output result to zero if a value of the output result is a denormal number (Valentine [0182]: Bit 19, FZ16, when set, indicates that output FP16 denormal element results are flushed to zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada further in view of Lutz with setting the output to zero as taught by Valentine. One of ordinary skill in the art would be motivated to make this combination because the denormals-are-zeros FP16 mode improves processor performance as taught by Valentine (Valentine [0181]).
Claims 6, 16, 23, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard in view of Harada further in view of Lutz further in view of Wilkins et al. (US 20140195581 A1) hereinafter Wilkins.
With regards to claim 6, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 4 above. Goddard fails to teach setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
However, Wilkins does teach setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero)
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada further in view of Lutz with setting the output to its maximum or minimum value as taught by Wilkins. One of ordinary skill in the art would be motivated to make this combination because this would speed up calculations as there would not have to be any special handling of the infinity or minus infinity.
With regards to claim 16, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 14 above. Goddard fails to teach setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
However, Wilkins does teach setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero)
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada further in view of Lutz with setting the output to its maximum or minimum value as taught by Wilkins. One of ordinary skill in the art would be motivated to make this combination because this would speed up calculations as there would not have to be any special handling of the infinity or minus infinity.
With regards to claim 23, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 21 above. Goddard fails to teach wherein the logic engine is configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
However, Wilkins does teach wherein the logic engine is configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity, (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero)
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada further in view of Lutz with setting the output to its maximum or minimum value as taught by Wilkins. One of ordinary skill in the art would be motivated to make this combination because this would speed up calculations as there would not have to be any special handling of the infinity or minus infinity.
With regards to claim 32, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 30 above. Goddard fails to teach a means for setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
However, Wilkins does teach a means for setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero)
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada further in view of Lutz with setting the output to its maximum or minimum value as taught by Wilkins. One of ordinary skill in the art would be motivated to make this combination because this would speed up calculations as there would not have to be any special handling of the infinity or minus infinity.
Claims 8, 10, 17, 25, 27, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard in view of Harada further in view of Lutz further in view of Vorbach et al. (US 20190377580 A1) hereinafter Vorbach.
With regards to claim 8, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 7 above. Goddard further teaches [generating an un-initialized flag associated with the first input data being the] qnan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach generating an un-initialized flag associated with the first input data being the [qnan].
However, Vorbach does teach generating an un-initialized flag associated with the first input data being the [qnan] (Vorbach [0383]: Floating point ALUs may additionally produce floating point specific flags such as NaN (not a number)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada further in view of Lutz with generating the flag as taught by Vorbach. One of ordinary skill in the art would be motivated to make this combination because such information can be for instance flags… This is useful in particular for branching as taught by Vorbach (Vorbach [0180]-[0181]). Also, flags would make calculations easier as the FPU would know what type of input an operand is.
With regards to claim 10, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 9 above. Goddard further teaches [generating an un-initialized flag associated with the first input data being the] snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach generating an un-initialized flag associated with the first input data being the [snan].
However, Vorbach does teach generating an un-initialized flag associated with the first input data being the [snan] (Vorbach [0383]: Floating point ALUs may additionally produce floating point specific flags such as NaN (not a number)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada further in view of Lutz with generating the flag as taught by Vorbach. One of ordinary skill in the art would be motivated to make this combination because such information can be for instance flags… This is useful in particular for branching as taught by Vorbach (Vorbach [0180]-[0181]). Also, flags would make calculations easier as the FPU would know what type of input an operand is.
With regards to claim 17, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 11 above. Goddard further teaches [generating an un-initialized flag associated with the first input data being the] qnan or snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach generating an un-initialized flag associated with the first input data being the [qnan or snan].
However, Vorbach does teach generating an un-initialized flag associated with the first input data being the [qnan or snan] (Vorbach [0383]: Floating point ALUs may additionally produce floating point specific flags such as NaN (not a number)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada further in view of Lutz with generating the flag as taught by Vorbach. One of ordinary skill in the art would be motivated to make this combination because such information can be for instance flags… This is useful in particular for branching as taught by Vorbach (Vorbach [0180]-[0181]). Also, flags would make calculations easier as the FPU would know what type of input an operand is.
With regards to claim 25, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 24 above. Goddard further teaches [wherein the logic engine is configured to generate an un- initialized flag associated with the first input data being] qnan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach wherein the logic engine is configured to generate an un- initialized flag associated with the first input data being [qnan].
However, Vorbach does teach wherein the logic engine is configured to generate an un- initialized flag associated with the first input data being [qnan] (Vorbach [0383]: Floating point ALUs may additionally produce floating point specific flags such as NaN (not a number)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada further in view of Lutz with generating the flag as taught by Vorbach. One of ordinary skill in the art would be motivated to make this combination because such information can be for instance flags… This is useful in particular for branching as taught by Vorbach (Vorbach [0180]-[0181]). Also, flags would make calculations easier as the FPU would know what type of input an operand is.
With regards to claim 27, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 26 above. Goddard further teaches [wherein the logic engine is configured to generate an un- initialized flag associated with the first input data being] snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach wherein the logic engine is configured to generate an un- initialized flag associated with the first input data being [snan].
However, Vorbach does teach wherein the logic engine is configured to generate an un- initialized flag associated with the first input data being [snan] (Vorbach [0383]: Floating point ALUs may additionally produce floating point specific flags such as NaN (not a number)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada further in view of Lutz with generating the flag as taught by Vorbach. One of ordinary skill in the art would be motivated to make this combination because such information can be for instance flags… This is useful in particular for branching as taught by Vorbach (Vorbach [0180]-[0181]). Also, flags would make calculations easier as the FPU would know what type of input an operand is.
With regards to claim 33, Goddard in view of Harada further in view of Lutz teaches all of the limitations of claim 28 above. Goddard further teaches [a means for generating an un-initialized flag associated with the first input data being the] qnan or snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach a means for generating an un-initialized flag associated with the first input data being the [qnan or snan].
However, Vorbach does teach a means for generating an un-initialized flag associated with the first input data being the [qnan or snan] (Vorbach [0383]: Floating point ALUs may additionally produce floating point specific flags such as NaN (not a number)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada further in view of Lutz with generating the flag as taught by Vorbach. One of ordinary skill in the art would be motivated to make this combination because such information can be for instance flags… This is useful in particular for branching as taught by Vorbach (Vorbach [0180]-[0181]). Also, flags would make calculations easier as the FPU would know what type of input an operand is.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jakob O Gudas whose telephone number is (571)272-0695. The examiner can normally be reached Monday-Thursday: 7:30AM-5:00PM Friday: 7:30AM-4:00PM.
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/J.O.G./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
