Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is final and is in response to claims filed on 09/25/2025 via amendment. Claims 1-33 are pending for examination. Claims 1, 11, 18, and 28 are currently amended. Claims 2-10, 12-17, 19-27, and 29-33 are as originally filed.
Response to Arguments
Claim Objections
Applicant has amended the claims at issue and therefore the previous claim objections have been withdrawn.
Double Patenting
The rejections of the claims under double patenting are maintained and will be held in abeyance until such time as claims are deemed allowable over the cited art,
Rejections Under 35 U.S.C. 112
Applicant’s arguments regarding the 35 U.S.C. 112 rejections have been fully considered. With regards to the rejections of claim 18 under 35 U.S.C. 112, Applicant argues “that the instant application in paragraph 18 explicitly discloses that ‘the logic engine 120 may be implemented in hardware’.” And that one of ordinary skill in the art would recognize logic components such as gates may be used by the logic engine. See Remarks 9.
Examiner respectfully disagrees with Applicant’s arguments. It is unclear what the structure of these units actually is/are. It is unclear if this these units are hardware, software, or a combination of both. The specification of the instant application discloses “It is appreciated that the logic engine 120 may be implemented in software according to one nonlimiting example” in paragraph 18. Based on this language in the disclosure, Applicant appears to be claiming anything and everything.
Applicant further argues that “One of ordinary skill in the art would appreciate that the converter engine could be implemented in a number of different ways”. See Remarks 9.
Examiner respectfully disagrees with applicant’s arguments. The converter engine, similar to the logic engine, could also be implemented in software, hardware, or as a combination of software and hardware.
With regards to the rejections of claims 28-32 under 35 U.S.C. 112, Applicant argues “that the ‘means for receiving a first input data and a second input data’, ‘a means for determining whether the first input data is a quiet not-a-number’, and ‘a means for setting the first input data to zero if the first input data’ is performed by the logic engine and converter engine”. See Remarks 10.
Examiner respectfully disagrees with Applicant’s arguments. Again, it is unclear what the structure of these units actually is/are. It is unclear if this these units are hardware, software, or a combination of both. The specification of the instant application discloses “It is appreciated that the logic engine 120 may be implemented in software according to one nonlimiting example” in paragraph 18. Based on this language in the disclosure, Applicant appears to be claiming anything and everything. The converter engine, similar to the logic engine, could also be implemented in software, or as a combination of software and hardware.
With regards to the rejections of claim 33 under 35 U.S.C. 112, Applicant argues “that the means for generating an un-initialized flag is generated by the logic engine”. See Remarks 10-11.
Examiner respectfully disagrees with Applicant’s arguments. Again, It is unclear what the structure of these units actually is/are. It is unclear if this these units are hardware, software, or a combination of both. The specification of the instant application discloses “It is appreciated that the logic engine 120 may be implemented in software according to one nonlimiting example” in paragraph 18. Based on this language in the disclosure, Applicant appears to be claiming anything and everything.
For the reasons stated above, the rejections under 35 U.S.C. 112 are maintained.
Rejections Under 35 U.S.C. 101
Applicants arguments regarding the 35 U.S.C. 101 rejections have been fully considered. Applicant argues that “claim 1 is inextricably intertwined and necessarily rooted in computer technology” and points to paragraphs 2-3 of the application arguing that “the problem of handling FP exceptions is inextricably intertwined and necessarily rooted in computer technology”. See Remarks 12. Applicant further argues that “the claim improves a computer-related technology” citing paragraphs 14-17 of the application arguing that “additional data paths for handling FP exceptions is eliminated, reducing hardware footprint, power consumptions, and complexity”. See Remarks 13.
Examiner respectfully disagrees with Applicant’s arguments. Merely adding a general computing circuit is a clear “apply it” scenario using generic computer components. MPEP 2106.05(f). The floating point arithmetic operating unit, the logic engine, the converter engine, the means for receiving a first input data and a second input data, the means for determining, the means for setting the first input data to zero, etc. do not denote any specific structure and is merely a generic circuit component performing the abstract ideas (the floating point arithmetic operation, determining if the first input is a qnan or snan, converting the first input, the addition operation, the subtraction operation, the add-reduce operation, the maximum operation, the minimum operation, the max-reduce operation, the min-reduce operation, the multiplication operation, the division operation, the generating an un-initialized flag, etc.).
It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements. See the discussion of Diamond v. Diehr, 450 U.S. 175, 187 and 191-92, 209 USPQ 1, 10 (1981)) in subsection II, below. In addition, the improvement can be provided by the additional element(s) in combination with the recited judicial exception... However, it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology...”. See MPEP 2106.05(a).
For the reasons stated above, the rejections under 35 U.S.C. 101 are maintained.
Rejections Under 35 U.S.C. 103
Applicants arguments regarding the 35 U.S.C. 103 rejections have been fully considered. Applicant argues that “Goddard fails to teach or suggest determining whether the first input data is a qnan or snan”. See Remarks 15.
Examiner respectfully disagrees with Applicant’s arguments. Examiner encourages applicant to further review the preceding paragraphs of column 8 of Goddard which further clarify the structure of the cited figure 2. Specifically, Goddard recites “Detected condition signals are provided to control logic, FCNTL 262, over a series of control lines represented collectively as control bus 278. Based on operand conditions so detected, FCNTL 262 drives control signals over the lines of control bus 278 to an arithmetic execution unit (e.g., FADD 230 or FMUL 241) or units, to FPDET 220, and to FRND 250” which shows that the operand conditions are detected before the arithmetic operation is performed.
Applicant further argues that “Harada does not teach or suggest qnan or snan”. See Remarks 15-16.
Examiner respectfully disagrees with Applicant’s arguments. Goddard teaches of detecting qnan and snan and Harada teaches of converting a number based on if it is nan.
Applicant further argues that “one of ordinary skill in the art would not be motivated to modify the teachings of Goddard with that of Harada as it would render Goddard unsatisfactory for its intended purpose”. See Remarks 16. Applicant further argues that “in Goddard, the arithmetic unit is prevented from generating a result on the round bus and that Harada does perform the arithmetic operation”. See Remarks 16.
Examiner respectfully disagrees with Applicant’s arguments. Neither Goddard nor Harada actively teach away from one another. Goddard does not explicitly prevent any and all output to occur and Harada is merely modifying the outputs (via the forced results) of Goddard to further specify the converting of the NaNs. Goddard explicitly requires arithmetic operations to occur at various components in the system, including the FRND and the FPDET (See Goddard cols. 9-10: Tables 1-3). Nothing in Goddard states that one of ordinary skill cannot convert NaNs nor cannot output results of any and all operations. Furthermore, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Applicant further argues that “Goddard fails to teach or suggest determining whether the output result will generate an exception”. See Remarks 17.
Examiner respectfully disagrees with Applicant’s arguments. The claim as written merely states that the method determines if an output would generate a floating point exception. As stated in the office action mailed 07/09/2025, Goddard determines if the output would generate a floating point exception in tables 1-3. Examiner encourages to review Goddard Column 15 Lines 1-14 which further clarify the structure of the cited figure 2. Specifically Goddard recites “The output multiplexer, ROUTMUX 556, implements logic to select the significand and exponent constituents corresponding to a rounded result value, while the remaining functional blocks are responsible for supplying candidate result constituents corresponding to the floating point value received from round bus 276 and in accordance with the IEEE rounding mode selected and with possible numerical overflow or underflow situations. ROUTMUX 556 selects from candidate constituents supplied by the other functional blocks and from internally generated constituents corresponding to result values”.
Applicant further argues that “Vorbach fails to teach or suggest the un-initialized flag of the present application.”
Examiner respectfully disagrees with Applicant’s arguments. The flag of Vorbach performs the same function as that of the present application, it is just not called an un-initialized flag.
For the reasons stated above, the rejections under 35 U.S.C. 103 are maintained.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on 07/16/2025 and 09/10/2025 are in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. They have been placed in the application file, and the information referred to therein has been considered as to the merits.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-33 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4-12, 14-19, 21-33 of copending Application No. 17/686,682 (hereinafter, “the ‘682 application”) in view of Goddard et al. (US 5748516 A) hereinafter Goddard.
Current Application
The ‘682 Application
Claim 1
Claim 1
A computer-implemented method comprising: receiving a first input data and a second input data at a floating point arithmetic operating unit,
A computer-implemented method comprising: receiving an input data at a floating point arithmetic operating unit,
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively,
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data;
wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data;
determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
determining whether the received input data is a quiet not-a-number (qnan) or whether the received input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
and converting a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan,
and converting a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is either the qnan or the snan,
wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the first input data is either the qnan or the snan.
wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the input data is either the qnan or the snan.
Claim 2
Claim 2
The method of Claim 1 further comprising performing the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result.
The method of claim 1 further comprising performing the floating point arithmetic operation on the input data with the modified value to generate an output result.
Claim 3
The method of Claim 1, wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation.
Claim 4
Claim 4
The method of Claim 2 further comprising determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
The method of claim 2 further comprising determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
Claim 5
Claim 5
The method of Claim 4 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
The method of claim 4 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 6
Claim 6
The method of Claim 4 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
The method of claim 4 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim 7
Claim 7
The method of Claim 1, wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the qnan.
The method of claim 1, wherein the converting of the value of the received input data to the modified value is setting a value of the input data to zero if the input data is the qnan.
Claim 8
Claim 8
The method of Claim 7 further comprising generating an un-initialized flag associated with the first input data being the qnan.
The method of claim 7 further comprising generating an un-initialized flag associated with the input data.
Claim 9
Claim 9
The method of Claim 1, wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the snan.
The method of claim 1, wherein the converting of the value of the received input data to the modified value is setting a value of the input data to zero if the input data is the snan.
Claim 10
Claim 10
The method of Claim 9 further comprising generating an un-initialized flag associated with the first input data being the snan.
The method of claim 9 further comprising generating an un-initialized flag associated with the converting.
Claim 11
Claim 11
A computer-implemented method comprising: receiving a first input data and a second input data at a floating point arithmetic operating unit,
A computer-implemented method comprising: receiving an input data at a floating point arithmetic operating unit,
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively,
wherein the floating point arithmetic operating unit is configured to perform a floating point arithmetic operation on the first input data and the second input data;
wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data;
determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
determining whether the received input data is a quiet not-a-number (qnan) or whether the received input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation
and setting the first input data to zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation.
setting the input data to value zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation on the input data by the floating point operating unit.
Claim 12
Claim 12
The method of Claim 11 further comprising performing the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result.
The method of claim 11 further comprising performing the floating point arithmetic operation on the input data with the set zero value to generate an output result.
Claim 13
The method of Claim 11, wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation.
Claim 14
Claim 14
The method of Claim 12 further comprising determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
The method of claim 12 further comprising determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
Claim 15
Claim 15
The method of Claim 14 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
The method of claim 14 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 16
Claim 16
The method of Claim 14 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
The method of claim 14 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim 17
Claim 17
The method of Claim 11 further comprising generating an un-initialized flag associated with the first input data being the qnan or snan.
The method of claim 11 further comprising generating an un-initialized flag associated with the input data in response to the setting.
Claim 18
Claim 18
A system comprising: a logic engine configured to receive a first input data and a second input data at a floating point arithmetic operating unit,
A system comprising: a logic engine configured to receive an input data at a floating point arithmetic operating unit,
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively,
wherein the floating point arithmetic operating unit is configured to perform a floating point arithmetic operation on the first input data and the second input data,
wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data,
determine whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
determine whether the received input data is a quiet not-a-number (qnan) or whether the received input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
and a convertor engine configured to convert a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan,
and a convertor engine configured to convert a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is either the qnan or the snan,
Claim 19
Claim 19
The system of Claim 18 further comprising said arithmetic floating point operating unit configured to perform the floating point arithmetic operation on the first input data that has been modified and on the second input data to generate an output result.
The system of claim 18 further comprising said arithmetic floating point operating unit configured to perform the floating point arithmetic operation on the input data with the modified value to generate an output result
Claim 20
The system of Claim 18, wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation.
Claim 21
Claim 21
The system of Claim 19, wherein the logic engine is configured to determine whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
The system of claim 19, wherein the logic engine is configured to determine whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
Claim 22
Claim 22
The system of Claim 21, wherein the logic engine is configured to set a value of the output result to zero if a value of the output result is a denormal number.
The system of claim 21, wherein the logic engine is configured to set a value of the output result to zero if a value of the output result is a denormal number.
Claim 23
Claim 23
The system of Claim 21, wherein the logic engine is configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
The system of claim 21, wherein the logic engine is configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim 24
Claim 24
The system of Claim 18, wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the qnan.
The system of claim 18, wherein the convertor engine is configured to set a value of the input data to zero if the input data is the qnan.
Claim 25
Claim 25
The system of Claim 24, wherein the logic engine is configured to generate an un- initialized flag associated with the first input data being qnan.
The system of claim 24, wherein the logic engine is configured to generate an un-initialized flag associated with the input data being qnan.
Claim 26
Claim 26
The system of Claim 18, wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the snan.
The system of claim 18, wherein the convertor engine is configured to set a value of the input data to zero if the input data is the snan.
Claim 27
Claim 27
The system of Claim 26, wherein the logic engine is configured to generate an un- initialized flag associated with the input data being snan.
The system of claim 26, wherein the logic engine is configured to generate an un-initialized flag associated with the input data being snan.
Claim 28
Claim 28
A system comprising: a means for receiving a first input data and a second input data at a floating point arithmetic operating unit,
A system comprising: a means for receiving an input data at a floating point arithmetic operating unit,
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively,
wherein the floating point arithmetic operating unit is configured to perform a floating point arithmetic operation on the first input data and the second input data;
wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data;
a means for determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
a means for determining whether the received input data is a quiet not-a-number (qnan) or whether the received input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
and a means for setting the first input data to zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation.
and a means for setting the input data to value zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation on the input data by the floating point operating unit.
Claim 29
Claim 29
The system of Claim 28 further comprising a means for performing the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result.
The system of claim 28 further comprising a means for performing the floating point arithmetic operation on the input data with the set zero value to generate an output result.
Claim 30
Claim 30
The system of Claim 29 further comprising a means for determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
The system of claim 29 further comprising a means for determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
Claim 31
Claim 31
The system of Claim 30 further comprising a means for setting a value of the output result to zero if a value of the output result is a denormal number.
The system of claim 30 further comprising a means for setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 32
Claim 32
The system of Claim 30 further comprising a means for setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
The system of claim 30 further comprising a means for setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim 33
Claim 33
The system of Claim 28 further comprising a means for generating an un-initialized flag associated with the first input data being the qnan or snan.
The system of claim 28 further comprising a means for generating an un-initialized flag associated with the input data in response to the setting.
As per claim 1, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach multiple inputs or wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the multiple inputs and the inputs being associated with floating point arithmetic operations as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 2, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach multiple inputs. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the multiple inputs as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 3, the ‘682 application does not teach the floating point arithmetic operations. Goddard teaches wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283; Goddard Tables 1-3: show multiplication, division, addition, and subtraction can be performed).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the floating point arithmetic operations as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operations to be performed, increasing flexibility.
As per claim 8, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach associated with the first input data being the qnan Goddard teaches associated with the first input data being the qnan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the first input being a qnan as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would signal to the system that the input is a qnan, increasing efficiency as the system would be aware when performing the calculations.
As per claim 10, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach associated with the first input data being the snan Goddard teaches associated with the first input data being the snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the first input being a snan as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would signal to the system that the input is a snan, increasing efficiency as the system would be aware when performing the calculations.
As per claim 11, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach multiple inputs or wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the multiple inputs and the inputs being associated with floating point arithmetic operations as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 12, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach multiple inputs. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the multiple inputs as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 13, the ‘682 application does not teach the floating point arithmetic operations. Goddard teaches wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation.(Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283; Goddard Tables 1-3: show multiplication, division, addition, and subtraction can be performed).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the floating point arithmetic operations as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operations to be performed, increasing flexibility.
As per claim 17, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach associated with the first input data being the qnan or snan Goddard teaches associated with the first input data being the qnan or snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the first input being a snan as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would signal to the system that the input is a snan, increasing efficiency as the system would be aware when performing the calculations.
As per claim 18, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach multiple inputs or wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the multiple inputs and the inputs being associated with floating point arithmetic operations as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 19, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach multiple inputs. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the multiple inputs as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 20, the ‘682 application does not teach the floating point arithmetic operations. Goddard teaches wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283; Goddard Tables 1-3: show multiplication, division, addition, and subtraction can be performed).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the floating point arithmetic operations as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operations to be performed, increasing flexibility.
As per claim 28, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach multiple inputs or wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the multiple inputs and the inputs being associated with floating point arithmetic operations as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 29, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach multiple inputs. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the multiple inputs as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 33, the ‘682 application teaches the language as shown in the table above. However the ‘682 application does not teach associated with the first input data being the qnan or snan Goddard teaches associated with the first input data being the qnan or snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of the ‘682 application with the first input being a snan as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would signal to the system that the input is a snan, increasing efficiency as the system would be aware when performing the calculations.
This is a provisional nonstatutory double patenting rejection.
Claims 1-33 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15-19, 21-28, and 33-36 of U.S. Patent No. 11301247 hereinafter Patent ‘247 in view of Goddard.
Current Application
U.S. Patent No. 11301247
Claim 1
Claim 15
A computer-implemented method comprising: receiving a first input data and a second input data at a floating point arithmetic operating unit,
A computer-implemented method comprising:
receiving a first input data at a floating point arithmetic operating unit for a FP arithmetic operation; receiving a second input data at the floating point arithmetic operating unit for the floating point operation;
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively,
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data;
determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
eliminating a floating point hardware exception responsive to the floating point arithmetic operation on the first and the second input data by performing one or more of: setting the first input data to zero if the first input data is a denormal number, a qnan (quiet not-a-number), or an snan (signaling not-a-number);
and converting a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan,
eliminating a floating point hardware exception responsive to the floating point arithmetic operation on the first and the second input data by performing one or more of: setting the first input data to zero if the first input data is a denormal number, a qnan (quiet not-a-number), or an snan (signaling not-a-number);
wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the first input data is either the qnan or the snan.
eliminating a floating point hardware exception responsive to the floating point arithmetic operation on the first and the second input data by performing one or more of: setting the first input data to zero if the first input data is a denormal number, a qnan (quiet not-a-number), or an snan (signaling not-a-number);
Claim 2
Claim 16
The method of Claim 1 further comprising performing the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result.
The method of claim 15 further comprising performing the floating point arithmetic operation on the first and the second input data or their modified values to generate an output result.
Claim 3
Claim 17
The method of Claim 1, wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation.
The method of claim 16, wherein the floating point arithmetic operation is selected from one of an addition operation, a subtraction operation, or an add-reduce operation.
Claim 4
The method of Claim 2 further comprising determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
Claim 5
Claim 18
The method of Claim 4 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
The method of claim 16 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 6
Claim 19
The method of Claim 4 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
The method of claim 16 further comprising setting a value of the output result to the maximum supported number if a value of the output result is a positive infinity,
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
and setting a value of the output result to the minimum supported number if a value of the output result is a negative infinity.
Claim 7
Claim 15
The method of Claim 1, wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the qnan.
setting the first input data to zero if the first input data is a denormal number, a qnan (quiet not-a-number), or an snan (signaling not-a-number);
Claim 8
Claim 21
The method of Claim 7 further comprising generating an un-initialized flag associated with the first input data being the qnan.
The method of claim 15 further comprising generating an un-initialized flag associated with qnan input data.
Claim 9
Claim 15
The method of Claim 1, wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the snan.
setting the first input data to zero if the first input data is a denormal number, a qnan (quiet not-a-number), or an snan (signaling not-a-number);
Claim 10
Claim 22
The method of Claim 9 further comprising generating an un-initialized flag associated with the first input data being the snan.
The method of claim 15 further generating an un-initialized flag associated with snan input data.
Claim 11
Claim 15
A computer-implemented method comprising: receiving a first input data and a second input data at a floating point arithmetic operating unit,
A computer-implemented method comprising:
receiving a first input data at a floating point arithmetic operating unit for a FP arithmetic operation; receiving a second input data at the floating point arithmetic operating unit for the floating point operation;
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively,
wherein the floating point arithmetic operating unit is configured to perform a floating point arithmetic operation on the first input data and the second input data;
determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
eliminating a floating point hardware exception responsive to the floating point arithmetic operation on the first and the second input data by performing one or more of: setting the first input data to zero if the first input data is a denormal number, a qnan (quiet not-a-number), or an snan (signaling not-a-number);
and setting the first input data to zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation.
eliminating a floating point hardware exception responsive to the floating point arithmetic operation on the first and the second input data by performing one or more of: setting the first input data to zero if the first input data is a denormal number, a qnan (quiet not-a-number), or an snan (signaling not-a-number);
Claim 12
Claim 16
The method of Claim 11 further comprising performing the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result.
The method of claim 15 further comprising performing the floating point arithmetic operation on the first and the second input data or their modified values to generate an output result.
Claim 13
Claim 17
The method of Claim 11, wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation.
The method of claim 16, wherein the floating point arithmetic operation is selected from one of an addition operation, a subtraction operation, or an add-reduce operation.
Claim 14
The method of Claim 12 further comprising determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
Claim 15
Claim 18
The method of Claim 14 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
The method of claim 16 further comprising setting a value of the output result to zero if a value of the output result is a denormal number.
Claim 16
Claim 19
The method of Claim 14 further comprising setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
The method of claim 16 further comprising setting a value of the output result to the maximum supported number if a value of the output result is a positive infinity,
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
and setting a value of the output result to the minimum supported number if a value of the output result is a negative infinity.
Claim 17
Claims 21 and 22
The method of Claim 11 further comprising generating an un-initialized flag associated with the first input data being the qnan or snan.
Claim 21: The method of claim 15 further comprising generating an un-initialized flag associated with qnan input data.
Claim 22: The method of claim 15 further generating an un-initialized flag associated with snan input data.
Claim 18
Claims 23, 33, and 35
A system comprising: a logic engine configured to receive a first input data and a second input data at a floating point arithmetic operating unit,
Claim 23: A system comprising: a logic engine configured to receive an input data for arithmetic operation to be operated on by a floating point arithmetic operating unit,
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively,
wherein the floating point arithmetic operating unit is configured to perform a floating point arithmetic operation on the first input data and the second input data,
determine whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
Claim 23: wherein the logic engine is configured to determine whether the received input data generates a floating point hardware exception responsive to the floating point arithmetic operation on the input data, wherein the determining occurs prior to performing the floating point arithmetic operation;
Claim 33: The system of claim 23, wherein the convertor engine is further configured to set a value of the input data to zero if the input data is a qnan (quiet not-a-number)
Claim 35: The system of claim 23, wherein the input data is an snan (signaling not-a-number) and wherein the modified value is zero.
and a convertor engine configured to convert a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan,
Claim 23: a convertor engine configured to convert a value of the received input data to a modified value responsive to the determining that the received input data generates the floating point hardware exception,
Claim 33: The system of claim 23, wherein the convertor engine is further configured to set a value of the input data to zero if the input data is a qnan (quiet not-a-number)
Claim 35: The system of claim 23, wherein the input data is an snan (signaling not-a-number) and wherein the modified value is zero.
Claim 19
Claim 24
The system of Claim 18 further comprising said arithmetic floating point operating unit configured to perform the floating point arithmetic operation on the first input data that has been modified and on the second input data to generate an output result.
The system of claim 23 further comprising an arithmetic floating point operator configured to perform the floating point arithmetic operation on the input data with modified value to generate an output result.
Claim 20
Claim 25
The system of Claim 18, wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation.
The system of claim 24, wherein the floating point arithmetic operation is selected from one of an addition operation, a subtraction operation, or an add-reduce operation.
Claim 21
Claim 26
The system of Claim 19, wherein the logic engine is configured to determine whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
The system of claim 24, wherein the logic engine is further configured to determine whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
Claim 22
Claim 27
The system of Claim 21, wherein the logic engine is configured to set a value of the output result to zero if a value of the output result is a denormal number.
The system of claim 26, wherein the convertor engine is further configured to set a value of the output result to zero if a value of the output result is a denormal number.
Claim 23
Claim 28
The system of Claim 21, wherein the logic engine is configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
The system of claim 26, wherein the convertor engine is further configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
and wherein the convertor engine is further configured to set a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim 24
Claim 33
The system of Claim 18, wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the qnan.
The system of claim 23, wherein the convertor engine is further configured to set a value of the input data to zero if the input data is a qnan (quiet not-a-number).
Claim 25
Claim 34
The system of Claim 24, wherein the logic engine is configured to generate an un- initialized flag associated with the first input data being qnan.
The system of claim 33, wherein the logic engine is further configured to generate an un-initialized flag associated with the input data.
Claim 26
Claim 35
The system of Claim 18, wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the snan.
The system of claim 23, wherein the input data is an snan (signaling not-a-number) and wherein the modified value is zero.
Claim 27
Claim 36
The system of Claim 26, wherein the logic engine is configured to generate an un- initialized flag associated with the input data being snan.
The system of claim 35, wherein the logic engine is configured to generate an un-initialized flag associated with the input data.
Claim 28
Claims 23, 33, and 35
A system comprising: a means for receiving a first input data and a second input data at a floating point arithmetic operating unit,
Claim 23: A system comprising: a logic engine configured to receive an input data for arithmetic operation to be operated on by a floating point arithmetic operating unit,
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively,
wherein the floating point arithmetic operating unit is configured to perform a floating point arithmetic operation on the first input data and the second input data;
a means for determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation;
Claim 23: wherein the logic engine is configured to determine whether the received input data generates a floating point hardware exception responsive to the floating point arithmetic operation on the input data, wherein the determining occurs prior to performing the floating point arithmetic operation;
Claim 33: The system of claim 23, wherein the convertor engine is further configured to set a value of the input data to zero if the input data is a qnan (quiet not-a-number)
Claim 35: The system of claim 23, wherein the input data is an snan (signaling not-a-number) and wherein the modified value is zero.
and a means for setting the first input data to zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation.
Claim 23: a convertor engine configured to convert a value of the received input data to a modified value responsive to the determining that the received input data generates the floating point hardware exception,
Claim 33: The system of claim 23, wherein the convertor engine is further configured to set a value of the input data to zero if the input data is a qnan (quiet not-a-number)
Claim 35: The system of claim 23, wherein the input data is an snan (signaling not-a-number) and wherein the modified value is zero.
Claim 29
Claim 24
The system of Claim 28 further comprising a means for performing the floating point arithmetic operation on the second input data and the first input data that has been modified to generate an output result.
The system of claim 23 further comprising an arithmetic floating point operator configured to perform the floating point arithmetic operation on the input data with modified value to generate an output result.
Claim 30
Claim 26
The system of Claim 29 further comprising a means for determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
The system of claim 24, wherein the logic engine is further configured to determine whether the output result of the floating point arithmetic operation generates a floating point hardware exception.
Claim 31
Claim 27
The system of Claim 30 further comprising a means for setting a value of the output result to zero if a value of the output result is a denormal number.
The system of claim 26, wherein the convertor engine is further configured to set a value of the output result to zero if a value of the output result is a denormal number.
Claim 32
Claim 28
The system of Claim 30 further comprising a means for setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
The system of claim 26, wherein the convertor engine is further configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity,
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
and wherein the convertor engine is further configured to set a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
Claim 33
Claims 34 and 26
The system of Claim 28 further comprising a means for generating an un-initialized flag associated with the first input data being the qnan or snan.
Claim 34: The system of claim 33, wherein the logic engine is further configured to generate an un-initialized flag associated with the input data.
Claim 36: The system of claim 35, wherein the logic engine is configured to generate an un-initialized flag associated with the input data.
As per claim 1, Patent ‘247 teaches the language as shown in the table above. However Patent ‘247 does not teach multiple inputs, wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, or wherein the floating point operating arithmetic unit is configured to perform the floating point arithmetic operation on the first input data and the second input data. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Patent ‘247 with the multiple inputs, the inputs being associated with floating point arithmetic operations, and performing arithmetic operations on the input data as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 4, Patent ‘247 does not teach determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception. Goddard teaches determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception (Goddard Col. 8 Lines 56-60: Depending on the floating point operation (e.g., add, multiply, divide, etc.) and the particular operand condition detected, arithmetic results may be forced by either FPDET 220 or FRND 250, thereby bypassing the normal flow through the arithmetic units; Goddard Tables 1-3: show determining if the output would be a qnan, snan, infinity, or an invalid operation).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Patent ‘247 with determining if the output would generate an exception as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would speed up the calculations as the system would know if the output would generate an exception and could terminate the calculations.
As per claim 11, Patent ‘247 teaches the language as shown in the table above. However Patent ‘247 does not teach multiple inputs, wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, or wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Patent ‘247 with the multiple inputs, the inputs being associated with floating point arithmetic operations, and performing arithmetic operations on the input data as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 14, Patent ‘247 does not teach determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception. Goddard teaches determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception (Goddard Col. 8 Lines 56-60: Depending on the floating point operation (e.g., add, multiply, divide, etc.) and the particular operand condition detected, arithmetic results may be forced by either FPDET 220 or FRND 250, thereby bypassing the normal flow through the arithmetic units; Goddard Tables 1-3: show determining if the output would be a qnan, snan, infinity, or an invalid operation).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Patent ‘247 with determining if the output would generate an exception as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would speed up the calculations as the system would know if the output would generate an exception and could terminate the calculations.
As per claim 18, Patent ‘247 teaches the language as shown in the table above. However Patent ‘247 does not teach multiple inputs, wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, or wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Patent ‘247 with the multiple inputs, the inputs being associated with floating point arithmetic operations, and performing arithmetic operations on the input data as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 19, Patent ‘247 teaches the language as shown in the table above. However the ‘682 application does not teach multiple inputs. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Patent ‘247 with the multiple inputs as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 28, Patent ‘247 teaches the language as shown in the table above. However Patent ‘247 does not teach multiple inputs, wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, or wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Patent ‘247 with the multiple inputs, the inputs being associated with floating point arithmetic operations, and performing arithmetic operations on the input data as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 29, Patent ‘247 teaches the language as shown in the table above. However the ‘682 application does not teach multiple inputs. Goddard teaches first and second data inputs (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Patent ‘247 with the multiple inputs as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would allow for more operation types to be performed that require multiple inputs, increasing flexibility.
As per claim 33, Patent ‘247 teaches the language as shown in the table above. However the ‘682 application does not teach associated with the first input data being the qnan or snan Goddard teaches associated with the first input data being the qnan or snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Patent ‘247 with the first input being a snan as taught by Goddard. One of ordinary skill in the art would be motivated to make this combination because it would signal to the system that the input is a snan, increasing efficiency as the system would be aware when performing the calculations.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim 28 recites “a means for receiving a first input data and a second input data”, “a means for determining whether the first input data is a”, and “a means for setting the first input data to zero”.
Claim 29 recites “a means for performing the floating point arithmetic operation”.
Claim 30 recites “a means for determining whether the output result”.
Claim 31 recites “a means for setting a value of the output result”.
Claim 32 recites “a means for setting a value of the output result to a”.
Claim 33 recites “a means for generating an un-initialized”.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a logic engine” and “a convertor engine” in claim 18.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18-33 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
With regards to claim 18, claim limitations “a logic engine” and “a convertor engine” invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. There is no corresponding structure, material, or acts in the specification to link to the function of the limitations. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
With regards to claim 28, claim limitations “a means for receiving a first input data and a second input data”, “a means for determining whether the first input data is a quiet not-a-number”, and “a means for setting the first input data to zero if the first input data” invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. There is no corresponding structure, material, or acts in the specification to link to the function of the limitations. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
With regards to claim 29, claim limitation “a means for performing the floating point arithmetic operation on the second input data and the first input data” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. There is no corresponding structure, material, or acts in the specification to link to the function of the limitations. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
With regards to claim 30, claim limitation “a means for determining whether the output result of the floating point arithmetic operation generates a” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. There is no corresponding structure, material, or acts in the specification to link to the function of the limitations. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
With regards to claim 31, claim limitation “a means for setting a value of the output result to zero if a value” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. There is no corresponding structure, material, or acts in the specification to link to the function of the limitations. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
With regards to claim 32, claim limitation “a means for setting a value of the output result to a maximum supported number if” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. There is no corresponding structure, material, or acts in the specification to link to the function of the limitations. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
With regards to claim 33, claim limitation “a means for generating an un-initialized flag” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. There is no corresponding structure, material, or acts in the specification to link to the function of the limitations. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-33 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more.
With regards to claim 1, at step 1, the claim is directed to a method, which is a statutory category of invention.
At Step 2A Prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical concepts. The claim language has been reproduced below:
A computer-implemented method comprising: (mental process, evaluation)
receiving a first input data and a second input data at a floating point arithmetic operating unit, (mental process, evaluation) wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, (mental process, evaluation) wherein the floating point arithmetic operating unit is configured to (mental process, evaluation) perform the floating point arithmetic operation on the first input data and the second input data; (mathematical calculation)
determining whether the first input data is a quiet not-a-number (qnan) (mental process, evaluation) or whether the first input data is a signaling not-a-number (snan) (mental process, evaluation) prior to performing the floating point arithmetic operation; (mental process, evaluation) and
converting a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan, (mathematical calculation) wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the first input data is either the qnan or the snan. (mental process, evaluation)
Each of the non-bolded limitations are mental processes and/or mathematical calculations. The “A computer-implemented method comprising” limitation is an evaluation mental process that can be performed by choosing what the method comprises. The “a first input data and a second input data at a” is an evaluation mental process that can be performed by choosing where the input data goes. The “wherein the first input data and the second input data are associated” limitation is an evaluation mental process that can be performed by choosing what the input data is associated with. The “the floating point arithmetic operating unit is configured to” limitation is an evaluation mental process that can be performed by choosing what the floating point operating unit is configured to do. The “perform the floating point arithmetic operation” is a mathematical calculation that can be performed by performing the arithmetic operation by hand using pen and paper. The “determining whether the first input data is a quiet not-a-number” limitation is an evaluation mental process that can be performed by determining if the input is a qnan by hand using pen and paper. The “whether the first input data is a signaling not-a-number (snan)” limitation is an evaluation mental process that can be performed by determining if the input is a snan by hand using pen and paper. The “prior to performing the floating point arithmetic” limitation is an evaluation mental process that can be performed by choosing when the determination happens. The “converting a value of the first input data to a” limitation is a mathematical calculation that can be performed by converting the input by hand using pen and paper. The “wherein the converting eliminates” limitation is an evaluation mental process that can be performed by choosing what the conversion does.
At step 2A Prong 2, the additional elements are bolded above. The “receiving” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘receiving’ in the context of the claim encompasses mere data gathering for the claimed arithmetic step. The remaining additional elements amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
Under Step 2B, the claim recites “receiving a first input data and a second input data at a” and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well- understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 11, it recites similar language to claim 1 and is rejected for, at least, the same reasons therein. Herein claim 11 is directed towards the statutory category of a method, thus also satisfying step 1. Moreover, under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 18, it recites similar language to claim 1 and is rejected for, at least, the same reasons therein. Herein claim 18 is directed towards the statutory category of a machine, thus also satisfying step 1. Moreover under step 2A prong 2 the additional elements are “a system”, “a logic engine”, and “a convertor engine”. These are no more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claims do not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 28, it recites similar language to claim 1 and is rejected for, at least, the same reasons therein. Herein claim 18 is directed towards the statutory category of a machine, thus also satisfying step 1. Moreover under step 2A prong 2 the additional elements are “a system”, “a means for receiving”, “a means for determining”, and “a means for setting”. These are no more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claims do not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 2, 12, 19, and 29, they are directed to mental processes and/or mathematical concepts. The “performing the floating point arithmetic operation on the second input data and the first input data” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing what the operands are for the arithmetic operation and then performing the arithmetic operation by hand using pen and paper. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 3, 13, and 20, they are directed to mental processes and/or mathematical concepts. The “wherein the floating point arithmetic operation is selected from one of” limitation is an evaluation mental process that can be performed by choosing what arithmetic operation to perform. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 4, 14, 21, and 30, they are directed to mental processes and/or mathematical concepts. The “determining whether the output result” limitation is an evaluation mental process that can be performed by looking at the result and determining it. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 5, 15, 22, and 31, they are directed to mental processes and/or mathematical concepts. The “setting a value of the output result to zero” limitation is an evaluation mental process and mathematical calculation that can be performed by setting the output to zero by hand using pen and paper. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 6, 16, 23, and 32, they are directed to mental processes and/or mathematical concepts. The “setting a value of the output result to a maximum” limitation is an evaluation mental process and mathematical calculation that can be performed by setting the output to a maximum if it is infinity by hand using pen and paper. The “setting a value of the output result to a minimum” limitation is an evaluation mental process and mathematical calculation that can be performed by setting the output to a minimum if it is negative infinity by hand using pen and paper. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 7 and 24, they are directed to mental processes and/or mathematical concepts. The “wherein the converting of the value of the first input data” limitation is an evaluation mental process and mathematical calculation that can be performed by setting the input to zero if it is a qnan by hand using pen and paper. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 8 and 25, they are directed to mental processes and/or mathematical concepts. The “generating an un-initialized flag” limitation is an evaluation mental process that can be performed by setting the flag if one sees that the input is a qnan. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 9 and 26, they are directed to mental processes and/or mathematical concepts. The “wherein the converting of the value of the first input data” limitation is an evaluation mental process and mathematical calculation that can be performed by setting the input to zero if it is an snan by hand using pen and paper. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 10 and 27, they are directed to mental processes and/or mathematical concepts. The “generating an un-initialized flag” limitation is an evaluation mental process that can be performed by setting the flag if one sees that the input is an snan. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 17 and 33, they are directed to mental processes and/or mathematical concepts. The “generating an un-initialized flag associated” limitation is an evaluation mental process that can be performed by setting the flag if one sees that the input is a qnan or snan. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7, 9, 11-14, 18-21, 24, 26, and 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard et al. (US 5748516 A) hereinafter Goddard in view of Harada et al. (US 20070257824 A1) hereinafter Harada.
With regards to claim 1 Goddard teaches A computer-implemented method comprising: receiving a first input data and a second input data at a floating point arithmetic operating unit, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: table 3 shows that qnan and snan numbers can be detected).
Goddard fails to teach and converting a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan, and wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the first input data is either the qnan or the snan.
However, Harada does teach and converting a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan, (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i))
wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the first input data is either the qnan or the snan (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with the converting of nans as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 2, Goddard in view of Harada teaches all of the limitations of claim 1 above. Goddards further teaches performing the floating point arithmetic operation on the second input data and the first input data [that has been modified] to generate an output result (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283).
Goddard fails to teach [the first input data] that has been modified.
However, Harada does teach [the first input data] that has been modified (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with the modified first input data as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 3, Goddard in view of Harada teaches all of the limitations of claim 1 above. Goddards further teaches wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283; Goddard Tables 1-3: show multiplication, division, addition, and subtraction can be performed).
With regards to claim 4, Goddard in view of Harada teaches all of the limitations of claim 2 above. Goddards further teaches determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception (Goddard Col. 8 Lines 56-60: Depending on the floating point operation (e.g., add, multiply, divide, etc.) and the particular operand condition detected, arithmetic results may be forced by either FPDET 220 or FRND 250, thereby bypassing the normal flow through the arithmetic units; Goddard Tables 1-3: show determining if the output would be a qnan, snan, infinity, or an invalid operation).
With regards to claim 7, Goddard in view of Harada teaches all of the limitations of claim 1 above. Goddards further teaches [wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the] qnan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the [qnan].
However, Harada does teach wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the [qnan] (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with setting the input to zero if it is a nan as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 9, Goddard in view of Harada teaches all of the limitations of claim 1 above. Goddards further teaches [wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the] snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the [snan].
However, Harada does teach wherein the converting of the value of the first input data to the modified value is setting the value of the first input data to zero if the first input data is the [snan] (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with setting the input to zero if it is a nan as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 11, Goddard teaches A computer-implemented method comprising: receiving a first input data and a second input data at a floating point arithmetic operating unit, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: table 3 shows that qnan and snan numbers can be detected).
Goddard fails to teach and setting the first input data to zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation.
However, Harada does teach and setting the first input data to zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with the converting of nans as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 12, Goddard in view of Harada teaches all of the limitations of claim 11 above. Goddards further teaches performing the floating point arithmetic operation on the second input data and the first input data [that has been modified] to generate an output result (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283).
Goddard fails to teach [the first input data] that has been modified.
However, Harada does teach [the first input data] that has been modified (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with the modified first input data as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 13, Goddard in view of Harada teaches all of the limitations of claim 11 above. Goddards further teaches wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283; Goddard Tables 1-3: show multiplication, division, addition, and subtraction can be performed).
With regards to claim 14, Goddard in view of Harada teaches all of the limitations of claim 12 above. Goddards further teaches determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception (Goddard Col. 8 Lines 56-60: Depending on the floating point operation (e.g., add, multiply, divide, etc.) and the particular operand condition detected, arithmetic results may be forced by either FPDET 220 or FRND 250, thereby bypassing the normal flow through the arithmetic units; Goddard Tables 1-3: show determining if the output would be a qnan, snan, infinity, or an invalid operation).
With regards to claim 18 Goddard teaches A system comprising: a logic engine configured to receive a first input data and a second input data at a floating point arithmetic operating unit, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
determine whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: table 3 shows that qnan and snan numbers can be detected).
Goddard fails to teach and a convertor engine configured to convert a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan, and wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the first input data is either the qnan or the snan.
However, Harada does teach and a convertor engine configured to convert a value of the first input data to a modified value prior to performing the floating point arithmetic operation if the first input data is either the qnan or the snan, (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i))
wherein the converting eliminates special handling on the input data by the floating point arithmetic operating unit when the first input data is either the qnan or the snan (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with the converting of nans as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 19, Goddard in view of Harada teaches all of the limitations of claim 18 above. Goddards further teaches said arithmetic floating point operating unit configured to perform the floating point arithmetic operation on the first input data [that has been modified] and on the second input data to generate an output result (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283).
Goddard fails to teach [the first input data] that has been modified.
However, Harada does teach [the first input data] that has been modified (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with the modified first input data as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 20, Goddard in view of Harada teaches all of the limitations of claim 18 above. Goddards further teaches wherein the floating point arithmetic operation is selected from one of addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, a max-reduce operation, a min-reduce operation, a multiplication operation, or a division operation (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283; Goddard Tables 1-3: show multiplication, division, addition, and subtraction can be performed).
With regards to claim 21, Goddard in view of Harada teaches all of the limitations of claim 19 above. Goddards further teaches wherein the logic engine is configured to determine whether the output result of the floating point arithmetic operation generates a floating point hardware exception (Goddard Col. 8 Lines 56-60: Depending on the floating point operation (e.g., add, multiply, divide, etc.) and the particular operand condition detected, arithmetic results may be forced by either FPDET 220 or FRND 250, thereby bypassing the normal flow through the arithmetic units; Goddard Tables 1-3: show determining if the output would be a qnan, snan, infinity, or an invalid operation).
With regards to claim 24, Goddard in view of Harada teaches all of the limitations of claim 18 above. Goddards further teaches [wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the] qnan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the [qnan].
However, Harada does teach wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the [qnan] (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with setting the input to zero if it is a nan as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 26, Goddard in view of Harada teaches all of the limitations of claim 18 above. Goddards further teaches [wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the] snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the [snan].
However, Harada does teach wherein the convertor engine is configured to set a value of the first input data to zero if the first input data is the [snan] (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with setting the input to zero if it is a nan as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 28 Goddard teaches A system comprising: a means for receiving a first input data and a second input data at a floating point arithmetic operating unit, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the first input data and the second input data are associated with operands of a floating point arithmetic operation respectively, (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
wherein the floating point arithmetic operating unit is configured to perform the floating point arithmetic operation on the first input data and the second input data; (Goddard Col. 5 Lines 50-57: FIG. 2 depicts a floating point arithmetic unit, FPU 200, for a superscalar processor. The FPU 200 includes a reservation station, FRES 210; control logic, FCNTL 262; a predetect unit, FPDET 220; two arithmetic units (an addition pipeline, FADD 230 and a multiplication pipeline, FMUL 241); and a rounding unit, FRND 250. Additionally, FPU 200 includes three internal busses (an internal A operand bus 272, an internal B operand bus 274, and a rounding bus 276))
a means for determining whether the first input data is a quiet not-a-number (qnan) or whether the first input data is a signaling not-a-number (snan) prior to performing the floating point arithmetic operation; (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: table 3 shows that qnan and snan numbers can be detected).
Goddard fails to teach and a means for setting the first input data to zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation.
However, Harada does teach and a means for setting the first input data to zero if the first input data is the qnan or the snan, wherein the setting occurs prior to performing the floating point arithmetic operation (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with the converting of nans as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 29, Goddard in view of Harada teaches all of the limitations of claim 28 above. Goddards further teaches a means for performing the floating point arithmetic operation on the second input data and the first input data [that has been modified] to generate an output result (Goddard Col. 7 Lines 32-43: First, the requisite floating point arithmetic unit must be available, and second, A and B operands must both be ready (i.e., operand tag references, if any, must be resolved). Each of the floating point arithmetic units (FADD 230 and FMUL 241) receives its operands from busses 272 and 274 and calculates a result which the unit drives onto round bus 276. A rounding unit, FRND 250, receives these results from round bus 276 and rounds the result in accordance with any of the four rounding modes specified by ANSI IEEE standard 754. FRND 250 drives a rounded floating point result back to FRES 210, which in turn drives it onto the result bus 283).
Goddard fails to teach [the first input data] that has been modified.
However, Harada does teach [the first input data] that has been modified (Harada [0153]: If a determining section 41a of the input determining section 41 determines that x(i)=NaN, a switch 41b is controlled to cause a 0 source 41c to output 0 in stead of x(i)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard with the modified first input data as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the calculation would not be stopped if an operand is not a number.
With regards to claim 30, Goddard in view of Harada teaches all of the limitations of claim 29 above. Goddards further teaches a means for determining whether the output result of the floating point arithmetic operation generates a floating point hardware exception (Goddard Col. 8 Lines 56-60: Depending on the floating point operation (e.g., add, multiply, divide, etc.) and the particular operand condition detected, arithmetic results may be forced by either FPDET 220 or FRND 250, thereby bypassing the normal flow through the arithmetic units; Goddard Tables 1-3: show determining if the output would be a qnan, snan, infinity, or an invalid operation).
Claims 5, 15, 22, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard in view of Harada further in view of Valentine et al. (US 20190163474 A1) hereinafter Valentine.
With regards to claim 5, Goddard in view of Harada teaches all of the limitations of claim 4 above. Goddard fails to teach setting a value of the output result to zero if a value of the output result is a denormal number.
However, Valentine does teach setting a value of the output result to zero if a value of the output result is a denormal number (Valentine [0182]: Bit 19, FZ16, when set, indicates that output FP16 denormal element results are flushed to zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with setting the output to zero as taught by Valentine. One of ordinary skill in the art would be motivated to make this combination because the denormals-are-zeros FP16 mode improves processor performance as taught by Valentine (Valentine [0181]).
With regards to claim 15, Goddard in view of Harada teaches all of the limitations of claim 14 above. Goddard fails to teach setting a value of the output result to zero if a value of the output result is a denormal number.
However, Valentine does teach setting a value of the output result to zero if a value of the output result is a denormal number (Valentine [0182]: Bit 19, FZ16, when set, indicates that output FP16 denormal element results are flushed to zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with setting the output to zero as taught by Valentine. One of ordinary skill in the art would be motivated to make this combination because the denormals-are-zeros FP16 mode improves processor performance as taught by Valentine (Valentine [0181]).
With regards to claim 22, Goddard in view of Harada teaches all of the limitations of claim 21 above. Goddard fails to teach wherein the logic engine is configured to set a value of the output result to zero if a value of the output result is a denormal number.
However, Valentine does teach wherein the logic engine is configured to set a value of the output result to zero if a value of the output result is a denormal number (Valentine [0182]: Bit 19, FZ16, when set, indicates that output FP16 denormal element results are flushed to zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with setting the output to zero as taught by Valentine. One of ordinary skill in the art would be motivated to make this combination because the denormals-are-zeros FP16 mode improves processor performance as taught by Valentine (Valentine [0181]).
With regards to claim 31, Goddard in view of Harada teaches all of the limitations of claim 30 above. Goddard fails to teach a means for setting a value of the output result to zero if a value of the output result is a denormal number.
However, Valentine does teach a means for setting a value of the output result to zero if a value of the output result is a denormal number (Valentine [0182]: Bit 19, FZ16, when set, indicates that output FP16 denormal element results are flushed to zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with setting the output to zero as taught by Valentine. One of ordinary skill in the art would be motivated to make this combination because the denormals-are-zeros FP16 mode improves processor performance as taught by Valentine (Valentine [0181]).
Claims 6, 16, 23, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard in view of Harada further in view of Wilkins et al. (US 20140195581 A1) hereinafter Wilkins.
With regards to claim 6, Goddard in view of Harada teaches all of the limitations of claim 4 above. Goddard fails to teach setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
However, Wilkins does teach setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero)
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with setting the output to its maximum or minimum value as taught by Wilkins. One of ordinary skill in the art would be motivated to make this combination because this would speed up calculations as there would not have to be any special handling of the infinity or minus infinity.
With regards to claim 16, Goddard in view of Harada teaches all of the limitations of claim 14 above. Goddard fails to teach setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
However, Wilkins does teach setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero)
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with setting the output to its maximum or minimum value as taught by Wilkins. One of ordinary skill in the art would be motivated to make this combination because this would speed up calculations as there would not have to be any special handling of the infinity or minus infinity.
With regards to claim 23, Goddard in view of Harada teaches all of the limitations of claim 21 above. Goddard fails to teach wherein the logic engine is configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
However, Wilkins does teach wherein the logic engine is configured to set a value of the output result to a maximum supported number if a value of the output result is a positive infinity, (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero)
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with setting the output to its maximum or minimum value as taught by Wilkins. One of ordinary skill in the art would be motivated to make this combination because this would speed up calculations as there would not have to be any special handling of the infinity or minus infinity.
With regards to claim 32, Goddard in view of Harada teaches all of the limitations of claim 30 above. Goddard fails to teach a means for setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity.
However, Wilkins does teach a means for setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero)
and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity (Wilkins [0051]: In the case of a division by zero, the result may be a saturated output quotient of plus or minus a maximum numerical value, with a remainder of zero).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with setting the output to its maximum or minimum value as taught by Wilkins. One of ordinary skill in the art would be motivated to make this combination because this would speed up calculations as there would not have to be any special handling of the infinity or minus infinity.
Claims 8, 10, 17, 25, 27, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Goddard in view of Harada further in view of Vorbach et al. (US 20190377580 A1) hereinafter Vorbach.
With regards to claim 8, Goddard in view of Harada teaches all of the limitations of claim 7 above. Goddard further teaches [generating an un-initialized flag associated with the first input data being the] qnan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach generating an un-initialized flag associated with the first input data being the [qnan].
However, Vorbach does teach generating an un-initialized flag associated with the first input data being the [qnan] (Vorbach [0383]: Floating point ALUs may additionally produce floating point specific flags such as NaN (not a number)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with generating the flag as taught by Vorbach. One of ordinary skill in the art would be motivated to make this combination because such information can be for instance flags… This is useful in particular for branching as taught by Vorbach (Vorbach [0180]-[0181]). Also, flags would make calculations easier as the FPU would know what type of input an operand is.
With regards to claim 10, Goddard in view of Harada teaches all of the limitations of claim 9 above. Goddard further teaches [generating an un-initialized flag associated with the first input data being the] snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach generating an un-initialized flag associated with the first input data being the [snan].
However, Vorbach does teach generating an un-initialized flag associated with the first input data being the [snan] (Vorbach [0383]: Floating point ALUs may additionally produce floating point specific flags such as NaN (not a number)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with generating the flag as taught by Vorbach. One of ordinary skill in the art would be motivated to make this combination because such information can be for instance flags… This is useful in particular for branching as taught by Vorbach (Vorbach [0180]-[0181]). Also, flags would make calculations easier as the FPU would know what type of input an operand is.
With regards to claim 17, Goddard in view of Harada teaches all of the limitations of claim 11 above. Goddard further teaches [generating an un-initialized flag associated with the first input data being the] qnan or snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach generating an un-initialized flag associated with the first input data being the [qnan or snan].
However, Vorbach does teach generating an un-initialized flag associated with the first input data being the [qnan or snan] (Vorbach [0383]: Floating point ALUs may additionally produce floating point specific flags such as NaN (not a number)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with generating the flag as taught by Vorbach. One of ordinary skill in the art would be motivated to make this combination because such information can be for instance flags… This is useful in particular for branching as taught by Vorbach (Vorbach [0180]-[0181]). Also, flags would make calculations easier as the FPU would know what type of input an operand is.
With regards to claim 25, Goddard in view of Harada teaches all of the limitations of claim 24 above. Goddard further teaches [wherein the logic engine is configured to generate an un- initialized flag associated with the first input data being] qnan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach wherein the logic engine is configured to generate an un- initialized flag associated with the first input data being [qnan].
However, Vorbach does teach wherein the logic engine is configured to generate an un- initialized flag associated with the first input data being [qnan] (Vorbach [0383]: Floating point ALUs may additionally produce floating point specific flags such as NaN (not a number)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with generating the flag as taught by Vorbach. One of ordinary skill in the art would be motivated to make this combination because such information can be for instance flags… This is useful in particular for branching as taught by Vorbach (Vorbach [0180]-[0181]). Also, flags would make calculations easier as the FPU would know what type of input an operand is.
With regards to claim 27, Goddard in view of Harada teaches all of the limitations of claim 26 above. Goddard further teaches [wherein the logic engine is configured to generate an un- initialized flag associated with the first input data being] snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach wherein the logic engine is configured to generate an un- initialized flag associated with the first input data being [snan].
However, Vorbach does teach wherein the logic engine is configured to generate an un- initialized flag associated with the first input data being [snan] (Vorbach [0383]: Floating point ALUs may additionally produce floating point specific flags such as NaN (not a number)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with generating the flag as taught by Vorbach. One of ordinary skill in the art would be motivated to make this combination because such information can be for instance flags… This is useful in particular for branching as taught by Vorbach (Vorbach [0180]-[0181]). Also, flags would make calculations easier as the FPU would know what type of input an operand is.
With regards to claim 33, Goddard in view of Harada teaches all of the limitations of claim 28 above. Goddard further teaches [a means for generating an un-initialized flag associated with the first input data being the] qnan or snan (Goddard Col. 8 Lines 52-54: In the embodiment disclosed in FIG. 2, operand conditions detected by FPDET 220, such as zero operands, infinity operands, and not a number (NaN) operands; Goddard Table 3: shows that qnan and snan numbers can be detected).
Goddard fails to teach a means for generating an un-initialized flag associated with the first input data being the [qnan or snan].
However, Vorbach does teach a means for generating an un-initialized flag associated with the first input data being the [qnan or snan] (Vorbach [0383]: Floating point ALUs may additionally produce floating point specific flags such as NaN (not a number)).
Therefore, it would have been obvious before the effective filing date of the claimed invention
for one of ordinary skill in the art to combine the teachings of Goddard in view of Harada with generating the flag as taught by Vorbach. One of ordinary skill in the art would be motivated to make this combination because such information can be for instance flags… This is useful in particular for branching as taught by Vorbach (Vorbach [0180]-[0181]). Also, flags would make calculations easier as the FPU would know what type of input an operand is.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jakob O Gudas whose telephone number is (571)272-0695. The examiner can normally be reached Monday-Thursday: 7:30AM-5:00PM Friday: 7:30AM-4:00PM.
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/J.O.G./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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