DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is FINAL and is in response to the response filed June 23rd, 2026. Claims 1-38 are pending, of which claims 1-38 are currently rejected.
Response to Arguments
The amendment filed June 23rd, 2026 has been entered. Claims 1-38 remain pending in the application.
Prior Art Rejections
Applicant’s arguments regarding the previously cited art have been fully considered and are not persuasive.
Applicant alleges that Lutz et al. (US 2020/0257499 A1) (hereinafter “Lutz”) does not teach the limitation “modified value differs based on whether the received input data is positive infinity or negative infinity” because Lutz does not teach using this table or that the table does not show any rounding to negative or positive infinity (Applicant Remarks: Pg. 9).
Examiner respectfully disagrees. Even if Lutz does not explicitly teach using Table 4 (found in ¶ 0113 of Lutz), Lutz does disclose Table 4 with this rounding as displayed in rows for modes RP and RN that discuss the selection of the closest value to minus infinity or plus infinity in order to avoid overflow or underflow. The fact that Table 4 is disclosed clearly shows that before the effective filing date of the claimed invention, there is disclosure for this limitation and therefore it is not inventive (and therethrough allowable). Applicant’s further alleging that because Lutz itself does not use this rounding table, combining Hinds et al. (6701427) (hereinafter “Hinds”) and Zbiciak et al. (US 2023/0042884 A1) (hereinafter “Zbiciak”) with Lutz does not teach this limitation. However, Lutz does in fact disclose this table having the rounding modes corresponding with the modified value differing based on whether the received input data is positive or negative infinity as there are two different modes to yield different outputs based on what the modified value being either positive (plus) or negative (minus) infinity.
Therefore, Hinds in view of Zbiciak in view of Lutz does in fact teach “wherein the modified value differs based on whether the received input data is positive infinity or negative infinity”.
See Claim Rejections - 35 USC § 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-7, 10, 12, 14-17, 19-20, 23, 25, 27-30, 32, 35 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Hinds et al. (6701427) (hereinafter “Hinds”), further in view of Zbiciak et al. (US 2023/0042884 A1) (hereinafter “Zbiciak”), further in view of Lutz et al. (US 2020/0257499 A1) (hereinafter “Lutz”).
Regarding claim 1, Hinds teaches a method for receiving input data for a floating point operation (Hinds: Abstract Lines 1-7 data processing apparatus that takes as inputs floating point operands to apply a floating point operation; Col. 17 Lines 60-62 floating point arithmetic operation carried out through floating point unit), determining whether the input data’s value would cause a floating point hardware exception responsive to the floating point arithmetic operation on the input data (Hinds: Col. 12 Lines 34-44 detection logic determines if inputs may cause a floating point hardware exception; Col. 12 Lines 22-28 special operand determination; Fig. 3 Element 800 detection logic circuit), and converting the values of the input data to a modified value, the modified value being used for the floating point arithmetic operation (Hinds: Fig. 3 Element 1000 qualifier circuit; Col. 3 Lines 8-13 exception determination logic determines if exception may occur using operands before exception is made before floating point operation and once conversion occurs of values operation is made with those converted values).
Although Hinds teaches determining different kinds of inputs that may cause a floating point hardware exception (Hinds: Col. 12 Lines 22-28), Hinds does not explicitly teach determining whether the input is specifically a positive or negative infinity value.
However, Zbiciak teaches determining specifically if the input is denormal, infinity, qnan or snan values (Zbiciak: ¶ 0096; ¶ 0022; Claims 2 and 14).
It would be obvious before the effective filing date of the claimed invention to combine the specific determination of infinity values as taught by Zbiciak with the receiving, determining, and converting as taught by Hinds as all teachings are directed towards floating point computation. Zbiciak enhances the apparatus of Hinds by accounting for the many different forms of floating point values (Zbiciak: ¶ 0096).
Hinds in view of Zbiciak does not explicitly teach:
wherein the modified value differs based on whether the received input data is positive infinity or negative infinity.
However, Lutz teaches:
wherein the modified value differs based on whether the received input data is positive infinity or negative infinity (Lutz: ¶ 0113 setting the value at different values based on if the input is negative infinity or positive infinity; Table 4).
It would be obvious before the effective filing date of the claimed invention to combine the modified value conversion based if the value is positive or negative infinity as taught by Lutz with the receiving and determining as taught by Hinds in view of Zbiciak as all teachings are directed towards the handling of computation when special operands are received and avoiding hardware exceptions. One with ordinary skill in the art would be motivated to combine the teachings because this would avoid overflow or underflow when dealing with infinity operands (Lutz: ¶ 0113).
Hinds in view of Zbiciak in view of Lutz therefore teaches:
A computer-implemented method comprising:
receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data;
determining whether the received input data is positive infinity or negative infinity prior to performing the floating point arithmetic operation; and
converting a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is positive infinity or negative infinity, wherein the modified value differs based on whether the received input data is positive infinity or negative infinity.
Regarding claim 2, Hinds in view of Zbiciak in view of Lutz further teaches:
The method of Claim 1 further comprising performing the floating point arithmetic operation on the input data with the modified value to generate an output result (Hinds: Col. 2 Lines 66-67 and Col. 3 Lines 1-24 final result is obtained using the converted value as derived from the exception determination logic).
Regarding claim 3, Hinds in view of Zbiciak in view of Lutz further teaches:
The method of Claim 2 further comprising determining whether the output result of the floating point arithmetic operation causes a floating point hardware exception (Hinds: Col. 12 Lines 28-33 explains that the result of floating point operations also undergoes the determination logic once more in order to ensure the result does not cause a floating point hardware exception).
Regarding claim 4, Hinds in view of Zbiciak in view of Lutz further teaches:
The method of Claim 2 further comprising setting a value of the output result to zero if the value of the output result is a denormal number (Hinds: Hinds: Col. 14 Lines 20-29 if operand is denormal, operand is treated as zero i.e., converted/flushed to 0 and the IsZero signal is activated; Col. 14 Lines 53-55 describe that if the IsZero signal is activated the output will be selected to be 0).
Regarding claim 6, Hinds in view of Zbiciak in view of Lutz further teaches:
The method of Claim 1, wherein the floating point arithmetic operation is selected from one of an addition operation, a subtraction operation, an add-reduce operation, a maximum operation, a minimum operation, an addition operation, a subtraction operation, a multiplication operation, a divisional operation, a max-reduce operation, a min-reduced operation, a negate operation, converting a first floating point to a second floating point if the input data is greater than a number and converting a third floating point to a fourth floating point if the input data is less than the number, or a floating point to integer operation (Hinds: Col. 4 Lines 6-18 conversion to different floating point based on threshold signals; Col. 4 Lines 24-28 conversion between data types).
Regarding claim 7, Hinds in view of Zbiciak in view of Lutz further teaches:
The method of Claim 1 further comprising setting the value of the input data to zero if the input data is a denormal number (Hinds: Col. 14 Lines 20-38 detection logic that detects if any of the operands may cause an exception i.e., operands that may be denormal, NaN, infinity, or 0 and setting to 0 through the IsZero signal).
Regarding claim 10, Hinds teaches detection logic that detects if any of the operands may cause an exception (i.e., if the operand is denormal, a NaN, infinity, or 0). In the case that any of the operands may cause an exception, the operand is to be treated as zero flushed i.e., set to 0 through the IsZero signal (Hinds: Col. 14 Lines 20-38). While Hinds does teach the possibility of operands being a nan (Hinds: Col. 12 Lines 22-28), Hinds does not explicitly teach the operand inputs being qnan. However, Zbiciak teaches the possibility of the input operands being qnan (Zbiciak: ¶ 0096; Claims 2 and 14) which would therefore be set as a 0 operand through the detection logic of Hinds.
It would be obvious before the effective filing date of the claimed invention to combine the qnan value as taught by Zbiciak with the setting to 0 of exception-causing operands as taught by Hinds as both teachings are directed towards floating point computations. The improvement of Zbiciak lies in accounting for the many different forms of floating point values (Zbiciak: ¶ 0096).
Hinds in view of Zbiciak in view of Lutz therefore teaches:
The method of Claim 1 further comprising setting the value of the input data to zero if the input data is a quiet not-a-number (qnan).
Regarding claim 12, Hinds teaches detection logic that detects if any of the operands may cause an exception (i.e., if the operand is denormal, a NaN, infinity, or 0). In the case that any of the operands may cause an exception, the operand is to be treated as zero flushed i.e., set to 0 through the IsZero signal (Hinds: Col. 14 Lines 20-38). While Hinds does teach the possibility of operands being a nan (Hinds: Col. 12 Lines 22-28), Hinds does not explicitly teach the operand inputs being snan. However, Zbiciak teaches the possibility of the input operands being snan (Zbiciak: ¶ 0096; Claims 2 and 14) which would therefore be set as a 0 operand through the detection logic of Hinds.
The motivation to combine provided with respect to claim 10 applies equally to claim 12.
Hinds in view of Zbiciak in view of Lutz therefore teaches:
The method of Claim 1, wherein the input data is a signaling not-a-number (snan) and wherein the modified value is zero.
Regarding claim 14, Hinds in view of Zbiciak in view of Lutz further teaches a logic engine for receiving input data for a floating point operation (Hinds: Abstract Lines 1-7 data processing apparatus that takes as inputs floating point operands to apply a floating point operation via Fig. 3 Element 800 detection logic i.e., logic engine) at floating point unit (Hinds: Col. 17 Lines 60-62 floating point arithmetic operation carried out through floating point unit), determining at a logic engine whether the input data’s value would cause a floating point hardware exception responsive to the floating point arithmetic operation on the input data (Hinds: Col. 12 Lines 34-44 detection logic i.e. logic engine determines if inputs may cause a floating point hardware exception; Col. 12 Lines 22-28 special operand determination; Fig. 3 Element 800 detection logic circuit i.e., detection logic circuit), and converting at a convertor engine the values of the input data to a modified value, the modified value being used for the floating point arithmetic operation (Hinds: Fig. 3 Element 1000 qualifier circuit; Col. 3 Lines 8-13 exception determination logic determines if exception may occur using operands before exception is made before floating point operation and once conversion occurs of values operation is made with those converted values).
Although Hinds teaches determining different kinds of inputs that may cause a floating point hardware exception (Hinds: Col. 12 Lines 22-28), Hinds does not explicitly teach determining whether the input is specifically a positive or negative infinity.
However, Zbiciak teaches determining specifically if the input is denormal, infinity, qnan or snan values (Zbiciak: ¶ 0096; Claims 2 and 14).
The motivation to combine provided with respect to claim 1 applies equally to claim 18.
Hinds in view of Zbiciak does not explicitly teach:
wherein the modified value differs based on whether the received input data is positive infinity or negative infinity.
However, Lutz teaches:
wherein the modified value differs based on whether the received input data is positive infinity or negative infinity (Lutz: ¶ 0113 setting the value at different values based on if the input is negative infinity or positive infinity; Table 4).
The motivation to combine with respect to claim 1 applies equally to claim 14.
Hinds in view of Zbiciak in view of Lutz therefore teaches:
A system comprising:
a logic engine configured to
receive an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data,
determine whether the received input data is positive infinity or negative infinity prior to performing the floating point arithmetic operation; and
a convertor engine configured to convert a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is positive infinity or negative infinity, wherein the modified value differs based on whether the received input data is positive infinity or negative infinity.
Claims 15-17 and 19 teach the system that practices the method of claims 2-4 and 6, respectively, and are therefore rejected for the same reasons therein.
Claim 20 teaches the system that practices the method of claim 7 and is therefore rejected for the same reasons therein.
Regarding claim 23, Hinds teaches a detection logic circuit (Hinds: Fig. 3 800 i.e., logic engine) that detects if any of the operands may cause an exception (i.e., if the operand is denormal, a NaN, infinity, or 0). In the case that any of the operands may cause an exception, the operand is to be treated as zero flushed i.e., set to 0 through the IsZero signal (Hinds: Col. 14 Lines 20-38). While Hinds does teach the possibility of operands being a nan (Hinds: Col. 12 Lines 22-28), Hinds does not explicitly teach the operand inputs being qnan. However, Zbiciak teaches the possibility of the input operands being qnan (Zbiciak: ¶ 0096; Claims 2 and 14) which would therefore be set as a 0 operand through the qualifier circuit (i.e., convertor engine, Fig. 3 1000) of Hinds after the determination of the operand carried out by the detection logic circuit (i.e., logic engine, Fig. 3 800).
It would be obvious before the effective filing date of the claimed invention to combine the qnan value as taught by Zbiciak with the setting to 0 of exception-causing operands as taught by Hinds as both teachings are directed towards floating point computations. The improvement of Zbiciak lies in accounting for the many different forms of floating point values (Zbiciak: ¶ 0096).
Hinds in view of Zbiciak in view of Lutz therefore teaches:
The system of Claim 14, wherein the convertor engine is further configured to set the value of the input data to zero if the input data is a quiet not-a-number (qnan).
Regarding claim 25, Hinds teaches a detection logic circuit that detects if any of the operands may cause an exception (i.e., if the operand is denormal, a NaN, infinity, or 0). In the case that any of the operands may cause an exception, the operand is to be treated as zero flushed i.e., set to 0 through the IsZero signal (Hinds: Col. 14 Lines 20-38). While Hinds does teach the possibility of operands being a nan (Hinds: Col. 12 Lines 22-28), Hinds does not explicitly teach the operand inputs being snan. However, Zbiciak teaches the possibility of the input operands being snan (Zbiciak: ¶ 0096; Claims 2 and 14) which would therefore be set as a 0 operand through the qualifier circuit (i.e., convertor engine, Fig. 3 1000) of Hinds after the determination of the operand carried out by the detection logic circuit (i.e., logic engine, Fig. 3 800).
The motivation to combine provided with respect to claim 23 applies equally to claim 25.
Hinds in view of Zbiciak in view of Lutz therefore teaches:
The system of Claim 14, wherein the input data is a signaling not-a-number and wherein the modified value is zero.
Regarding claim 27, Hinds in view of Zbiciak in view of Lutz further teaches a logic engine for receiving input data for a floating point operation (Hinds: Abstract Lines 1-7 data processing apparatus that takes as inputs floating point operands to apply a floating point operation via Fig. 3 Element 800 detection logic i.e., logic engine, means for receiving) at floating point unit (Hinds: Col. 17 Lines 60-62 floating point arithmetic operation carried out through floating point unit), determining at a logic engine whether the input data’s value would cause a floating point hardware exception responsive to the floating point arithmetic operation on the input data (Hinds: Col. 12 Lines 34-44 detection logic i.e. logic engine determines if inputs may cause a floating point hardware exception; Col. 12 Lines 22-28 special operand determination; Fig. 3 Element 800 detection logic circuit i.e., detection logic circuit, means for determining), and converting at a convertor engine the values of the input data to a modified value, the modified value being used for the floating point arithmetic operation (Hinds: Fig. 3 Element 1000 qualifier circuit i.e., means for converting; Col. 3 Lines 8-13 exception determination logic determines if exception may occur using operands before exception is made before floating point operation and once conversion occurs of values operation is made with those converted values).
Although Hinds teaches determining different kinds of inputs that may cause a floating point hardware exception (Hinds: Col. 12 Lines 22-28), Hinds does not explicitly teach determining whether the input is specifically a positive or negative infinity.
However, Zbiciak teaches determining specifically if the input is denormal, infinity, qnan or snan values (Zbiciak: ¶ 0096; Claims 2 and 14).
The motivation to combine provided with respect to claim 1 applies equally to claim 27.
Hinds in view of Zbiciak does not explicitly teach:
wherein the modified value differs based on whether the received input data is positive infinity or negative infinity.
However, Lutz teaches:
wherein the modified value differs based on whether the received input data is positive infinity or negative infinity (Lutz: ¶ 0113 setting the value at different values based on if the input is negative infinity or positive infinity; Table 4).
The motivation to combine with respect to claim 1 applies equally to claim 27.
Hinds in view of Zbiciak in view of Lutz therefore teaches:
A system comprising:
a means for receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data;
a means for determining whether the received input data is positive infinity or negative infinity prior to performing the floating point arithmetic operation; and
a means for converting a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is positive infinity or negative infinity, wherein the modified value differs based on whether the received input data is positive infinity or negative infinity.
Claims 28-30, 32, and 35 teach the system that practices the method of claims 2-4, 7, and 10 respectively and are therefore rejected for the same reasons therein.
Regarding claim 38, Hinds in view of Zbiciak in view of Lutz further teaches:
The method of claim 1, wherein the converting comprises:
setting the modified value to a maximum supported number when the received input data is positive infinity (Lutz: ¶ 0113 and Table 4 when the input is positive infinity, the highest possible number i.e., supported number closest to positive infinity is selected); and
setting the modified value to a minimum supported number when the received input data is negative infinity (Lutz: ¶ 0113 and Table 4 when the input is being negative infinity, the lowest possible number i.e., supported number closest to negative infinity is selected).
The motivation to combine with respect to claim 1 is equally applicable to claim 38.
Claims 5, 18, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Hinds in view of Zbiciak in view of Lutz, further in view of Wilkins et al. (US 2014/0195581 A1) (hereinafter “Wilkins”).
Regarding claim 5, while Hinds in view of Zbiciak in view of Lutz teaches the method of claim 2 and setting a value of the output based on certain conditions (Hinds: Col. 14 Lines 20-29 if operand is denormal, operand is treated as zero i.e., converted/flushed to 0 and the IsZero signal is activated; Col. 14 Lines 53-55 describe that if the IsZero signal is activated the output will be selected to be 0), Hinds in view of Zbiciak in view of Lutz does not explicitly teach setting an output value to a maximum supported number if a value is a positive infinity or setting an output value to a minimum supported number if a value is a negative infinity.
However, Wilkins teaches:
setting a value of the output result to a maximum supported number if a value of the output result is a positive infinity, and setting a value of the output result to a minimum supported number if a value of the output result is a negative infinity (Wilkins: ¶ 0051 setting at a maximum number or minimum number in the case of infinity which is caused by division by 0).
It would be obvious before the effective filing date of the claimed invention to combine the value setting as taught by Wilkins with the method as taught by Hinds in view of Zbiciak in view of Lutz as all teaching are directed to floating point computations. The improvement of Wilkins lies in being able to handle infinity input (¶ 0051).
Regarding claim 18 and 31 teach the system that practices the method of claim 5 and are therefore rejected for the same reasons therein.
Claims 8, 21, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Hinds in view of Zbiciak in view of Lutz, further in view of Sharangpani et al. (5886915) (hereinafter “Sharangpani”).
Regarding claim 8, while Hinds in view of Zbiciak in view of Lutz teaches the method of claim 7, Hinds in view of Zbiciak in view of Lutz does not explicitly teach generating an out-of-bounds flag associated with the denormal number.
However, Sharangpani teaches:
The method of Claim 7 further comprising generating an out-of-bounds flag associated with the denormal number (Sharangpani: Col. 8 Lines 7-19 setting status flag when denormal number at input is replaced with 0; Fig. 3 320).
It would be obvious before the effective filing date of the claimed invention to combine the 0-setting when the input data is a denormal number as taught by Sharangpani with the method of Hinds in view of Zbiciak in view of Lutz as all teachings are directed towards floating point computations. Sharangpani enhances the method of Hinds in view of Zbiciak in view of Lutz by accounting for the resulting lost precision due to the setting (Sharangpani: Col. 8 Lines 7-10).
Claims 21 and 33 recite the system that practices the method of claim 8 and are therefore rejected for the same reasons therein.
Claims 9, 22, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Hinds in view of Zbiciak in view of Lutz, further in view of Swartzlander, JR et al. (US 2014/0074903 A1) (hereinafter “Swartzlander”).
Regarding claim 9, while Hinds in view of Zbiciak in view of Lutz teaches the method of claim 1, Hinds in view of Zbiciak in view of Lutz does not explicitly teach generating an out-of-bounds flag associated with the input data being either positive or negative infinity.
However, Swartzlander teaches:
generating an out-of-bounds flag associated with the input data being either positive or negative infinity (Swartzlander: ¶ 0074 overflow flag i.e., out-of-bounds flag set when input is positive or negative infinity).
It would be obvious before the effective filing date of the claimed invention to combine the out-of-bounds flag as taught by Swartzlander with the method of Hinds in view Zbiciak in view of Lutz as all teachings are directed to floating point computations. The enhancement of Swartzlander lies in accounting for values that exceed the maximum or minimum allowed values (Swartzlander: ¶ 0074).
Claims 22 and 34 recite the system that practices the method of claim 9 and are therefore rejected for the same reasons therein.
Claims 11, 13, 24, 26, 36, and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Hinds in view of Zbiciak in view of Lutz, further in view of Kuroiwa (5309383) (hereinafter “Kuroiwa”).
Regarding claim 11, while Hinds in view of Zbiciak in view of Lutz teaches the method of Claim 10, Hinds in view of Zbiciak does not explicitly teach generating an un-initialized flag associated with the input data being a qnan.
However, Kuroiwa teaches:
generating an un-initialized flag associated with the input data being the qnan (Wilkins: Col. 8 Lines 44-52 flag set in relation to input being qnan).
It would be obvious before the effective filing date of the claimed invention to combine the flag generating as taught by Kuroiwa with the method as taught by Hinds in view of Zbiciak in view of Lutz as all teachings are directed towards floating point computations. Kuroiwa enhances the method of Hinds in view of Zbiciak in view of Lutz by ensuring proper detection and determination of the various types of inputs (Kuroiwa: Col. 8 Lines 44-52).
Regarding claim 13, while Hinds in view of Zbiciak in view of Lutz teaches the method of Claim 12, Hinds in view of Zbiciak in view of Lutz does not explicitly teach generating an un-initialized flag associated with the input data being a snan.
However, Kuroiwa teaches:
generating an un-initialized flag associated with the input data being the snan (Wilkins: Col. 8 Lines 44-52 flag set in relation to input being snan).
The motivation to combine provided with respect to claim 11 applies equally to claim 13.
Claims 24 and 26 recite the system that practices the method of claims 11 and 13 respectively and are therefore rejected for the same reasons therein.
Claim 36 recites the system that practices the method of claim 11 and is therefore rejected for the same reasons therein.
Regarding claim 37, Hinds in view of Zbiciak in view of Lutz teaches the system of claim 27. Hinds further teaches a detection logic circuit that detects if any of the operands may cause an exception (i.e., if the operand is denormal, a NaN, infinity, or 0). In the case that any of the operands may cause an exception, the operand is to be treated as zero flushed i.e., set to 0 through the IsZero signal (Hinds: Col. 14 Lines 20-38). While Hinds does teach the possibility of operands being a nan (Hinds: Col. 12 Lines 22-28), Hinds does not explicitly teach the operand inputs being snan. However, Zbiciak teaches the possibility of the input operands being snan (Zbiciak: ¶ 0096; Claims 2 and 14) which would therefore be set as a 0 operand through the qualifier circuit (i.e., convertor engine, Fig. 3 1000) of Hinds after the determination of the operand carried out by the detection logic circuit (i.e., logic engine, Fig. 3 800).
The motivation to combine provided with respect to claim 12 applies equally to claim 37.
Hinds in view of Zbiciak in view of Lutz does not explicitly teach generating an un-initialized flag when the input data is a snan and the input data is set to 0.
However, Kuroiwa teaches:
generating an un-initialized flag associated with the input data being the snan (Wilkins: Col. 8 Lines 44-52 flag set in relation to input being snan).
The motivation to combine provided with respect to claim 13 applies equally to claim 37.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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