DETAILED ACTION
This action is in response to the arguments and amendments filed on 2/11/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Badrieh (US Patent 11636891) in view of Jain et al. (US Patent 7902800) and Lin et al. (US Patent 10938298). Regarding claim 1, Badrieh discloses (see fig. 3) a device comprising: a power stage (315, 385a-b) that provides an output signal (regulated output from 315) and a first feedback signal (outputs from 385b) based on an input signal (output from 305) and a control signal (comparison output signal within 315 that’s used in regulating the voltage output from 315); a digital stage (360) having digital circuitry that provides a second feedback signal (output from 360) based on operational activity of the digital circuitry using the output signal (output from 360 based on 365/375/380, which is based on output from 385a), wherein: the first feedback signal (output from 385b) refers to an output power based voltage signal (output from 385b is a sensed output voltage). Badrieh does not disclose that the output signal refers to an output power based current signal generated and provided by the power stage directly to the digital circuitry of the digital stage; a control stage that provides the control signal based on the input signal, the first feedback signal and a second feedback signal, wherein the first feedback signal refers to an output power based voltage signal generated by a voltage regulation circuity of the power stage. Jain et al. discloses (see fig. 1 and 2) that an output signal (Io) refers to an output power based current signal generated and provided by a power stage (Io is from power stage 210) directly to digital circuitry of a digital stage (see Io direct connection to 100). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Badrieh to include the features of Jain et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Lin et al. discloses (see fig. 2) a control stage (10) that provides a control signal (output from 10) based on an input signal (VAC, which used in producing VCC), a first feedback signal (VCOM) and a second feedback signal (VCS. All three signals are concurrently needed to produce the output from 10. VCC is needed as a working voltage for 10 (see column 4 lines 42-44). Once 10 is operating, VCOM and VCS are also used to generate the output from 10), wherein the first feedback signal (VCOM) refers to an output power based voltage signal (VCOM is a voltage signal) generated by a voltage regulation circuity of the power stage (VCOM originates from voltage regulation circuitry (30/40/50/60/70/FB) of the power stage shown in fig.2). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Badrieh to include the features of Lin et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Badrieh (US Patent 11636891) in view of Jain et al. (US Patent 7902800), Lin et al. (US Patent 10938298) and Huang (US Patent 8416596). Regarding claim 5, Badrieh does not disclose that the control stage receives a reference signal and provides the control signal to the power stage based on the input signal, the reference signal, the first feedback signal and the second feedback signal, the control stage is directly coupled to the power stage so as to provide the control signal to the power stage, and the input signal refers to an input voltage signal, and the reference signal refers to a reference voltage signal. Huang discloses (see fig. 2) a control stage(220) receives a reference signal (output from 227) and provides a control signal (output from 220) to a power stage (output to 200) based on an input signal (Vdd), the reference signal (Vref), a first feedback signal (output from 240) and a second feedback signal (VCS), the control stage is directly coupled to the power stage (direct connection of 220 to 200) so as to provide the control signal to the power stage, and the input signal refers to an input voltage signal (Vdd is an input voltage), and the reference signal refers to a reference voltage signal (Vref is a reference signal). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Badrieh to include the features of Huang because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies.
Claim(s) 12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Badrieh (US Patent 11636891) in view of Lin et al. (US Patent 10938298) and Huang (US Patent 8416596). Regarding claim 12, Badrieh discloses (see fig. 3) a device comprising: first control circuitry (350) that receives a first feedback signal from voltage regulation circuitry (350 connection to feedback from voltage regulator 315) and provides a first control signal based on the first feedback signal (output from 350); second control circuitry (380) that receives a second feedback signal from digital circuitry (output from 365/375 to 380) and provides a second control signal based on the second feedback signal (output from 380). Badrieh does not disclose merging circuitry that receives the first control signal from the first control circuitry, receives the second control signal from the second control circuitry, and then generates and provides a unified control signal to the voltage regulation circuitry based both the first control signal and the second control, wherein: the voltage regulation circuitry provides multiple regulated output signals as output including the first feedback signal, and the first control circuitry receives an input voltage, receives a reference voltage, receives the first feedback signal from the voltage regulation circuitry, and provides the first control signal to the merging circuitry based on the input voltage, the reference voltage and the first feedback signal. Lin et al. discloses (see fig. 2) merging circuitry (12) that receives a first control signal from a first control circuitry (output from ADC1 to first input of 12), the first control signal being based on the input voltage (Vcc), a reference voltage (GND) and a first feedback signal (VCS), receives a second control signal from a second control circuitry (output from ADC2 to 12), and then generates and provides a unified control signal (VGS is a whole signal) to a voltage regulation circuitry (40/30/60/70) based on both the first control signal and the second control signal (output from 12 is based on the outputs from ADC1 and ADC2). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Badrieh to include the features of Lin et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Huang discloses (see fig. 2) a voltage regulation circuitry (240/RS) that provides multiple regulated output signals as output including a first feedback signal (see outputs VCS and FB), and a first control circuitry (220) that receives an input voltage (VDD), receives a reference voltage (Vref), and receives the first feedback signal from the voltage regulation circuitry (outputs from 240/RS to 220). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Badrieh to include the features of Huang because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claim 14, Bradrieh discloses (see fig. 3) that the first feedback signal (output from 385b) refers to an output power based voltage signal generated and provided by the voltage regulation circuitry directly to the first control circuitry (direct connection between output from 385b to 350), and the second feedback signal (output from 365/375 to 380) refers to an activity factor based signal generated and provided by the digital circuitry based on the operational activity of the digital circuitry (output from 365/375 to 380 is based on the activity of 375).
Claim(s) 7-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Badrieh (US Patent 11636891) in view of Jain et al. (US Patent 7902800), Lin et al. (US Patent 10938298) and Radic (US Patent 11183937). Regarding claim 7, Badrieh does not disclose that the power stage includes voltage regulation circuitry that receives the control signal from the control stage and then provides the first feedback signal to the control stage by way of a first feedback loop path, and the power stage is coupled between the control stage and the digital stage so that the voltage regulation circuitry receives the control signal directly from the control stage and then provides the output signal directly to the digital circuitry. Radic discloses (see fig. 1) that a power stage includes voltage regulation circuitry (M1, 102, feedback circuitry) that receives a control signal from a control stage (output from 116/106/121/110/114/120 to gate of M1) and then provides a first feedback signal to the control stage by way of a first feedback loop path (feedback loop comprising ISNS to 121/110), and the power stage is coupled between the control stage and a digital stage (M1, 102, feedback circuitry connected between 113/108 and 116/106) so that the voltage regulation circuitry receives the control signal directly from the control stage (direct connection between 116/106/121/110/114/120 to gate of M1) and then provides an output signal directly to the digital circuitry (direct connection between feedback circuitry providing Vfb and 113/108). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Badrieh to include the features of Radic because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claim 8, Badrieh does not disclose that the first feedback loop path is a standard loop path that is configured to provide the first feedback signal directly to the control stage as an output power based voltage signal generated and provided by the power stage. Radic discloses (see fig. 1) that the first feedback loop path (path including voltage ISNS) is a standard loop path that is configured to provide the first feedback signal directly to the control stage as an output power based voltage signal generated and provided by the power stage (see direction of ISNS to control stage 116/106/121/110/114/120). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Badrieh to include the features of Radic because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claim 9, Badrieh does not disclose that the digital stage includes the digital circuitry that receives the output signal from the power stage and then provides the second feedback signal to the control stage by way of a second feedback loop path, and the digital stage is coupled to the power stage and the control stage so that the digital circuitry receives the output signal directly from the power stage and then provides the second feedback signal directly to the control circuitry. Radic discloses (see fig. 1) that a digital stage (113/108) includes the digital circuitry that receives an output signal from a power stage (113/108 connection to Vfb from power stage comprising M1, 102, feedback circuitry) and then provides a second feedback signal to a control stage by way of a second feedback loop path (path including output from 113/108 to control stage comprising 116/106/121/110/114/120), and the digital stage is coupled to the power stage and the control stage so that the digital circuitry receives the output signal directly from the power stage (direct connection of Vfb to 113/108) and then provides the second feedback signal directly to the control circuitry (direct connection of 113/108 to control circuitry). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Badrieh to include the features of Radic because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding clam 10, Badrieh does not disclose that the second feedback loop path is an observer loop path that is configured to provide the second feedback signal directly to the control stage as an activity factor based signal generated and provided by the digital stage based on the operational activity of the digital circuitry using the output signal. Radic discloses (see fig. 1) that the second feedback loop path is an observer loop path (path between 113/108 and control stage 116/106/121/110/114/120) that is configured to provide the second feedback signal directly to the control stage as an activity factor based signal generated and provided by the digital stage based on the operational activity of the digital circuitry using the output signal (direct connection of output from 113/108 to control stage 116/106/121/110/114/120). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Badrieh to include the features of Radic because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claim 11, Bradrieh does not disclose that the digital circuitry comprises processing circuitry with at least one of a processor, a central processing unit (CPU), a digital signal processor (DSP), and a graphics processing unit (GPU). Radic discloses (see fig. 1) that the digital circuitry comprises processing circuitry with at least one of a processor (113/108), a central processing unit (CPU), a digital signal processor (DSP), and a graphics processing unit (GPU). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Badrieh to include the features of Radic because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Badrieh (US Patent 11636891) in view of Lin et al. (US Patent 10938298) and Huang (US Patent 8416596) and Arpino et al. (US Patent 11682962). Regarding claim 13, Badrieh does not disclose that the merging circuitry sums the first control signal and the second control signal to generate the output control signal. Arpino et al. discloses (see fig. 4) a merging circuitry (summer 86) that integrates a first control signal (output from 94) and a second control signal (output from 88) into a single control waveform that regulates voltage output of a voltage regulation circuitry (single output 106 from summer 86 used as a control means to regulate the voltage output from 12), wherein the single control waveform is provided as a control-path signal to voltage regulation circuitry (single output 106 to voltage regulation circuitry 96/42/12). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the device of Badrieh to include the features of Arpino et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies.
Allowable Subject Matter
Claims 3-4 are allowed.
The following is an examiner’s statement of reasons for allowance: Regarding claim 3, the prior art fails to teach or disclose a device comprising wherein: the second feedback signal refers to an activity factor based control voltage signal generated and provided by the digital stage based on the operational activity of the digital circuitry using the output signal, and the activity factor based control voltage signal has an activity factor that predictively measures the operational activity of the digital circuitry, in combination with all the limitations set forth in claim 3.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 2, 6, and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments (filed on 2/11/2026) with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments (filed on 2/11/2026) regarding claim 12 have been fully considered but they are not persuasive. Regarding claim 12, the applicant argues that “Badrieh describes two distinct feedback paths - an analog feedback circuit 350 (with RC 355) and a digital feedback circuit 360 (oscillator 365 / counter 375 / DAC 380). Critically, Badrieh explains that only one path is used at a time: "the regulator 315 may receive the feedback signal 325 from the analog feedback circuit 350. In other examples, the regulator 315 may receive the feedback signal 325 from the digital feedback circuit 360. That is, the circuit 300 may further include switches or other similar components to select either the analog feedback circuit 350 or the digital feedback circuit 360 ... In some cases, the selection ... may be dynamically selectable ... In some cases, the selection ... may be determined ... and may be hard-coded ..." (See Badrieh, col. 9, lines 13-43; col 10, lines 4-14). This disclosure makes clear that Badrieh is built on a selection mechanism that chooses between feedback paths, rather than combining them. Such a system teaches away from the claimed “merging circuitry” that generates a unified control signal based on both a first control signal and a second control signal. The examiner does not agree with the applicant’s arguments regarding the Badrieh reference. As stated in the rejection of claim 12 above, Badrieh is not relied upon to disclose “merging circuitry that receives the first control signal from the first control circuitry, receives the second control signal from the second control circuitry, and then generates and provides a unified control signal to the voltage regulation circuitry based on a combination of the first control signal and the second control, wherein: the voltage regulation circuitry provides multiple regulated output signals as output including the first feedback signal, and the first control circuitry receives an input voltage, receives a reference voltage, receives the first feedback signal from the voltage regulation circuitry, and provides the first control signal to the merging circuitry based on the input voltage, the reference voltage and the first feedback signal”. The Lin et al. reference is relied upon to disclose (see fig. 2) merging circuitry (12) that receives a first control signal from a first control circuitry (output from ADC1 to first input of 12), the first control signal being based on the input voltage (Vcc), a reference voltage (GND) and a first feedback signal (VCS), receives a second control signal from a second control circuitry (output from ADC2 to 12), and then generates and provides a unified control signal (VGS is a whole signal) to a voltage regulation circuitry (40/30/60/70) based on both the first control signal and the second control signal (output from 12 is based on the outputs from ADC1 and ADC2). Further regarding claim 12, the applicant argues that “Lin states: " the power controller 10 comprises a first analog-to-digital conversion (ADC) unit ADC1 a second ADC unit ADC2 and a digital processing core unit 12. The first ADC unit ADC1 is intended to receive the current sensing signal VCS and generate a digital current sensing signal DVCS, and the second ADC unit ADC2 is intended to receive the load feedback signal VCOM and generate a digital load feedback signal DVCOM. In addition, the digital processing core unit 12 receives the digital current sensing signal DVCS and the digital load feedback signal DVCOM to generate the PWM driving signal VGS and at the same time perform the load power detection illustrated in FIG. 1". (See Lin, col. 7, lines 25-37). This disclosure confirms that Lin's digital processing core receives measured values and produces a PWM drive signal. Lin does not disclose first control circuitry that receives a first feedback signal from voltage regulation circuitry and provides a first control signal based on that first feedback signal, as required by claim 12. In particular, Lin's ADC1 receives VCS (a current sensing signal) and Lin's ADC2 receives VCOM (a load feedback signal), which are measured signals, not control signals. Processing multiple sensed parameters is not equivalent to merging control-path outputs into a unified control signal based on both control signals, as now required by claim 12.”. The examiner does not agree with the applicant’s arguments regarding the Lin reference. The outputs from ADC1 and ADC2 are first and second control signals (which are produced by receiving a first feedback signal VCS and a second feedback signal VCOM) because they are both used in controlling the operation of 12 to produce the signal VGS. Therefore, Lin does disclose (see fig. 2) merging circuitry (12) that receives a first control signal from a first control circuitry (output from ADC1 to first input of 12), the first control signal being based on the input voltage (Vcc), a reference voltage (GND) and a first feedback signal (VCS), receives a second control signal from a second control circuitry (output from ADC2 to 12), and then generates and provides a unified control signal (VGS is a whole signal) to a voltage regulation circuitry (40/30/60/70) based on both the first control signal and the second control signal (output from 12 is based on the outputs from ADC1 and ADC2). Further regarding claim 12, the applicant argues that “Huang is directed to conventional regulator loops. While it shows standard feedback- based regulation, Huang does not contemplate (and therefore cannot teach or suggest) merging two separate control-path outputs into a single regulation control signal. Accordingly, Huang does not supply the missing teaching absent from Badrieh and Lin. Accordingly, for at least for the above reasons, the cited sections of Lin, Badrieh, and Huang, as relied upon by the Examiner, do not teach, suggest, or otherwise disclose the limitations as recited in claim 12, at least as amended. Thus, clam 12 is patentable over Lin, Badrieh, and Huang, taken individually or in combination (assuming arguendo such a combination can be made which Applicant does not admit). Claim 14 is patentable at least by virtue of its dependence on claim 12”. The examiner does not agree with the applicant’s arguments regarding the Huang reference. Huang is not relied upon to disclose “merging two separate control path outputs into a single regulation control signal”. Furthermore, claim 12 does not state “merging two separate control path outputs into a single regulation control signal”. Claim 12 merely states “merging circuitry that receives the first control signal from the first control circuitry, receives the second control signal from the second control circuitry, and then generates and provides a unified control signal to the voltage regulation circuitry based on both the first control signal and the second control”, which is taught by Lin et al. (see claim 12 rejection above) not Huang.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY A GBLENDE whose telephone number is (571)270-5472. The examiner can normally be reached M-F 9am-5pm.
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/JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
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