Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 2, 2026 has been entered.
Response to Amendment
This Office action is in response to the applicant’s amendment filed on March 2, 2026.
Claim 25 has been added.
Claim Objections
Claims 1, 4, 11, and 17 are objected to because of the following informalities:
Claim 1, line 2 “a memory controller circuitry” should read “memory controller circuitry”
Claim 1, line 3 “an interface circuitry” should read “interface circuitry”
Claim 4, lines 2-3 “wherein the allocate the address range” should read “wherein allocating the address range”
Claim 4, line 3 “comprises allocate” should read “comprises allocating”
Claim 11, line 4 “configure a memory controller circuitry” should read “configure memory controller circuitry”
Claim 11, line 7 “an interface circuitry” should read “interface circuitry”
Claim 17, line 2 “a memory controller circuitry” should read “memory controller circuitry”
Claim 17, line 5 “an interface circuitry” should read “interface circuitry”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20, 23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Cawlfield et al. (US 8863141 B2), hereinafter referred to as Cawlfield, in view of Guim Bernat et al. (US 20190042294 A1), hereinafter referred to as as Guim Bernat, further in view of Venkatesh et al. (US 7464201 B1), hereinafter referred to as Venkatesh, further in view of Tanenbaum (non-patent literature, Tanenbaum, Andres S. Structured Computer Organization Second Edition, Englewood Cliffs N.J., Prentice-Hall. Inc., 1984. Page 11)
Regarding claim 1, Cawlfield discloses an apparatus comprising: a memory controller (a hypervisor operative on the host system, wherein the host system comprises at least one memory and at least one processor coupled to the memory, to manage the plurality of logical partitions of pools of virtualized resources [Cawlfield claim 1]. The at least one processor coupled to the memory would operate the hypervisor which manages (controls) the memory, making the processor(s) a memory controller.) to allocate an address range for a process among the multiple memory pools (responsive to determining that insufficient local resources are available for reservation to meet a performance parameter for at least one resource specified in a reservation request for a particular logical partition managed by the hypervisor in the host system, to identify another logical partition from among the plurality of logical partitions that is assigned the at least one resource meeting the performance parameter specified in the reservation request [Cawlfield claim 1]. The reservation request can be for an allocation of memory which would include allocating a range of addresses among multiple memory pools [“For example, if the reservation request is for a memory allocation” Cawlfield col. 9 lines 57-58]. The allocation would be for an application or workload, which are kinds of processes [“a hypervisor may manage the allocation of resources into one or more logical partitions, or virtual machine, each representing a separate logical grouping of resources assigned to an instance of an operating system, upon which an application or workload runs” Cawlfield col. 1 lines 18-22]) based on parameters associated with the address range and performance capabilities of the multiple memory pools, (“With reference now to FIG. 7, a block diagram illustrates one example of a broker agent managing local memory allocations and logical partition migrations, to provide memory meeting the quality of service requirements of one or more workloads.” [Cawlfield col. 15 lines 1-5]. The broker agent is part of the hypervisor (see Fig. 1) running on the processor that serves as a memory controller. Providing memory meeting the quality of service requirements would entail providing memory with corresponding performance capabilities.)
Cawlfield does not appear to explicitly disclose memory controller circuitry comprising: interface circuitry to receive memory access commands to forward to a memory pool of multiple memory pools and circuitry to allocate an address range wherein: the memory controller circuitry is to process the received memory access commands, the memory access commands comprise one or more of a memory read or memory write.
However, Guim Bernat teaches memory controller circuitry comprising: interface circuitry to receive memory access commands to forward to a memory pool of multiple memory pools and (“FIG. 4 is an example of a detailed architecture of a platform 310 and a pooled memory 320, 330 in accordance with one aspect. The platform 310 includes an NIC 312 (e.g. iNIC). The NIC 312 may be extended to act as a first level of interface and as a first level of intelligence in order to distribute push and pull requests from the VNFs/services across different pooled memories and storage schemes. For example, the extension of the NIC 312 may be implemented in the NIC FPGA” [Guim Bernat par. 36]. Wherein NIC stands for network interface card (see Guim Bernat par. 24), an FPGA is circuitry, and the broadest reasonable interpretation of memory controller circuitry includes network level memory controllers such as the NIC 312. Additionally “The NIC 312 may include pull and push interfaces 406. The pull and push interfaces 406 may be used by the VNFs or services (running in a local server or FPGAs) to push or pull data to and from different VNFs or services. The pull and push interfaces 406 may use the system address decoder 408 to decide to which physical memory pool or pools the pull or push requests need to be sent” [Guim Benat par. 40]. Wherein a pull request is synonymous with a memory access command.) wherein: the memory controller circuitry is to process the received memory access commands, the memory access commands comprise one or more of a memory read or memory write (See above. Wherein push and pull requests are forms of memory write access and memory read access commands (respectively), and forwarding/distributing received memory access commands is a form of processing received memory access commands).
Cawlfield and Guim Bernat are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Cawlfield and Guim Bernat before him or her, to modify the apparatus of Cawlfield to include the attributes of memory controller circuitry comprising: interface circuitry to receive memory access commands to forward to a memory pool of multiple memory pools and circuitry to allocate an address range wherein: the memory controller circuitry is to process the received memory access commands, the memory access commands comprise one or more of a memory read or memory write of Guim Bernat because it will enhance apparatus efficiency.
The motivation for doing so would be for the purpose of load balancing and improving quality of service.
The reason for doing so would be “For each virtual channel, the tenant may specify bandwidth requirements. In order to meet the bandwidth requirements, the POD manager or the resource manager may allocate multiple physical memory pools to a particular virtual channel or, alternatively or additionally, configure a quality of service (QoS) bandwidth level from a physical memory pool to meet the bandwidth needs of the particular virtual channel. In this case, push requests to those memory pools are not replicated but may be distributed across the multiple physical memory pools to achieve the required bandwidth” [Guim Bernat paragraph 34]. In this example, greater quality of service in terms of bandwidth was achieved by balancing the load across the multiple physical memory pools. In the case of allocating addresses, greater memory capacity could similarly be made available through this technique, for example.
Therefore, it would have been obvious to combine Cawlfield and Guim Bernat to obtain the invention as specified in the instant claim.
Neither Cawflield nor Guim Bernat appear to explicitly disclose the memory controller circuitry is to communicate with the multiple memory pools by Ethernet packets.
However, Venkatesh teaches the memory controller circuitry is to communicate with the multiple memory pools by Ethernet packets (“Network systems typically have a media access controller (MAC), which receives packets from a physical media such as twisted pair copper wire in the case of IEEE 802.3 commonly known as copper ethernet, or from a wireless front end which converts RF signals into packets as in the case of IEEE standard 802.11, commonly known as wireless ethernet. The MAC provides the interface from a variety of physical interfaces and produces a single interface for receiving and transmitting packets” [Venkatesh col. 1 lines 19-27]. Wherein it would be obvious to a person having ordinary skill in the art that a MAC would comprise circuitry in view of Venkatesh (see additionally Venkatesh Figs. 1 and 2)).
Cawlfield/Guim Bernat and Venkatesh are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Cawlfield/Guim Bernat and Venkatesh before him or her, to modify the apparatus of Cawlfield/Guim Bernat to include the attributes of the memory controller circuitry is to communicate with the multiple memory pools by Ethernet packets of Venkatesh because it will enhance apparatus efficiency.
The motivation for doing so would be to enable high speed communication with a shared memory. “For example, [it] is currently possible to place many gigabit ethernet devices on a shared memory 18 in an Intel cpu-based host, or personal computer (PC) 12” (bracketed text added for grammatical clarity) [Venkatesh col. 1 lines 43-46].
Therefore, it would have been obvious to combine Cawlfield/Guim Bernat and Venkatesh to obtain the invention as specified in the instant claim.
None of Cawlfield/Guim Bernat/Venkatesh appear to explicitly disclose circuitry to allocate an address range for a process among the multiple memory pools based on parameters associated with the address range and performance capabilities of the multiple memory pools.
However, Tanenbaum teaches circuitry to allocate an address range for a process among the multiple memory pools based on parameters associated with the address range and performance capabilities of the multiple memory pools (Tanenbaum page 11 “hardware and software are logically equivalent”. In combination with the teachings of Cawlfield/Guim Bernat/Venkatesh it would have been obvious for a person having ordinary skill in the art to implement such logic as hardware circuitry).
Cawlfield/Guim Bernat/Venkatesh and Tanenbaum are analogous art because they are from the same field of endeavor of computer engineering.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Cawlfield/Guim Bernat/Venkatesh and Tanenbaum before him or her, to modify the apparatus of Cawlfield/Guim Bernat/Venkatesh to include the attributes of circuitry to allocate an address range for a process among the multiple memory pools based on parameters associated with the address range and performance capabilities of the multiple memory pools of Tanenbaum because it will enhance apparatus efficiency
The motivation for doing so would be “Any operation performed by software can also be built directly into the hardware and any instruction executed by the hardware can also be simulated in software. The decision to put certain functions in hardware and others in software is based on such factors as cost, speed, reliability, and frequency of expected changes … As time progressed, it became obvious to hardware designers that certain operations were being performed frequently enough to justify constructing special hardware circuits to execute them directly (to make them faster)” [Tanenbaum page 11].
Therefore, it would have been obvious to combine Cawlfield/Guim Bernat/Venkatesh and Tanenbaum to obtain the invention as specified in the instant claim.
Regarding claims 11 and 17, the applicant is directed to the rejection to claim 1 above, as they are rejected under the same rationale.
Regarding claim 2, Cawlfield/Guim Bernat/Venkatesh/Tanenbaum discloses the apparatus of claim 1, wherein the service level parameters comprise two or more of latency, network bandwidth, amount of memory allocation, memory bandwidth, data encryption use, type of encryption to apply to stored data, use of data encryption to transport data to a requester, memory technology, and/or durability of a memory device (Managing memory allocations (see the citations from claim 1 above) inherently includes managing an amount of memory allocation. Furthermore, Cawlfield discloses “Factors that may influence policy broker 540 in determining the best remote host system for a particular workload may include, but are not limited to, I/O requirements of the application, including CPU, memory usage, network bandwidth, and disk space requirements, power usage of the application, and hardware requirements, such as a particular adapter or hardware accelerator required for an application” [col. 11 lines 16-23]. Policy broker 540 is part of the hypervisor running on the processor serving as a memory controller (see figures 1, 2, and 5). Thus, Cawlfield discloses two or more the recited service level parameters in claim 2.)
Regarding claims 12 and 18, the applicant is directed to the rejection to claim 2 above, as they are rejected under the same rationale.
Regarding claim 3, Cawlfield/Guim Bernat/Venkatesh/Tanenbaum discloses the apparatus of claim 1, wherein the performance capabilities of the multiple memory pools are based on two or more of: latency, network bandwidth, amount of memory allocation, memory bandwidth, data encryption use, type of encryption to apply to stored data, use of data encryption to transport data to a requester, memory technology, and/or durability of a memory device (Cawlfield discloses amount of memory allocation as a performance capability. The logical partitions (LPAR) serve as pools. Data will be allocated to an LPAR capable or performing the required allocation. “With reference now to FIG. 7, a block diagram illustrates one example of a broker agent managing local memory allocations and logical partition migrations, to provide memory meeting the quality of service requirements of one or more workloads. In the example, as illustrated at reference numeral 702, in a first system memory allocation, the memory available in a host system is allocated between "LPAR 1", "LPAR 2", and "LPAR 3" or is available in as free memory. In the example, a workload in "LPAR 3" requests a lease of memory for two hours and broker agent 146 leases the memory to "LPAR 3" from the free memory, as illustrated at reference numeral 704. Next, in the example, a workload in "LPAR 2" requests additional memory and specifies a performance parameter of real memory, but the request requires a memory allocation that that is larger than the remaining free memory, which would result in an overallocation, as illustrated at reference numeral 706. Since broker agent 146 determines that the additional memory required by "LPAR 2" is not available locally, and the requesting application in "LPAR 2" requires real memory and an altruistic cost, broker agent 146 determines whether it is more cost effective to migrate "LPAR 2" to a remote host system or to migrate "LPAR 3" to a remote host system and free up the memory leased to "LPAR 3", to locally provide the memory required by "LPAR 2". In the example, broker agent 146 determines that it is more cost effective to migrate "LPAR 2" to a remote host system and "LPAR 2" approves the offer to migrate to a remote host to receive the requested real memory” [Cawlfield col. 15 lines 1-28 and Fig. 7]. Additionally, “Performance parameters may include, but are not limited to, a lease start time, a lease duration, a desired quality of service (QoS), a resource locality, and a cost. In one example, a lease start time may specify "now" and may specify one or more future times. In one example, a lease duration may specify a particular time or may specify a workload estimation. In one example, a desired QoS may specify a particular type of resource, a particular option for a resource, or other values that indicate a quality of service for a particular type of resource” [Cawlfield col. 5 lines 35-44]. Wherein specifying a particular type of resource would include specifying the type of memory technology, see “the "quality of service" value specified in a memory allocation request may specify "real memory" to designate that memory paging is not acceptable” [Cawlfield col. 9 lines 20-23]).
Regarding claims 13 and 19, the applicant is directed to the rejection to claim 3 above, as they are rejected under the same rationale.
Regarding claim 4, Cawlfield/Guim Bernat/Venkatesh/Tanenbaum discloses, the apparatus of claim 1, wherein allocating an address range for a process among multiple memory pools comprises allocating address translations to the address range based on the multiple memory pools that store data associated with the address range (“operating system 108 may determine there is insufficient memory in a shared memory pool to allocate for the resource request, but operating system 108 may apply a quality of service policy for a performance trade-off, such as memory paging, to satisfy the resource request” [Cawlfield col. 8 lines 63-67]. Memory paging requires address translations and virtual memory allocations).
Regarding claims 14, the applicant is directed to the rejection to claim 4 above, as they are rejected under the same rationale.
Regarding claim 5, Cawlfield/Guim Bernat/Venkatesh/Tanenbaum discloses The apparatus of claim 1, wherein to allocate the address range for the process among multiple memory pools, the memory controller is to dynamically distribute mapped addresses within the allocated address range among one or more of the multiple memory pools by an interleave of the allocated address range among the multiple memory pools (“The pooled memory control unit 410 may include a configuration interface 412. The configuration interface 412 for a memory pool may allow specifying memory physical address ranges to respective VNFs/services running on different compute resources and what read and/or write permissions the respective compute resources have. ... [0043] The pooled memory control unit 410 may include a load balancing and resiliency controller 414. The load balancing and resiliency controller 414 may perform load balancing among push and pull requests received from the NIC 312 based on certain criteria, e.g. QoS associated with the customer, traffic, etc. The load balancing and resiliency controller 414 may replicate or distribute push requests to multiple physical memory pools based on the configuration that the specific connection has (e.g. data may be replicated to multiple physical pools or distributed across multiple physical pools). [0044] The pooled memory control unit 410 may include a system address decoder 418. The system address decoder 418 may determine the physical memory pool to which a particular VNF or service is mapped in response to the push and pull requests from the NIC 312” [Guim Bernat paragraphs 42-44]. Specifying an address range is essentially equivalent to allocating an address range in this context. The system address decoder would be decoding address mappings, meaning the allocated addresses are mapped addresses. Furthermore, it would be obvious to have the memory controller perform these functions of the pooled memory control unit 410. For example, the NIC 312 is already disclosed to have similar functionalities (for example in Guim Bernat pars. 37-40), is comprised of the same four main components (see Guim Bernat Fig. 4 part numbers 402-408 and 412-418, and the pooled memory control unit 410 handles a plurality of memory devices (see the DIMMs in Guim Bernat Fig. 4) analogously to the claimed functionality of a memory controller handling a plurality of memory pools) based on service level parameters associated with the address range and performance capabilities of the multiple memory pools (“The load balancing and resiliency controller 414 may perform load balancing among push and pull requests received from the NIC 312 based on certain criteria, e.g. QoS associated with the customer, traffic, etc. The load balancing and resiliency controller 414 may replicate or distribute push requests to multiple physical memory pools based on the configuration that the specific connection has” [Guim Bernat par. 44]. Additionally, see the rejection to claim 1 above).
Regarding claims 15, 16, and 20, the applicant is directed to the rejection to claim 5 above, as they are rejected under the same rationale.
Regarding claim 6, Cawlfield/Guim Bernat/Venkatesh/Tanenbaum teaches the apparatus of claim 1, comprising one or more queues associated with one or more classes of service, wherein different queues of the one or more queues are to provide a class of service differentiation (“It is desired to have a communications interface with the following features: … separation of memory allocation into a plurality of separate queues” [Venkatesh col. 1 lines 58-64]. And “The advantage of maintaining multiple queues as shown in FIG. 7 is the ability to associate different quality of service to each queue” [Venkatesh col. 9 lines 11-12]) for issuance of memory access commands to the multiple memory pools (taught by Cawlfield; see the rejection to claim 1 above).
Regarding claim 7, the combination of Cawlfield/Guim Bernat/Venkatesh/Tanenbaum teaches the apparatus of claim 1, wherein the multiple memory pools are selected based on the performance capabilities of the multiple memory pools meeting the service level parameters associated with the address range (“For each virtual channel, the tenant may specify bandwidth requirements. In order to meet the bandwidth requirements, the POD manager or the resource manager may allocate multiple physical memory pools to a particular virtual channel or, alternatively or additionally, configure a quality of service (QoS) bandwidth level from a physical memory pool to meet the bandwidth needs of the particular virtual channel. In this case, push requests to those memory pools are not replicated but may be distributed across the multiple physical memory pools to achieve the required bandwidth” [Guim Bernat paragraph 34]. In the case of allocating multiple physical memory pools to meet a bandwidth quality of service need, the address range would be the entire address range of the pools, and the performance capabilities of the memory pools would be their available bandwidth).
Regarding claim 8, Cawlfield/Guim Bernat/Venkatesh/Tanenbaum discloses the apparatus of claim 1, comprising: a network interface device [Cawlfield network interface 932] and the multiple memory pools [see the rejection to claim 1 above], wherein the network interface device is to issue one or more memory access commands to the multiple memory pools (“If there are not sufficient resources available for the reservation request on host system 602, broker agent 632 broadcasts a call for bids to remote host system 650 and remote host system 660 through management network 640 and waits for offers from remote host system 650 and remote host system 660 with bids for migration of application 624 alone or LPAR 604, to the remote host system” [Cawlfield col. 13 lines 59-65]. Additionally, “The present invention may be performed in a variety of systems and combinations of systems, made up of functional components, such as the functional components described with reference to computer system 900 and may be communicatively connected to a network, such as network 902. In one example, each of host system 602, remote host system 650, and remote host system 660 may each implement one or more instances of functional components of computer system 900” [Cawlfield col. 17 lines 48-56]. Furthermore, “In the example, network interface 932 includes an adapter 934 for connecting computer system 900 to network 902 through a link. Although not depicted, network interface 932 may include additional software, such as device drivers, additional hardware and other controllers that enable communication” [Cawlfield col. 19 lines 28-33]. Wherein bidding for LPAR (logical partition) 604 would be a memory access request to a memory pool. The device of Cawlfield would be capable of performing this function for multiple pools (LPAR 604 is merely used as an example, Cawlfield discloses that there are other pools available for access, such as LPAR 614). The bidding over a network would happen via the network interface 932 issuing communications. See also the rejection to claim 1 above).
Regarding claim 9, Cawlfield/Guim Bernat/Venkatesh/Tanenbaum discloses the apparatus of claim 8, comprising one or more processors to execute the process, wherein the one or more processors are communicatively coupled to the memory controller circuitry (“The NIC 312 may include pull and push interfaces 406. The pull and push interfaces 406 may be used by the VNFs or services (running in a local server or FPGAs)” [Guim Bernat par. 40]. Wherein a local server or FPGAs would comprise one or more processors and would require a communicative coupling to the NIC 312 to be able to use the interfaces 406).
Regarding claim 10, Cawlfield/Guim Bernat/Venkatesh/Tanenbaum discloses The apparatus of claim 9, comprising a datacenter, (The plain language meaning of datacenter is “a large group of networked computer servers typically used by organizations for the remote storage, processing, or distribution of large amounts of data” (see the screen capture of an online dictionary below).
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The systems described in Cawlfield meet this definition, for example in “In the example, a virtualized computing environment 100 may include one or more types of virtualized environments, including, but not limited to, a workload distribution environment, a cloud computing environment, a grid environment, a cluster environment, and other types of computing environments” [Cawlfield col. 4 lines 47-52] and the invention is directed towards remote storage of large amounts of data (see claim 8)) wherein the datacenter includes the multiple memory pools and a server that is to execute an orchestrator (“Computer program code for carrying out operations of on embodiment of the invention may be written in any combination of one or more programming languages … The program code may execute entirely on the user's computer, such as computer system 900, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server” [Cawlfield col. 19 lines 12-23]. Hypervisor 120 can serve as an orchestrator (as the specification of the instant application describes in paragraph 37 “In some examples, orchestrator 320 can be implemented as a hypervisor or container manager”) and can run on a server) to select the multiple memory pools based on the performance capabilities of the multiple memory pools meeting the service level parameters associated with the address range (taught by Cawlfield; see the rejection to claim 1 above).
Regarding claim 23, Cawlfield/Guim Bernat/Venkatesh/Tanenbaum disclose The apparatus of claim 1, wherein: at least one of the multiple memory pools comprises dual inline memory modules (DIMMs), and (Guim Bernat Fig. 4 depicts two memory pools 320 and 330, each comprised of DIMMs) a first memory pool of the multiple memory pools has different request to response latency characteristics than a second memory pool of the multiple memory pools (“The pooled memory may include a (normal) pooled memory 320 and an accelerated pooled memory 330. The accelerated memory 330 is a memory with a hardware processor or capabilities for processing data (e.g. format conversion, etc.) before storing the data into the memory. The processing may be performed with a field programmable gate array (FPGA) or any hardware processor or accelerator” [Guim Bernat paragraph 24]. Wherein the accelerated memory pool would be able to fulfill a request faster due to the acceleration hardware, so it would have different request to response latency characteristics than the normal memory pool).
Regarding claim 25, Cawlfield/Guim Bernat/Venkatesh/Tanenbaum disclose The apparatus of claim 1, wherein the memory controller circuitry comprises a network interface controller to communicate with the multiple memory pools by Ethernet packets (“The NIC 312 may include pull and push interfaces 406. The pull and push interfaces 406 may be used by the VNFs or services (running in a local server or FPGAs) to push or pull data to and from different VNFs or services. The pull and push interfaces 406 may use the system address decoder 408 to decide to which physical memory pool or pools the pull or push requests need to be sent” [Guim Benat par. 40]. Wherein a network interface card is synonymous with a network interface controller. Additionally, Venkatesh teaches the application of Ethernet packets to a network interface: “Network systems typically have a media access controller (MAC), which receives packets from a physical media such as twisted pair copper wire in the case of IEEE 802.3 commonly known as copper ethernet, or from a wireless front end which converts RF signals into packets as in the case of IEEE standard 802.11, commonly known as wireless ethernet. The MAC provides the interface from a variety of physical interfaces and produces a single interface for receiving and transmitting packets” [Venkatesh col. 1 lines 19-27]. Therefore the claim would have been obvious to a person having ordinary skill in the art).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Cawlfield/Guim Bernat/Venkatesh/Tanenbaum, further in view of Khandual et al. (US 20200104264 A1), hereinafter referred to as Khandual.
Regarding claim 24, Cawlfield/Guim Bernat/Venkatesh/Tanenbaum disclose The apparatus of claim 1, wherein: the memory controller circuitry comprises a System Address Decoder (SAD) configured with an address map to indicate a target memory pool of the multiple memory pools to associate with a target memory address of the address range, (“The pooled memory control unit 410 may include a system address decoder 418. The system address decoder 418 may determine the physical memory pool to which a particular VNF or service is mapped” [Guim Bernat paragraph 44]. Additionally, see Guim Bernat system address decoder 408 of the NIC 312. Wherein a person having ordinary skill in the art would recognize the purpose of a SAD is to be configured with an address map to indicate a target memory pool of the multiple memory pools to associate with a target memory address of the address range, so it would have been obvious to have a SAD, as in Guim Bernat, be configured as such) at least one of the multiple memory pools comprises dual inline memory modules (DIMMs) (taught by Guim Bernat; see the rejection to claim 23 above) and comprises a second memory controller for the DIMMs, (Guim Bernat Fig. 4 depicts a pooled memory control unit 410 (which is synonymous with a memory controller) for each pool of DIMMs 320 and 330, in which the pools are downstream of platform 310/NIC 312) a first memory pool of the multiple memory pools has different request to response latency characteristics than a second memory pool of the multiple memory pools, and (taught by Guim Bernat; see the rejection to claim 23 above) the memory controller circuitry is to allocate the address range for the process among the first and second memory pools (see the rejection to claim 1 above).
Cawlfield/Guim Bernat/Venkatesh/Tanenbaum do not appear to explicitly disclose to achieve latency parameters of the service level parameters based on latency characteristics of both the first and second memory pools.
However, Khandual teaches to achieve latency parameters of the service level parameters based on latency characteristics of both the first and second memory pools (“If multiple attributes (e.g., a certain level of latency and a certain level of reliability) are requested, then these multiple attributes (block 612) are matched to a particular memory device that meets these multiple attributes” [Khandual paragraph 59]. Additionally, “one or more embodiments of the present invention present a system for allocating, mapping, and/or migrating (on-demand) applications to a memory system that aptly suits the applications needs. For example, power hungry workloads can use LPDDR (low power DDR) to save power; high performance workloads can be placed in DDR5 or even LLDRAM (low latency DRAM); and persistent applications can be placed in MRAM/PCM or NVDIMMs (non-volatile DIMMs) based on latency requirements” [Khandual paragraphs 35-36]. Wherein a memory device could be considered a memory pool.)
Cawlfield/Guim Bernat/Venkatesh/Tanenbaum and Khandual are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Cawlfield/Guim Bernat/Venkatesh/Tanenbaum and Khandual before him or her, to modify the apparatus of Cawlfield/Guim Bernat/Venkatesh/Tanenbaum to include the attributes of to achieve latency parameters of the service level parameters based on latency characteristics of both the first and second memory pools of Khandual because it will enhance apparatus efficiency.
The motivation for doing so would be “In light of heterogeneous memories and applications having various needs and system demands, one or more embodiments of the present invention present a system for allocating, mapping, and/or migrating (on-demand) applications to a memory system that aptly suits the applications needs.” [Khandual paragraph 35]. Matching applications to memory pools that suit their needs (service level parameters) including latency would improve the efficiency of those applications.
Therefore, it would have been obvious to combine Cawlfield/Guim Bernat/Venkatesh/Tanenbaum and Khandual to obtain the invention as specified in the instant claim.
Response to Arguments
Examiner thanks the applicant for their remarks of March 2, 2026. The remarks have been accepted and fully considered. However, the remarks are not fully persuasive.
In light of the amendments to the claims, the objection to claim 23 is withdrawn.
On pages 8-10 of the applicant’s remarks, applicant argues that the 103 rejections indicated in the previous Office Action should be withdrawn. The examiner respectfully disagrees. The arguments are moot in light of the updated 103 claim rejections above.
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Peterson et al. (US 20210318961 A1)
Relevant excerpt: “A compute platform coupled to one or more tiers of memory, such as remote pooled memory in a disaggregated environment executes memory transactions to access objects that are stored in the one or more tiers”
Conclusion
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/C.J.O./
Examiner, Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138
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