Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 14, 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Pub. No.: US 20170358591 A1), in view of Sotome et al. (US 20200273880 A1), hereinafter as Sotome.
Regarding claim 1, Kim discloses a semiconductor memory device (semiconductor integrated circuit device in Fig. 9) comprising: a stacked body (stack structure ST; see Fig. 9) in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked (the stack structure ST may include conductive layers 110 and insulating layers 115 alternately stacked; see Fig. 9 and [0020]); and a pillar (a vertical pillar comprising of memory layer 125, channel layer 130b, core pattern 135, and first capping layer 146; see Fig. 9) including a channel layer (channel layer 130b; see Fig. 9) extending in a stacking direction of the plurality of conductive layers in the stacked body (channel layer 130b extends vertically through the alternating conductive 110 and insulating 115 layers of the stack structure ST; see Fig. 9), a memory layer (memory layer 125; see Fig. 9) provided on a side surface of the channel layer (a channel layer 130 may be formed on the memory layer 125; see Fig. 9 and [0022]), and a cap layer provided on the channel layer (second capping layer 146 is formed on the channel layer 130b; see Fig. 9), the cap layer being connected to an upper layer wiring of the stacked body (Because a bit line or a wiring connected to a bit line may make contact with a channel layer and first capping layer, a contact resistance of a contact portion of the channel layer may be increased; see [0028]), wherein the channel layer extends into the stacked body at least from a height position of an uppermost conductive layer of the plurality of conductive layers (the channel layer 130b extends into the stack structure ST at least from a height position of the uppermost conductive layer 110, of the plurality of conductive layers; see Fig. 9), and a grain size of crystal contained in the channel layer is larger than a grain size of crystal contained in the cap layer (The first capping layer 140 may have a specific resistance relatively higher than a specific resistance of the channel layer 130, and a specific resistance of a material may be increased proportional to decreasing a grain size of the material. Thus, the channel layer may have a crystal grain size larger than the first capping layer; see [0027]), but fails to disclose the crystal of the channel layer contains at least one dopant of carbon, nitrogen, or oxygen, the dopant being diffused throughout the channel layer from a memory layer side to a side opposite of the memory layer, and a volume density of the dopant in the crystal of the channel layer is 3×10.sup.18 atoms/cm.sup.3 or more and 5×10.sup.20 atoms/cm.sup.3 or less.
Sotome discloses a semiconductor memory device (memory cell array 10; see Fig. 4) comprising: a crystal of the channel layer (channel film 44; see Fig. 4) contains at least one dopant of carbon, nitrogen, or oxygen (The impurities contained in the channel film 44 are selected from, for example, a group configuring carbon, phosphorus, boron, and germanium. The impurity contained in the channel film 44 is preferably carbon; see [0049]), the dopant being diffused throughout the channel layer from a memory layer side to a side opposite of the memory layer ([0048] discloses dopant concentration in both first surface 44a and surface 44b), and a volume density of the dopant in the crystal of the channel layer is 1×10.sup.20/cm.sup.3 or more and 1×10.sup.21/cm.sup.3 or less (the channel film 44 has a first region 44A and a second region 44B. The first region 44A is, for example, a region where a concentration of the impurities is higher than or equal to 1×10.sup.20/cm.sup.3 and lower than or equal to 1×10.sup.21/cm.sup.3; see [0046]).
Sotome does not directly disclose with sufficient specificity a volume density of the dopant in the crystal of the channel layer is 3×10.sup.18 atoms/cm.sup.3 or more and 5×10.sup.20 atoms/cm.sup.3 or less. However, Sotome does teach a channel film 44 that has a first region 44A where a concentration of the impurities is higher than or equal to 1×10.sup.20/cm.sup.3 and lower than or equal to 1×10.sup.21/cm.sup.3 (see [0046]). MPEP 2144.05 I states “In the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
The teachings of Kim are incorporated with the teachings of Sotome by substituting the conductive impurities of the polysilicon channel layer of Kim (channel layer 130; see Kim Fig. 6), with the carbon impurities concentration of the polysilicon channel film of Sotome (see Sotome Fig. 5 and [0046]).
In view of the teachings of Sotome, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Kim with the teachings of Sotome, wherein the combination discloses a semiconductor memory device comprising: a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked; and a pillar including a channel layer extending in a stacking direction of the plurality of conductive layers in the stacked body, a memory layer provided on a side surface of the channel layer, and a cap layer provided on the channel layer, the cap layer being connected to an upper layer wiring of the stacked body, wherein the channel layer extends into the stacked body at least from a height position of an uppermost conductive layer of the plurality of conductive layers, and a grain size of crystal contained in the channel layer is larger than a grain size of crystal contained in the cap layer, the crystal of the channel layer contains at least one dopant of carbon, nitrogen, or oxygen, the dopant being diffused throughout the channel layer from a memory layer side to a side opposite of the memory layer, and a volume density of the dopant in the crystal of the channel layer is 1×10.sup.20/cm.sup.3 or more and 1×10.sup.21/cm.sup.3 or less, because the carbon impurity reduces the thickness variation of the finished channel film during the channel film formation process by reducing the etch rate of the channel film during formation, compared to regions with no impurities (see Sotome [0068-0069]). Since the etch rate of the region with impurities is lower than the etch rate of the region with no impurities, a variation in the etch rate in the region with impurities is smaller than the variation in the etch rate in the region with no impurities, and the variation in the slimming amount of the channel film is reduced (see Sotome [0068]). Furthermore, carbon impurities have the added benefit of having minimal influence on the threshold voltage of a memory cell array and crystal grain size (see Sotome [0049] and [0065]); and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the conductive impurities of the polysilicon channel layer of Kim, with the carbon impurities concentration of the polysilicon channel layer of Sotome to obtain predictable results.
Regarding claim 14, Kim discloses a semiconductor memory device (semiconductor integrated circuit device in Fig. 8) comprising: a stacked body (stack structure ST; see Fig. 8) in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked (the stack structure ST may include conductive layers 110 and insulating layers 115 alternately stacked; see Fig. 8 and [0020]); and a pillar (a vertical pillar comprising of memory layer 125, channel layer 130a, core pattern 135, first capping layer 140a, and second capping layer 145; see Figure 1 below) including a semiconductor layer (semiconductor layer comprising of polysilicon channel layer 130a, polysilicon first capping layer 140a, and polysilicon second capping layer 145; see Figure 1 below, [0022], [0024-0025], and [0030]) extending in a stacking direction of the plurality of conductive layers in the stacked body (the semiconductor layer comprising of 130a, 140a, and 145 extends vertically through the alternating conductive 110 and insulating 115 layers of the stack structure ST in a stacking direction towards the semiconductor substrate 100; see Figure 1 below), wherein the semiconductor layer includes: a first region reaching from a position higher than an uppermost conductive layer of the plurality of conductive layers to an upper end portion of the pillar (first region comprising of 145 extends from a height position higher than the uppermost conductive layer 110 to the upper end of the vertical pillar; see Figure 1 below); and a second region extending at least from a height position of the uppermost conductive layer into the stacked body (the second region comprising of channel layer 130a extends at least from a height position of the uppermost conductive layer 110, into the stack structure ST towards the direction of the semiconductor substrate 100; see Figure 1 below), the second region having a grain size of crystal contained in the semiconductor layer larger than a grain size of the crystal in the first region (A crystallization of the channel layer 130a having a relatively larger grain size may be provided to the second capping layer 145 so that the second capping layer 145 may have a grain size larger than the second grain size. Consequently, the grain size of 145 may differ from the grain sizes of 140a and 130a such that 145 has a lower specific resistance than 140a and a greater specific resistance than 130a. Thus, the grain size of the second capping layer 145 is larger than the grain size of the first capping layer 140a and smaller than the grain size of the channel layer 130a; see Fig. 7 and [0031]), but fails to disclose the crystal of the second region contains at least one dopant of carbon, nitrogen, or oxygen, the dopant being diffused throughout the channel layer from a memory layer side to a side opposite of the memory layer, and a volume density of the dopant in the crystal of the second region is 3×10.sup.18 atoms/cm.sup.3 or more and 5×10.sup.20 atoms/cm.sup.3 or less.
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Sotome discloses a semiconductor memory device (memory cell array 10; see Fig. 4) comprising: a crystal of the channel layer (channel film 44; see Fig. 4) contains at least one dopant of carbon, nitrogen, or oxygen (The impurities contained in the channel film 44 are selected from, for example, a group configuring carbon, phosphorus, boron, and germanium. The impurity contained in the channel film 44 is preferably carbon; see [0049]), the dopant being diffused throughout the channel layer from a memory layer side to a side opposite of the memory layer ([0048] discloses dopant concentration in both first surface 44a and surface 44b), and a volume density of the dopant in the crystal of the channel layer is 1×10.sup.20/cm.sup.3 or more and 1×10.sup.21/cm.sup.3 or less (the channel film 44 has a first region 44A and a second region 44B. The first region 44A is, for example, a region where a concentration of the impurities is higher than or equal to 1×10.sup.20/cm.sup.3 and lower than or equal to 1×10.sup.21/cm.sup.3; see [0046]).
Sotome does not directly disclose with sufficient specificity a volume density of the dopant in the crystal of the channel layer is 3×10.sup.18 atoms/cm.sup.3 or more and 5×10.sup.20 atoms/cm.sup.3 or less. However, Sotome does teach a channel film 44 that has a first region 44A where a concentration of the impurities is higher than or equal to 1×10.sup.20/cm.sup.3 and lower than or equal to 1×10.sup.21/cm.sup.3 (see [0046]). MPEP 2144.05 I states “In the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
The teachings of Kim are incorporated with the teachings of Sotome by substituting the conductive impurities of the polysilicon channel layer of Kim, with the carbon impurities concentration of the polysilicon channel layer of Sotome.
In view of the teachings of Sotome, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Kim with the teachings of Sotome, wherein the combination discloses a semiconductor memory device comprising: a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked; and a pillar including a semiconductor layer extending in a stacking direction of the plurality of conductive layers in the stacked body, wherein the semiconductor layer includes: a first region reaching from a position higher than an uppermost conductive layer of the plurality of conductive layers to an upper end portion of the pillar; and a second region extending at least from a height position of the uppermost conductive layer into the stacked body, the second region having a grain size of crystal contained in the semiconductor layer larger than a grain size of the crystal in the first region, the crystal of the second region contains at least one dopant of carbon, nitrogen, or oxygen, the dopant being diffused throughout the channel layer from a memory layer side to a side opposite of the memory layer, and a volume density of the dopant in the crystal of the channel layer is 1×10.sup.20/cm.sup.3 or more and 1×10.sup.21/cm.sup.3 or less, because the carbon impurity reduces the thickness variation of the finished channel film during the channel film formation process by reducing the etch rate of the channel film during formation, compared to regions with no impurities (see Sotome [0068-0069]). Since the etch rate of the region with impurities is lower than the etch rate of the region with no impurities, a variation in the etch rate in the region with impurities is smaller than the variation in the etch rate in the region with no impurities, and the variation in the slimming amount of the channel film is reduced (see Sotome [0068]). Furthermore, carbon impurities have the added benefit of having minimal influence on the threshold voltage of a memory cell array and crystal grain size (see Sotome [0049] and [0065]); and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the conductive impurities of the polysilicon channel layer of Kim, with the carbon impurities concentration of the polysilicon channel layer of Sotome to obtain predictable results.
Regarding claim 21, the combination of Kim and Sotome does not disclose the volume density of the dopant in the crystal of the channel layer is 3 x 1018 atoms/cm3 or more and less than 1 x 1020 atoms/cm3. However, Sotome does teach a channel film 44 that has a first region 44A where a concentration of the impurities is higher than or equal to 1×10.sup.20/cm.sup.3 and lower than or equal to 1×10.sup.21/cm.sup.3 (see [0046]). MPEP 2144.05 I states “a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985)”).
Regarding claim 22, the combination of Kim and Sotome does not disclose the volume density of the dopant in the crystal of the channel layer is 3 x 1018 atoms/cm3 or more and less than 1 x 1020 atoms/cm3. However, Sotome does teach a channel film 44 that has a first region 44A where a concentration of the impurities is higher than or equal to 1×10.sup.20/cm.sup.3 and lower than or equal to 1×10.sup.21/cm.sup.3 (see [0046]). MPEP 2144.05 I states “a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985)”).
Claims 2 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Sotome, and further in view of Furumura et al. (Y. Furumura et al 1986 J. Electrochem. Soc. 133 379), hereinafter as Furumura.
Regarding claim 2, the combination of Kim and Sotome discloses the semiconductor memory device of claim 1, but fails to disclose wherein an average grain size of the crystal in the channel layer is 100 nm or more.
Furumura discloses wherein an average grain size of the crystal of a selective polysilicon is 100 nm or more (grain size of the grown film was about 0.3 um; see page 382, column 8, lines 38-41).
The teachings of Kim are incorporated with the teachings of Furumura by substituting the average grain size of the polysilicon crystal in the channel layer of Kim and Sotome, with the 0.3 um grain size of the selectively grown polysilicon of the teachings of Furumura.
In view of the disclosures of Furumura, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of the combination of Kim and Sotome with the teachings of Furumura, wherein the combination discloses wherein an average grain size of the crystal in the channel layer is 100 nm or more, because this results in higher on-state current and faster program speed due to the different local electric field induced by an oxide valley at an interface between the polysilicon channel layer and a core silicon oxide dielectric layer. Additionally, a channel layer with polysilicon average crystal grain size of 100 nm or more has a lower interface trap density; and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of average grain size of the polysilicon crystal of the channel layer of the device of Kim and Sotome, with the observed grain size of the polysilicon crystal of Furumura to obtain predictable results.
Regarding claim 15, the combination of Kim and Sotome discloses the semiconductor memory device of claim 1, but fails to disclose wherein an average grain size of the crystal in the channel layer is 100 nm or more.
Furumura discloses wherein an average grain size of the crystal of a selective polysilicon is 100 nm or more (grain size of the grown film was about 0.3 um; see page 382, column 8, lines 38-41).
The teachings of Kim are incorporated with the teachings of Furumura by substituting the average grain size of the polysilicon crystal in the channel layer of Kim and Sotome, with the 0.3 um grain size of the selectively grown polysilicon of the teachings of Furumura.
In view of the disclosures of Furumura, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of the combination of Kim and Sotome with the teachings of Furumura, wherein the combination discloses wherein an average grain size of the crystal in the channel layer is 100 nm or more, because this results in higher on-state current and faster program speed due to the different local electric field induced by an oxide valley at an interface between the polysilicon channel layer and a core silicon oxide dielectric layer. Additionally, a channel layer with polysilicon average crystal grain size of 100 nm or more has a lower interface trap density; and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of average grain size of the polysilicon crystal of the channel layer of the device of Kim and Sotome, with the observed grain size of the polysilicon crystal of Furumura to obtain predictable results.
Claims 5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Sotome, and further in view of Kwon et al. (Pub. No.: US 20200194441 A1), hereinafter as Kwon.
Regarding claim 5, the combination of Kim and Sotome discloses the semiconductor memory device of claim 1, but fails to disclose wherein the crystal of the cap layer contains at least one dopant of arsenic and or phosphorus.
Kwon discloses a semiconductor memory device (a cell array of a 3D NVM device in Fig. 4H) wherein the crystal of the cap layer (capping layer 145; see Fig. 4H) contains at least one dopant of arsenic and or phosphorus (conductive ions may be implanted into the capping layer 145. When the drain selection transistor may include an NMOS transistor, the conductive ions may include N type impurities such as Phosphorus ions or Arsenic ions; see Fig. 4H and [0054]).
The teachings of the combination of Kim and Sotome are incorporated with the teachings of Kwon by using the known technique of doping the capping layer with at least one N type impurity such as phosphorus or arsenic ions, as taught by Kwon, to dope the cap layer of the combination of Kim and Sotome (first capping layer 146; see Kim Fig. 9), so that the cap layer of the combined device has N-type impurities such as phosphorus or arsenic ions.
In view of the disclosures of Kwon, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kim and Sotome with the teachings of Kwon, wherein the combination discloses the semiconductor memory device according to claim 1, wherein the crystal of the cap layer contains at least one dopant of arsenic and or phosphorus, because N type impurities in the cap layer allows the cap layer to operate as the junction region. For example, the cap layer can operate as the drain of the drain selection transistor (see Kwon 0054); and the combination is an application of a known technique to a known device ready for improvement to yield predictable results – applying the technique taught by Kwon of doping N-type impurities such as phosphorus or arsenic into the cap layer of Kim and Sotome to allow the cap layer to operate as the junction region.
Regarding claim 18, the combination of Kim and Sotome discloses the semiconductor memory device of claim 14, but fails to disclose wherein the crystal of the first region contains at least one dopant of arsenic and or phosphorus.
Kwon discloses a semiconductor memory device (a cell array of a 3D NVM device in Fig. 4H) wherein the crystal of the first region (capping layer 145; see Fig. 4H) contains at least one dopant of arsenic and or phosphorus (conductive ions may be implanted into the capping layer 145. When the drain selection transistor may include an NMOS transistor, the conductive ions may include N-type impurities such as Phosphorus ions or Arsenic ions; see Fig. 4H and [0054]).
The teachings of the combination of Kim and Sotome are incorporated with the teachings of Kwon by using the known technique of doping the capping layer with at least one N type impurity such as phosphorus or arsenic ions, as taught by Kwon, to dope the first region of the combination of Kim and Sotome (first region comprises of a portion of 140a extending from a height position higher than the uppermost conductive layer 110 to the upper surface of 145, which is the upper end of the pillar; see Figure 2 below), so that the first region of the combined device has N-type impurities such as phosphorus or arsenic ions.
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Figure 2
In view of the disclosures of Kwon, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kim and Sotome with the teachings of Kwon, wherein the combination discloses the crystal of the first region contains at least one dopant of arsenic and or phosphorus, because N type impurities in the first region allows the first region to operate as the junction region. For example, the first region can operate as the drain of the drain selection transistor (see Kwon 0054); and the combination is an application of a known technique to a known device ready for improvement to yield predictable results – applying the technique taught by Kwon of doping N-type impurities such as phosphorus or arsenic into the first region of Kim and Sotome to allow the first region to operate as the junction region.
Claims 6, 7, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Sotome, and further in view of Shimomura et al. (Pub. No.: US 20230069307 A1), hereinafter as Shimomura.
Regarding claim 6, the combination of Kim and Sotome discloses the semiconductor memory device of claim 1, wherein the pillar includes a core material having insulating characteristics extending in the stacking direction (the pillar comprising of memory layer 125, channel layer 130b, first capping layer 146, and core pattern 135 includes a core pattern 135 that can be formed of an insulating material such as polisilazane, extending in the stacking direction towards the semiconductor substrate 100; see Fig. 9 and [0023]), but fails to disclose a layer thickness of the channel layer sandwiched between the memory layer and the core material is 5 nm or less.
Shimomura discloses a semiconductor memory device wherein a layer thickness of the channel layer (vertical semiconductor channel 60; see Fig. 13D) sandwiched between the memory layer and the core material (vertical semiconductor channel 60 is sandwiched between memory film 50 and dielectric core 62; see Fig. 13D) is 2 nm to 10 nm (The thickness of the semiconductor channel material layer 60L may be in a range from 2 nm to 10 nm; see Fig. 13C and [0128]).
Shimomura does not directly disclose with sufficient specificity a layer thickness of the channel layer sandwiched between the memory layer and the core material is 5 nm or less. However, Shimomura does teach the thickness of the semiconductor channel material layer 60L may be in a range from 2 nm to 10 nm (see [0128]). MPEP 2144.05 I states “In the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
The teachings of the combination of Kim and Sotome are incorporated with the teachings of Shimomura by substituting the channel layer in the combination of Kim and Sotome (channel layer 130b; see Kim Fig. 9) with the channel layer in the device of Shimomura (vertical semiconductor channel 60; see Shimomura Fig. 13D), so that the combined device has a channel layer thickness that is 5 nm or less.
In view of the disclosures of Shimomura, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of the combination of Kim and Sotome with the teachings of Shimomura, wherein the combination discloses wherein the pillar includes a core material having insulating characteristics extending in the stacking direction, and a layer thickness of the channel layer sandwiched between the memory layer and the core material is 2 nm to 10 nm, because a channel layer with a layer thickness below 5 nm increases gate capacitance, increases channel control, and reduces the occurrence of short channel effects; and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the channel layer in the teachings of Kim and Sotome, with the channel layer of the teachings of Shimomura to obtain predictable results.
Regarding claim 7, the combination of Kim, Sotome, and Shimomura discloses the semiconductor memory device according to claim 6, wherein a height position of an upper end portion of the core material (height position of upper end portion of core pattern 135; see Fig. 9) is different from a height position of an upper end portion of the channel layer (height of upper end portion of core pattern 135 is different from height position of upper end portion of channel layer 130b; see Fig. 9).
Regarding claim 19, the combination of Kim and Sotome discloses the semiconductor memory device according to claim 14, wherein the pillar includes a core material having insulating characteristics extending in the stacking direction (the pillar comprising of memory layer 125, channel layer 130b, first capping layer 146, and core pattern 135 includes a core pattern 135 that can be formed of an insulating material such as polisilazane, extending in the stacking direction towards the semiconductor substrate 100; see Fig. 9 and [0023]), but fails to disclose and a layer thickness of the semiconductor layer covering a side surface of the core material is 5 nm or less.
Shimomura discloses a semiconductor memory device wherein a layer thickness of the channel layer (vertical semiconductor channel 60; see Fig. 13D) sandwiched between the memory layer and the core material (vertical semiconductor channel 60 is sandwiched between memory film 50 and dielectric core 62; see Fig. 13D) is 2 nm to 10 nm (The thickness of the semiconductor channel material layer 60L may be in a range from 2 nm to 10 nm; see Fig. 13C and [0128]).
Shimomura does not directly disclose with sufficient specificity a layer thickness of the channel layer sandwiched between the memory layer and the core material is 5 nm or less. However, Shimomura does teach the thickness of the semiconductor channel material layer 60L may be in a range from 2 nm to 10 nm (see [0128]). MPEP 2144.05 I states “In the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
The teachings of the combination of Kim and Sotome are incorporated with the teachings of Shimomura by substituting the channel layer in the combination of Kim and Sotome (channel layer 130b; see Kim Fig. 9) with the channel layer in the device of Shimomura (vertical semiconductor channel 60; see Shimomura Fig. 13D).
In view of the disclosures of Shimomura, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of the combination of Kim and Sotome with the teachings of Shimomura, wherein the combination discloses wherein the pillar includes a core material having insulating characteristics extending in the stacking direction, and a layer thickness of the channel layer sandwiched between the memory layer and the core material is 2 nm to 10 nm, because a channel layer with a layer thickness below 5 nm increases gate capacitance, increases channel control, and reduces the occurrence of short channel effects; and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the channel layer in the teachings of Kim and Sotome, with the channel layer of the teachings of Shimomura to obtain predictable results.
Regarding claim 20, the combination of Kim, Sotome, and Shimomura discloses the semiconductor memory device according to claim 19, wherein a height position of an upper end portion of the core material (height position of upper end portion of core pattern 135; see Fig. 8) is different from a height position of a boundary portion between the first region and the second region (the height position of the boundary between the first region 145 and the second region 130a is different from the height position of the core pattern 135; see Figure 2 above).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Sotome and Shimomura, and further in view of Kwon.
Regarding claim 8, the combination of Kim, Sotome, and Shimomura discloses the semiconductor memory device of claim 6, but fails to disclose wherein an upper end portion of a core material protrudes into a cap layer.
Kwon discloses a semiconductor memory device wherein the upper end portion of the core material (gap-filling insulation layer 140; see Fig. 4H) protrudes into the cap layer (the gap-filling insulation layer 140 protrudes into the capping layer 145; see Fig. 4H).
The teachings of the combination of Kim, Sotome, and Shimomura are incorporated with the teachings of Kwon by substituting the configuration of the pillar in the combination of Kim, Sotome, and Shimomura, in which the core material does not protrude into the cap layer (core pattern 135 does not protrude into cap layer 146; see Kim Fig. 9), with the configuration of Kwon in which the core material protrudes into the cap layer (the gap-fill insulating layer 140 protrudes into the capping layer 145; see Kwon Fig. 4H).
In view of the disclosures of Kwon, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of the combination of Kim, Sotome, and Shimomura with the teachings of Kwon, wherein the combination discloses an upper end portion of a core material protrudes into a cap layer, because core material protrusion into the cap layer allows for enhanced structural stability of the gate structure during high-temperature fabrication, and also reduces gate capacitance and lower parasitic capacitance during device operation; and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the gate capping layer configuration in the teachings of Kim, Sotome, and Shimomura, with the gate capping layer configuration of the teachings of Kwon to obtain predictable results.
Claims 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Sotome, and further in view of Lee et al. (Pub. No.: US 20220254805 A1), hereinafter as Lee.
Regarding claim 9, the combination of Kim and Sotome discloses the semiconductor memory device according to claim 1, but fails to disclose further comprising: a conductive film extending in a direction along the plurality of conductive layers below the stacked body, wherein a lower end portion of the pillar extends to the conductive film.
Lee discloses a semiconductor memory device (semiconductor memory device in Fig. 4) further comprising: a conductive film (third source layer SL3, formed of a conductive material; see Fig. 4 and [0057]) extending in a direction along the plurality of conductive layers below the stacked body (third source layer SL3 extends in a D1 direction along the plurality of conductive layers 104 below the stacked body; see Fig. 4), wherein a lower end portion of the pillar extends to the conductive film (the lower end portions of the channel structure CH extend to the third source layer SL3; see Fig. 4).
The teachings of the combination of Kim and Sotome are combined with the teachings of Lee by combining the channel layer grain size, the cap layer grain size, and the conductive impurities concentration and impurities type of the channel layer as taught by Kim and Sotome, with the device of Lee, so that the combined device has a conductive film extending in a direction along the plurality of conductive layers below a stacked body (third source layer SL3 extending under the stacked structure in a D1 direction; see Lee Fig. 4), wherein a lower end portion of the pillar extends to the conductive film (a lower end portion of the channel structure CH extends to the third source layer SL3; see Lee Fig. 4). The combination also ensures the memory layer (memory layer 120; see Lee Fig. 4) does not cover the portion of the channel layer where the channel layer is electrically connected to the conductive film extending in a direction along the plurality of conductive layers below the stacked body, and the channel layer in the combined device (channel layer 122 in the channel structure CH; see Lee Fig. 4) has the grain size and conductive impurity type and concentration from the teachings of Kim and Sotome.
In view of the disclosures of Lee, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of the combination of Kim and Sotome with the teachings of Lee, wherein the combination discloses further comprising: a conductive film extending in a direction along the plurality of conductive layers below the stacked body, wherein a lower end portion of the pillar extends to the conductive film, because this configuration allows the channel layer to serve as the junction region of the source selection transistor (see Lee [0078]), since the junction region is formed through diffusion from the source layer SL (see Lee [0084]); and the combination is combining prior art elements according to known methods to yield predictable results – combining the channel layer grain size, the cap layer grain size, and the conductive impurities concentration and impurities type of the channel layer as taught by Kim and Sotome, with the device of Lee to yield the predictable result of the channel layer serving as the junction region of the source selection transistor.
Regarding claim 10, the combination of Kim, Sotome, and Lee discloses the semiconductor memory device according to claim 9, wherein the channel layer is connected to the conductive film at the side surface (The third source layer SL3 may be electrically coupled to a channel layer 122 of each of the channel structures CH; see Lee Fig. 4 and [0055]).
Regarding claim 11, the combination of Kim, Sotome, and Lee discloses the semiconductor memory device according to claim 10, wherein the memory layer (memory layer 120; see Lee Fig. 4) covers a lower end portion of the channel layer (the memory layer 120 covers the lower end portion of the channel layer 122; see Lee Fig. 4).
Regarding claim 12, the combination of Kim, Sotome, and Lee discloses the semiconductor memory device according to claim 10, wherein the memory layer (memory layer 120; see Lee Fig. 4) covers the side surface and a lower end portion of the channel layer excluding a predetermined depth position in the conductive film (memory layer 120 covers the side surface and lower end portion of the channel layer 122, but does not cover a predetermined depth position where the channel layer 122 is electrically connected to the third source layer SL3; see Lee Fig. 4).
Regarding claim 13, the combination of Kim and Sotome discloses the semiconductor memory device according to claim 1, but fails to disclose further comprising: a separation layer that penetrates at least the uppermost conductive layer of the plurality of conductive layers, extends in a first direction along the plurality of conductive layers, and separates the penetrated conductive layer in a second direction intersecting the first direction.
Lee discloses a semiconductor memory device comprising: a separation layer (isolation layer 106; see Fig. 4) that penetrates at least the uppermost conductive layer of the plurality of conductive layers (isolation layer 106 penetrates the uppermost conductive layer 104 of the plurality of conductive layers in the stacked structure; see Fig. 4 and [0068]), extends in a first direction along the plurality of conductive layers (isolation layer 106 extends in a D2 direction along the plurality of conductive layers 104; see Fig. 4), and separates the penetrated conductive layer in a second direction intersecting the first direction (isolation layer 106 separates the penetrated conductive layers 104 in a D1 direction, intersecting the D2 direction; see Fig. 4).
The teachings of the combination of Kim and Sotome are combined with the teachings of Lee by forming the separation layer of Lee (isolation layer 106; see Lee Fig. 4) between the vertical pillars in the combined device of Kim and Sotome (vertical pillars comprising of core pattern 135, first capping layer 146, memory layer 125, and channel layer 130b; see Kim Fig. 9), so that the separation layer penetrates at least the uppermost conductive layer (conductive layer 110; see Kim Fig. 9) and extends in a first direction along the plurality of conductive layers and separates the conductive layers in a second direction that is transverse to the first direction (see Figure 3 below).
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Figure 3
In view of the disclosures of Lee, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of the combination of Kim and Sotome with the teachings of Lee, wherein the combination discloses further comprising: a separation layer that penetrates at least the uppermost conductive layer of the plurality of conductive layers, extends in a first direction along the plurality of conductive layers, and separates the penetrated conductive layer in a second direction intersecting the first direction, because a separation layer separating a gate conductive layer located on the uppermost layer in each gate stack can help define first and second drain selection lines (see Lee [0068]). Additionally, the separation layer helps to reduce unwanted coupling and parasitic capacitance; and the combination is combining prior art elements according to known methods to yield predictable results – combining the isolation layers 106 of the teachings of Lee with the combined device of the teachings of Kim and Sotome to yield the predictable result of defining drain selection lines, reducing unwanted coupling, and reducing parasitic capacitance.
Response to Arguments
Applicant's arguments filed July 22, 2025 have been fully considered but they are not persuasive. It is urged, in pages 7 and 8 of the remarks, that neither Kim nor Sotome, either alone or in combination, teach the dpopant being diffused throughout the channel layer from a memory layer side to a side opposite of the memory layer in Sotome. However, as mentioned in paragraph [0048] of Sotome, it discloses the concentration of impurities in the first surface 44a of the channel film 44 is higher than the concentration of impurities in the second surface 44b. It further discloses in the channel film 44, for example, the concentration of impurities gradually decreases from the first surface 44a to the second surface 44b. Therefore, Sotome does show the dopant being diffused throughout the channel layer 44 from a memory layer side (right side of film [44]) to a side opposite of the memory layer (left side of film [44]). The combination of Kim and Sotome shows all the claimed elements as claimed in amended claims 1 and 14, and new claims 21 and 22. The remaining references (Furumura, Kwon, Shimomura, Lee), in combination with Kim and Sotome, show all the limitations of the pending dependent claims (2, 5-13, 15, and 18-20).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818