DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7,10,11,14,17,18, 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sankaranarayanan (patent application publication No. 2016/0125263) in view of Jiang (patent No 6,078,941).
Sankaranarayanan taught the invention substantially as claimed including (as to claim 1) An apparatus, comprising: a processor (100) to receive a single processor instruction [Vector Dot Product Mask Positive Negative (VDOTPMPN)] which comprises an opcode, a mask operand, and one or more operands to identify four or more source inputs
to perform arithmetic operations that include at least multiplication operations, addition operations, and subtraction operations (e.g., see fig. 1 and paragraph 0054); and circuitry coupled to the processor to cause the processor to perform a fused multiple multiplication and addition-subtraction operation on four or more source inputs in response to a single processor instruction to produce one or more results (e.g., see figs. 11,29,30 and paragraphs 0127-0131)[note the execution of the Vector Dot Product Mask Positive Negative (VDOTPMPN) instruction where the mask is either 1,0, or -1 provides this limitation and Sankaranarayanan disclosed at paragraph 0128 ” the VDOTPMPN includes a mask operand that is 1,0,or -1 for each vector element. Proper use of this mask enables control over the number of terms and selection of addition or subtraction”].
Sankaranarayanan did not expressly detail the mask is to indicate that the respective portions of the respective two multi-bit intermediate values are to comprise: only respective lower portions of the respective two multi-bit intermediate values; or only respective upper portions of the respective two multi-bit intermediate values. Jiang however taught this limitation (e.g., see fig. 5 and col. 5, line 26-col. 6, line 35).
It would have been obvious to one of ordinary skill in the art to combine the teachings of Sankaranarayanan and Jiang. Both references were directed toward the problems of selectively performing multiplication and addition/subtraction operation(s) in a data processor. One of ordinary skill would have been motivated to incorporate the Jiang teaching of performing the addition or subtraction on only low or high portions of the data at least to support the processing of differing size data without having to convert the data which would increase throughput.
Due to the similarities between claims 1 and 10 and 17; claims 10 and 17 are rejected for the same reasons as claim 1 above. As to the further limitations of claim 10, Sankaranarayanan taught decode circuitry to decode a single instruction (113), the single instruction to include respective fields for one or more source operands, one or more destination operands, and an opcode, the opcode to indicate execution circuitry is to perform a fused multiple multiplication and addition- subtraction operation (e.g., see figs. 11,13 and paragraphs 0089-0095,0102 and 0113 and 0127).
As the further limitations of claim 17 Sankaranarayanan taught fetching instruction (e.g see figs. 1,11) retrieving data and scheduling execution of the instruction (dispatch and decode phase and streaming engine 125 e.g., see fig. 11 and paragraphs 0073 and 0079) the processor to perform the FMMAS operation [Vector Dot Product Mask Positive Negative (VDOTPMPN)] comprises the processor to:
perform multiplication operations each to generate, based on a respective two source inputs of the four or more source inputs (2901,2902 ,2903, 2908), a different respective one of multiple multi-bit intermediate values; and perform one or more arithmetic operations each based on respective portions of a respective two multi-bit intermediate values of the multiple multi-bit intermediate values; for each arithmetic operation of the one or more arithmetic operations: a respective value of the mask operand is to identify that the arithmetic operation is to be a respective one of an addition operation or a subtraction operation; and the opcode or the mask operand (e.g., see fig. 29 and paragraph 0127 where Sankaranarayanan discloses “An example of a typical instruction that supports selective horizontal addition is the VDOTPMPN instruction supported by C7000 DSP. VDOTPMPN stands for Vector DOT Product Mask Positive Negative. This instruction supports addition of elements within a vector. The mask maybe used to specify which elements within the vector need to be added to produce each element in the resultant sum vector’.
As to claim 2 Sankaranarayanan taught The apparatus of claim 1, wherein the single processor instruction (VDOTPMPN) indicates two or more sets of the four or more source inputs for each of the multiplication operations the processor is to perform the a multiplication operation between a respective argument of each set of the two or more sets (e.g., see figs. 29,31 and paragraphs 0105-0107 and 0127- 0128)[note the data size indicated by the instruction includes size(s) that for instruction execution two or more of four or more sets such as a quad word (128) for vectors A and B (see paragraph 0128).
As to claim 3 Sankaranarayanan and Jiang taught The apparatus of claim 2, Sankaranarayanan taught wherein the opcode is to identify that, for each arithmetic operation of the one or more arithmetic operations, the respective portions of the respective two multi-bit intermediate values (VDOTPMPN) (e.g., see paragraphs 0127-0129 and fig. 29)[note the mask operand field value indicates whether an addition or subtraction of the products are performed] .
As to claims 4,12,19 Sankaranarayanan and Jiang taught The apparatus of claim 1, Sankaranarayanan taught wherein, in response to the single processor instruction, the circuitry is further to cause the processor to: perform a first operation (2901-2908) indicated by the single processor instruction to multiply respective first and second arguments of first and second input sources (2901,2902) indicated by the single processor instruction to produce a first intermediate value (e.g., see paragraphs 0127-0129 and fig. 29); perform a second operation indicated by the single processor instruction to multiply respective third and fourth arguments of third and fourth input source (2903, 2908) indicated by the single processor instruction to produce a second intermediate value (e.g., see paragraphs 0127-0129 and fig. 29); and perform a third operation indicated by the single processor instruction to one of add and subtract a first portion (2911,2912) of the first intermediate value and a second portion (2913,2918) of the second intermediate value to produce a result of the one or more results (e.g., see paragraphs 0127-0129 and 0133-0134 and fig. 29). Sankaranarayanan taught
The mask is to comprise bits which each correspond to a different one of the one or more arithmetic operations; each of the first bits is to specify that the corresponding arithmetic operation is to calculate one of: sum of the respective of the respective portions of the multi-bit intermediate values or a difference between the respective portions of the respective two multi-bit intermediate values (e.g., see paragraphs 0127-0129 and fig. 29); (e.g., see paragraphs 0127-0129 and 0133-0134 and fig. 29).
As to claims 5,11,18 Sankaranarayanan and Jiang taught The apparatus of claim 1, Sankaranarayanan taught wherein, in response to the single processor instruction, the circuitry is further to cause the processor to: store a result of the FMMAS operation in a location indicated by the single processor instruction (e.g., see paragraph 0056 and 0092)[note Sankaranarayanan disclosed at paragraph 0056 “the result may be written into an instruction specified register’ ].
As to claims 6,13,20 Sankaranarayanan and Jiang taught The apparatus of claim 1, Sankaranarayanan taught wherein the single processor instruction includes a mask operand that indicates whether the third operation is an addition operation or a subtraction operation (e.g., see figs. 11,29,30 and paragraphs 0127-0131) [note the execution of the Vector Dot Product Mask Positive Negative (VDOTPMPN) instruction that includes a mask operand where the mask operand is either 1,0, or -1 provides this limitation].
As to claims 7,14,21 Sankaranarayanan and Jiang taught The apparatus of claim 1, Sankaranarayanan taught wherein the single processor instruction includes a mask operand (e.g., see paragraph 0127) that indicates first portion of the first intermediate value and the second portion of the second intermediate value (e.g., see fig. 29 and paragraph 0127 where Sankaranarayanan discloses “An example of a typical instruction that supports selective horizontal addition is the VDOTPMPN instruction supported by C7000 DSP. VDOTPMPN stands for Vector DOT Product Mask Positive Negative. This instruction supports addition of elements within a vector. The mask maybe used to specify which elements within the vector need to be added to produce each element in the resultant sum vector’. And see paragraph 0130 where Sankaranarayanan discloses “ at paragraph [0131] Process 3000 then calculates row sums using a VDOTPMPN instruction in block 3004. This process is illustrated in FIG. 31 for an example of eight element vector length for a block sum of a 3x3 block. Vector 3101 illustrates eight elements packed in the vector register |.sub.aa, |.sub.ab .. . |.sub.ah. Each element of resultant vector 3110 is the sum of three elements of vector 3101. As illustrated in FIG. 31: element H.sub.ab is the sum of I.sub.aa, |.sub.ab and |.sub.ac; element H.sub.ac is the sum of I.sub.ab, |.sub.ac and |.sub.ad; element H.sub.ad is the sum of |.sub.ac, I.sub.ad and |.sub.ae; element H.sub.ae is the sum of |.sub.ad, |.sub.ae and I.sub.af; element H.sub.af is the sum of I.sub.ae, |.sub.af and |.sub.ag; and element H.sub.ag is the sum of I.sub.af, |.sub.ag and I.sub.an. As required each row sum spans the three column image size” .
Jiang taught wherein for each arithmetic operation of the one or more arithmetic operations, another respective value of the mask operand identifies that the respective portions of the respective two multi-bit intermediate values are to comprise: only the respective lower portions of the respective two multi-bit intermediate; or only the respective upper portions of the respective two multi-bit intermediate values (e.g., see figs. 5 and col. 5, lines 26-col. 6, line 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8,9,15,16,22,23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sankaranarayanan and Jiang as applied to claim 4 above, and further in view of Lupon (ACM paper entitled Speculative Hardware/Software Co-Designed Floating-Point Multiply-Add Fusion).
As to claims 8,15,22 Sankaranarayanan and Jiang taught The apparatus of claim 4, Lupon taught wherein, in response to the single processor instruction, the circuitry (e.g., see fig. 2) (overflow detector) is further to cause the processor to: provide an overflow indication to the processor if any of the multiple-bit intermediate values is larger than a threshold value (e.g., see section 3.2 An FMA Unit with Intermediate rounding, CMA execution right column on page 627- left column on page 628).
It would have been obvious to one of ordinary skill in the art to combine the teachings of Sankaranarayanan and Lupon. Both references were directed toward the problems of performing fused multiply add operation in a data processor. One of ordinary skill in the art would have been motivated to incorporate the Lupon teachings of detecting overflow at least to enable the system to know when the data was size that would, when operated on, yield an inaccurate result so corrective operations could be performed to ensure the resulting calculation would have been correct.
As to claim 9,16,23 (as to claim is best understood considering the conventional meaning of underflow where the number is smaller than could be represented and that are very near zero) Sankaranarayanan and Jiang taught The apparatus of claim 1, Lupon taught wherein, in response to the single processor instruction, the circuitry is further to cause the processor to: provide an underflow indication to the processor if any of the first intermediate value and the second multiple multi-bit intermediate values is less than zero (e.g., see section 3.2 An FMA Unit with Intermediate rounding, CMA execution right column on page 627)[note the detection of product exponent underflow corresponds to this limitation].
Response to Arguments
The change in scope of the amended claims has necessitated a new search.
Applicant’s arguments, see remarks , filed 07/01/2025, with respect to the rejection(s) of claim(s) 1-11,14-18,21-23 under 35 U.S.C.103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Sankaranarayanan and Jiang. And another rejection in view of Sankaranarayanan and Jiang and Lupon,
The limitations in the claims previously rejected under of the 35 U.S.C 103 are maintained and the added limitations of the claims are rejected further in view of the newly added reference Jiang as detailed in the rejection above edited to address the features added in the amendment.
The Applicant argues in substance that the cited prior art does not disclose the processor to perform the FMMAS operations comprises to perform multiplication operations each to generate , based on respective two source inputs of the four or more source inputs , a different, respective one of multiple multi-bit intermediate values and perform one or more arithmetic operations each based on respective portions of a respective tow multi-bit intermediate values of the multiple intermediate values; for each arithmetic operation of the one or more arithmetic operations a respective value of the mask operand is to identify that arithmetic operation is to be a respective one of an addition operation or a subtraction operation; and the opcode or the mask operand is to indicate that the respective portions of the respective two multi-bit intermediate values is to comprise: only respective lower portions of the respective two multi-bit intermediate values; or only respective upper portions of the respective two multi-bit intermediate values; or indicate that for each arithmetic operation of the one or more arithmetic operations, the mask operation is to identify that the respective portions of the multi-bit intermediate values are to comprise: only respective lower portions of the respective two multi-bit intermediate values; or only respective upper portions of the respective two multi-bit intermediate values
The Examiner contends that the combination of the Sankaranarayanan and Jiang references taught this limitation as detailed in the rejection above.
The Examiner contends that Sankaranarayanan and Jiang, and further in view of Lupon (ACM paper entitled Speculative Hardware/Software Co-Designed Floating-Point Multiply-Add Fusion) taught the limitation of claims 8,9,15,16,22,23 as detailed in the rejection above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tanaka (patent application publication No. 2004/0078549) disclosed processor executing SIMD instructions (e.g., see abstract).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC COLEMAN whose telephone number is (571)272-4163. The examiner can normally be reached M-F.
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ERIC . COLEMAN
Primary Examiner
Art Unit 2183
EC
/ERIC COLEMAN/Primary Examiner, Art Unit 2183