Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is nonfinal and is in response to claims filed on 03/30/2026 via RCE. Claims 1-10 and 12-20 are pending for examination. Claims 1, 8-10, 13-14, and 17 are currently amended.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/30/2026 has been entered.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 02/26/2026 is in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Response to Arguments
Objections to the Claims
Applicant has amended the claims at issue, and, therefore, the previous rejections have been withdrawn.
Claim Interpretation
Applicant has amended the language of claim 14. However, these amendments still are directed to contingent language. Therefore, the previous interpretation of claim 14 has been updated and maintained.
Rejections Under 35 U.S.C. 112(a)
Applicant has amended the claims at issue, and, therefore, the previous rejections have been withdrawn.
Rejections Under 35 U.S.C. 112(b)
Applicant has not amended the limitation of “a zero anticipator and counter for determining a number of bits from among the first bits of two mantissa values are equal”, and, therefore, the previous rejection of claim 14 is maintained.
Applicant has amended the other claims at issue, and, therefore, the previous rejections have been withdrawn.
Rejections Under 35 U.S.C. 103
Applicant’s arguments, see Remarks 12-13, filed 03/30/2026, with respect to claims 1-10, 12-13, and 17-20 have been fully considered and are persuasive. The previous rejections of claims 1-10, 12-13, and 17-20 has been withdrawn.
Applicant’s arguments regarding the 35 U.S.C. 103 rejections of claims 14-16 have been fully considered. Claims 14-16 are still directed to contingent language and thus only one of the ‘in response’ limitations is required to be taught by the prior art.
Plondke teaches of “performing an inverse operation on the simplified value during at least two cycles of the floating point operation circuit”, see Plondke [0032] and Plondke Fig. 1.
Plondke also teaches of “and performing, based on the transform factor, an inverse transform operation in a last cycle of the at least two cycles of the floating point operation circuit,” see Plondke [0034] and Plondke Fig. 1.
Plondke in view of Lutz teaches of “and an exponent adder for adding an exponent value of the transform factor in the last cycle of the at least two cycles of the floating point operation circuit,” see Plondke [0032], Plondke Fig. 1, Plondke [0034], and Lutz [0033].
Rejections Under 35 U.S.C. 101
Applicant’s arguments regarding the 35 U.S.C. 101 rejections have been fully considered. Applicant argues “As discussed in detail in the specification, e.g., at paragraphs [0102], [0129], [0133] and [0158], the claimed circuit improves the operation of a hardware accelerator by preventing loss of information when an input value belongs to a subnormal range (i.e., less than a threshold value) so as to make division by the input value resource intensive (e.g., consuming more time and memory)”. See Remarks 10-11.
Examiner respectfully disagrees with Applicant’s arguments. These purported improvements are to the math itself and generic computer components.
It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements. See the discussion of Diamond v. Diehr, 450 U.S. 175, 187 and 191-92, 209 USPQ 1, 10 (1981)) in subsection II, below. In addition, the improvement can be provided by the additional element(s) in combination with the recited judicial exception... However, it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology...”. See MPEP 2106.05(a).
Applicant further argues “the claims are not directed to an evaluation mental process at least for the reason that the determination of bit values performed by various recited circuit components cannot practically be performed by a human mind”. See Remarks 11.
Examiner respectfully disagrees with Applicant’s arguments. The various circuits are recited at a high level of generality and is a clear “apply it” scenario using generic computer components. MPEP 2106.05(f). The circuits do not denote any specific structure and is merely a generic circuit component performing the abstract ideas (the determination of bit values, etc.), which can be performed in the human mind with the aid of pen and paper.
Applicant further argues “the configuration of the exponent adder is an additional element that amounts to significantly more than the judicial exception”. See Remarks 11.
Examiner respectfully disagrees with Applicant’s arguments. The exponent adder is recited at a high level of generality and is a clear “apply it” scenario using generic computer components. MPEP 2106.05(f). The exponent adder does not denote any specific structure and is merely a generic circuit component performing the abstract ideas (adding the exponent value of the transform factor, etc.), which can be performed in the human mind with the aid of pen and paper.
Applicant further argues “claim 1 is patent eligible at Step 2B at least for the reason that it includes an inventive concept of using fused multiplication and addition operations to perform problematic division operations”. See Remarks 11.
Examiner respectfully disagrees with Applicant’s arguments. These purported improvements are to the math itself.
It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements. See the discussion of Diamond v. Diehr, 450 U.S. 175, 187 and 191-92, 209 USPQ 1, 10 (1981)) in subsection II, below. In addition, the improvement can be provided by the additional element(s) in combination with the recited judicial exception... However, it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology...”. See MPEP 2106.05(a).
Applicant further argues “Applicant further notes that the various components of the floating point operation circuit recited in claim 1 are specialized hardware circuits as discussed in the specification”. See Remarks 12.
Examiner respectfully disagrees with Applicant’s arguments. The specialized hardware circuits are recited at a high level of generality and is a clear “apply it” scenario using generic computer components. MPEP 2106.05(f). The circuits do not denote any specific structure and is merely a generic circuit component performing the abstract ideas, which can be performed in the human mind with the aid of pen and paper.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites “add an exponent bias value to a zero count of mantissa value”. This should be changed to “dd an exponent bias value to a zero count of the mantissa value”.
Claim 1 recites “add the exponent value of the transform factor and exponents of two input value”. This should be changed to “add the exponent value of the transform factor and exponents of two input values”.
Appropriate correction is required.
Claim Interpretation Part I
Claim 14 is directed to a method that recites conditional language. Claim 14 recites “wherein generating the transform factor comprises: in response to the divisor belonging to a normal range, outputting, by the zero anticipator and counter, an exponent value of the divisor, and generating, by an exponent extractor, a normal transform factor from the exponent value of the divisor” and “in response to the divisor belonging to a subnormal range, outputting, by the zero anticipator and counter, a zero count, and generating, by the exponent extractor, a subnormal transform factor”.
The conditional nature of this claim language allows for an interpretation where any prior art meets the broadest reasonable interpretation of the claim without having the conditional language even occurring (and thus only the preceding limitations required by the prior art). For example, in claim 14, only one of the “outputting, by the zero anticipator and counter, an exponent value of the divisor, and generating, by an exponent extractor, a normal transform factor from the exponent value of the divisor” and “outputting, by the zero anticipator and counter, a zero count, and generating, by the exponent extractor, a subnormal transform factor” limitations is required to be taught by the prior art. See MPEP 2111.04(II); see also Ex parte Schulhauser. Examiner notes that the broadest reasonable interpretation of the method of claim 14 require only one of those “in response to” conditions to occur and thus the claim language ends. Examiner encourages claim amendments that specifically removes the conditional language of the claims and thus expressly has the claimed scenarios occur. Examiner respectfully reiterates that without changing the conditional nature of the claim, the method claims carry no patentable weight as noted above.
Claim Interpretation Part II
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: “mantissa multiplier”, “alignment shifter”, “exponent adder”, “mantissa adder”, “exponent extractor”, and “zero anticipator and counter” in claims 1, 8, and 14.
The specification recites, in paragraph [00181], “In the above-described embodiments, components according to embodiments of the present disclosure are referenced by using blocks. The blocks may be implemented with various hardware devices, such as, for example, an integrated circuit, an application specific IC (ASIC), a field programmable gate array (FPGA), and a complex programmable logic device (CPLD), firmware driven in hardware devices, software such as, for example, an application, or a combination of a hardware device and software. Also, the blocks may include circuits implemented with semiconductor elements in an integrated circuit, or circuits enrolled as an intellectual property (IP) block”
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to claim 14, it recites “a zero anticipator and counter for determining a number of bits from among the first bits of two mantissa values are equal”. This is generally confusing to one of ordinary skill in the art and the grammar is confusing. It is unclear if the zero anticipator and counter is one component or two separate components. It is also unclear what is being determined to be equal.
Claims 15-16 are rejected for being dependent on an above rejected claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-10 and 12-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more.
With regards to claim 1, at step 1, the claim is directed to a machine, which is a statutory category of invention.
At Step 2A Prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical concepts. The claim language has been reproduced below:
A floating point operation circuit configured to: (mental process, evaluation)
receive a first instruction, and first, second and third input values from registers storing respective input values; (mathematical relationship)
in response to receiving the first instruction, (mental process, evaluation) generate a first output value by performing a fused multiplication and addition operation on the first, second and third input values and store the first output value, (mathematical calculation)
receive a second instruction; and (mental process, evaluation; mathematical relationship)
in response to receiving the second instruction, (mental process, evaluation) generate a transform factor and a simplified value from one input value from among a fourth, fifth and sixth input values, (mathematical calculation) and generate a second output value being an inverse value of the one input by performing an inverse operation on the simplified value (mathematical calculation) during at least two cycles of the floating point operation circuit (mental process, evaluation) and performing an inverse transform operation based on the transform factor (mathematical calculation) in a last cycle of the at least two cycles, (mental process, evaluation)
wherein the floating point operation circuit comprises: (mental process, evaluation)
a mantissa multiplier configured to (mental process, evaluation) multiply a mantissa of the first input value and a mantissa of the second input value (mathematical calculation) and transfer an output thereof to an alignment shifter;
an exponent adder configured to (mental process, evaluation) add an exponent of the first input value and an exponent of the second input value (mathematical calculation) and transfer an output thereof to the alignment shifter;
the alignment shifter configured to (mental process, evaluation) align a number of digits of the third input value, and a number of digits of the values of the outputs of the mantissa multiplier and exponent adder, (mathematical calculation) and output a mantissa of the third input value, and mantissa values calculated by the mantissa multiplier and exponent adder;
a mantissa adder configured to (mental process, evaluation) add mantissa values output from the alignment shifter (mathematical calculation); and
an exponent extractor configured to (mental process, evaluation) generate the transform factor, (mathematical calculation
wherein in response to the one input value belonging to a subnormal range, the exponent extractor is configured to (mental process, evaluation) add an exponent bias value to a zero count of mantissa value of the one input value and subtracting 2 therefrom to obtain an exponent value of the transform factor, and (mathematical calculation)
wherein the exponent adder is further configured to (mental process, evaluation) add the exponent value of the transform factor and exponents of two input value from the registers, (mathematical calculation) in the last cycle of the at least two cycles (mental process, evaluation).
Each of the non-bolded limitations are mental processes and/or mathematical calculations. The “A floating point operation circuit configured to” limitation is an evaluation mental process that can be performed by choosing what the floating point operation circuit is configured to do. The “receive a first instruction, and first, second and third” limitation is a mathematical relationship that can be performed by receiving the instruction and inputs by hand using pen and paper. The “in response to receiving the first instruction” limitation is an evaluation mental process that can be performed by choosing what to do after receiving a first instruction. The “generate a first output value by performing a fused multiplication” limitation is a mathematical calculation that can be performed by performing a fused multiply add calculation by hand using pen and paper. The “receive a second instruction” limitation is an evaluation mental process and mathematical relationship that can be performed by receiving the instruction by hand using pen and paper. The “in response to receiving the second instruction” limitation is an evaluation mental process that can be performed by choosing what to do after receiving a second instruction. The “generate a transform factor and a simplified value from one input value from among a fourth, fifth and sixth input values” limitation is a mathematical calculation that can be performed by inverting the input by hand using pen and paper. The “and generate a second output value being an inverse value of the one input” limitation is a mathematical calculation that can be performed by performing the inverse operation on the simplified value by hand using pen and paper. The “during at least two cycles of” limitation is an evaluation mental process that can be performed by choosing when the operation occurs. The “and performing an inverse transform operation based on” limitation is a mathematical calculation that can be performed by performing the inverse transform operation by hand using pen and paper. The “in a last cycle of the at” limitation is an evaluation mental process that can be performed by choosing when to perform the inverse transform operation. The “wherein the floating point operation circuit comprises” limitation is an evaluation mental process that can be performed by choosing what the floating point operation circuit comprises. The “a mantissa multiplier configured to” limitation is an evaluation mental process that can be performed by choosing what the mantissa multiplier is configured to do. The “multiply a mantissa of the first input value and a mantissa of the second input value” limitation is a mathematical calculation that can be performed by multiplying the mantissas by hand using pen and paper. The “an exponent adder configured to” limitation is an evaluation mental process that can be performed by choosing what the exponent adder is configured to do. The “add an exponent of the first input value and an exponent” limitation is a mathematical calculation that can be performed by adding the exponents by hand using pen and paper. The “the alignment shifter configured to” limitation is an evaluation mental process that can be performed by choosing what the alignment shifter is configured to do. The “align a number of digits of the third input value” limitation is a mathematical calculation that can be performed by aligning the digits by hand using pen and paper. The “a mantissa adder configured to” limitation is an evaluation mental process that can be performed by choosing what the mantissa adder is configured to do. The “add mantissa values” limitation is a mathematical calculation that can be performed by adding the mantissas by hand using pen and paper. The “an exponent extractor configured to” limitation is an evaluation mental process that can be performed by choosing what the exponent extractor is configured to do. The “generate the transform factor” limitation is a mathematical calculation that can be performed by generating the transform factor by hand using pen and paper. The “wherein in response to the one input value belonging to a subnormal range, the exponent extractor is configured to” limitation is an evaluation mental process that can be performed by choosing what the exponent extractor is configured to do. The “add an exponent bias value to a zero count of mantissa value” limitation is a mathematical calculation that can be performed by adding an exponent bias value to a zero count of the mantissa value of the one input value and subtracting 2 therefrom by hand using pen and paper. The “wherein the exponent adder is further configured to” limitation is an evaluation mental process that can be performed by choosing what the exponent adder is further configured to do. The “add the exponent value of the transform factor and exponents of two input value from” limitation is a mathematical calculation that can be performed by adding the exponent value of the transform factor and exponents of two input values by hand using pen and paper. The “in the last cycle of the at least two cycles” limitation is an evaluation mental process that can be performed by choosing when the adding of the exponents is performed.
At step 2A Prong 2, the additional elements are bolded above. The “receiving” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘receiving’ in the context of the claim encompasses mere data gathering. The “storing” limitation, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘storing’ in the context of the claim encompasses mere data gathering. The “transfer” limitation, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘transfer’ in the context of the claim encompasses mere data gathering. The “output” limitation, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘output’ in the context of the claim encompasses mere data gathering. The remaining additional elements amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
Under Step 2B, the claim recites “receive a first instruction, and first, second and third input values”, “in response to receiving the first instruction”, “receive a second instruction”, “in response to receiving the second instruction”, “transfer an output thereof”, “transfer an output thereof”, “and output a mantissa of the third input value”, “output from the alignment shifter”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 2, it is directed to mental processes and/or mathematical concepts. The “the floating point operation circuit is further configured to” limitation is an evaluation mental process that can be performed by choosing what the floating point operation circuit is further configured to do. The “generate a simplified output by performing an inverse operation” limitation is a mathematical calculation that can be performed by performing an inverse operation by hand using pen and paper. The “which is based on the simplified value” limitation is an evaluation mental process that can be performed by choosing what the inverse operation is based on. Under step 2A Prong 2, none of the additional elements regarding the generic computer components (i.e. floating point operation circuit, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claims do not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 3, it is directed to mental processes and/or mathematical concepts. The “the floating point operation circuit is further configured to” limitation is an evaluation mental process that can be performed by choosing what the floating point operation circuit is further configured to do. The “generate the second output value by performing” limitation is a mathematical calculation that can be performed by performing the inverse operation by hand using pen and paper. Under step 2A Prong 2, none of the additional elements regarding the generic computer components (i.e. floating point operation circuit, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claims do not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 4, it is directed to mental processes and/or mathematical concepts. The “wherein the inverse transform operation comprises” limitation is an evaluation mental process that can be performed by choosing what the inverse transform comprises. The “multiplying the simplified output” limitation is a mathematical calculation that can be performed by multiplying the simplified output and transform factor together my hand using pen and paper. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 5, it is directed to mental processes and/or mathematical concepts. The “wherein the inverse operation is based” limitation is an evaluation mental process that can be performed my choosing what the inverse operation is based on. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 6, it is directed to mental processes and/or mathematical concepts. The “wherein the simplified value is in a range” limitation is an evaluation mental process that can be performed my choosing what the range of the simplified value is. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 7, it is directed to mental processes and/or mathematical concepts. The “the floating point operation circuit is configured to” limitation is an evaluation mental process that can be performed by choosing what the floating point operation circuit is configured to do. The “perform the inverse operation once” limitation is a mathematical calculation that can be performed by fused multiplication and addition operation by hand using pen and paper. The “which is based on the first instruction” limitation is an evaluation mental process that can be performed by choosing what the fused multiplication and addition instruction is based on. Under step 2A Prong 2, none of the additional elements regarding the generic computer components (i.e. floating point operation circuit, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claims do not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 8, it is directed to mental processes and/or mathematical concepts. The “the floating point operation circuit is further configured to” limitation is an evaluation mental process that can be performed by choosing what the floating point operation circuit is further configured to do. The “generate the simplified value” limitation is a mathematical calculation that can be performed by multiplying the one input value and transform factor by hand using pen and paper. Under step 2A Prong 2, none of the additional elements regarding the generic computer components (i.e. floating point operation circuit, exponent extractor, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claims do not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 9, it is directed to mental processes and/or mathematical concepts. The “wherein the transform factor and the simplified value from the one input value are generated differently” limitation is an evaluation mental process that can be performed by choosing how the transform factor and simplified value are generated. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 10, it is directed to mental processes and/or mathematical concepts. The “in response to the one input value belonging to the normal range, the exponent extractor is configured to” limitation is an evaluation mental process that can be performed by choosing what the exponent extractor is configured to do. The “subtract an exponent value of the one input value and 1 from an exponent bias value to obtain an exponent value of the transform factor” limitation is a mathematical calculation that can be performed by subtracting the exponent and 1 form the bias by hand using pen and paper. Under step 2A Prong 2, none of the additional elements regarding the generic computer components (i.e. exponent extractor, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claims do not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 12, it is directed to mental processes and/or mathematical concepts. The “wherein an exponent value of the simplified value” limitation is an evaluation mental process that can be performed by choosing what the exponent value is. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 13, it is directed to mental processes and/or mathematical concepts. The “wherein the simplified value is fixed as belonging to a normal range” limitation is an evaluation mental process that can be performed by choosing the range of the simplified value. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 14, at step 1, the claim is directed to a method, which is a statutory category of invention.
At Step 2A Prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical concepts. The claim language has been reproduced below:
An operating method of a floating point operation circuit, comprising: (mental process, evaluation)
calculating an inverse value of a divisor of a division operation, based on a second operation mode; and (mental process, evaluation; mathematical calculation)
performing a multiplication operation of a dividend and an inverse value of the divisor, based on a first operation mode, (mental process, evaluation; mathematical calculation)
wherein calculating the inverse value of the divisor of the division operation, based on the second operation mode comprises: (mental process, evaluation)
generating a transform factor and a simplified value from the divisor, in the second operation mode (mental process, evaluation; mathematical calculation)
performing an inverse operation on the simplified value (mathematical calculation) during at least two cycles of the floating point operation circuit; and (mental process, evaluation)
performing, based on the transform factor, an inverse transform operation (mathematical calculation) in a last cycle of the at least two cycles of the floating point operation circuit, (mental process, evaluation)
wherein the floating point operation circuit comprises: (mental process, evaluation)
a first register for storing the dividend, a second register for storing the divisor, and a third register for storing an input value; (mental process, evaluation)
a zero anticipator and counter for (mental process, evaluation) determining a number of bits from among the first bits of two mantissa values are equal, (mathematical calculation) the two mantissa values including: (i) a mantissa of the input value, and (ii) a mantissa of an multiplication of mantissa values of the dividend and the divisor, (mental process, evaluation; mathematical calculation) and generating an anticipated zero count; and (mathematical calculation)
an exponent extractor for (mental process, evaluation) generating the transform factor based on an output of the zero anticipator and counter; and (mathematical calculation)
an exponent adder for (mental process, evaluation) adding an exponent value of the transform factor (mathematical calculation) in the last cycle of the at least two cycles of the floating point operation circuit, (mental process, evaluation)
wherein generating the transform factor comprises: (mental process, evaluation)
in response to the divisor belonging to a normal range, outputting, by the zero anticipator and counter, an exponent value of the divisor, (mathematical calculation) and generating, by the exponent extractor, a normal transform factor from the exponent value of the divisor; and (mathematical calculation)
in response to the divisor belonging to a subnormal range, outputting, by the zero anticipator and counter, a zero count, (mathematical calculation) and generating, by the exponent extractor, a subnormal transform factor (mathematical calculation)
wherein the exponent extractor (mental process, evaluation) adds an exponent bias value to the zero count of mantissa value of the input value and subtracts 2 therefrom to obtain the exponent value of the transform factor (mathematical calculation).
Each of the non-bolded limitations are mental processes and/or mathematical calculations. The “An operating method” limitation is an evaluation mental process that can be performed by choosing what the operating method comprises. The “calculating an inverse” limitation is an evaluation mental process an mathematical calculation that can be performed by calculating the inverse of a divisor by hand using pen and paper. The “performing a multiplication operation of a dividend” limitation is an evaluation mental process an mathematical calculation that can be performed by multiplying the dividend and the inverse of the divisor by hand using pen and paper. The “wherein calculating the inverse value” limitation is an evaluation mental process that can be performed by choosing what the calculating comprises. The “generating a transform” limitation is an evaluation mental process an mathematical calculation that can be performed by generating the transform factor and simplified value by hand using pen and paper. The “performing an inverse operation on the simplified value” limitation is a mathematical calculation that can be performed by performing the inverse operation on the simplified value by hand using pen and paper. The “during at least two cycles of” limitation is an evaluation mental process that can be performed by choosing when the operation occurs. The “performing, based on the transform factor, an inverse transform operation” limitation is a mathematical calculation that can be performed by performing the inverse transform operation by hand using pen and paper. The “in a last cycle of the at” limitation is an evaluation mental process that can be performed by choosing when to perform the inverse transform operation. The “wherein the floating point operation circuit comprises” limitation is an evaluation mental process that can be performed by choosing what the floating point operation circuit comprises. The “a first register for storing the dividend” limitation is an evaluation mental process that can be performed by choosing what the registers store. The “a zero anticipator and counter for” limitation is an evaluation mental process that can be performed by choosing what the zero anticipator and counter does. The “determining a number of bits” limitation is a mathematical calculation that can be performed by determining the number of bits by hand using pen and paper. The “the two mantissa values including” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing what the mantissas are and adding the divisor and dividend by had using pen and paper. The “generating an anticipated zero count” limitation is a mathematical calculation that can be performed by generating the anticipated zero count by hand using pen and paper. The “an exponent extractor for” limitation is an evaluation mental process that can be performed by choosing what the exponent extractor does. The “generating the transform value based on” limitation is a mathematical calculation that can be performed by generating the transform value by hand using pen and paper. The “an exponent extractor for” limitation is an evaluation mental process that can be performed by choosing what the exponent extractor is used for. The “adding an exponent value of the transform factor” limitation is a mathematical calculation that can be performed by adding an exponent value of the transform factor by hand using pen and paper. The “in the last cycle of the at least two cycles” limitation is an evaluation mental process that can be performed by choosing when the operation is performed. The “wherein generating the transform factor comprises” limitation is an evaluation mental process that can be performed by choosing what the generating the transform factor comprises. The “an exponent value of the divisor” limitation is a mathematical calculation that can be performed by outputting the exponent value by hand using pen and paper. The “a normal transform factor from the” limitation is a mathematical calculation that can be performed by generating the normal transform factor by hand using pen and paper. The “a zero count” limitation is a mathematical calculation that can be performed by outputting the zero count by hand using pen and paper. The “subnormal transform factor” limitation is a mathematical calculation that can be performed by generating the subnormal transform factor by hand using pen and paper. The “wherein the exponent extractor” limitation is an evaluation mental process that can be performed by choosing what the exponent extractor does. The “adds an exponent bias value to the zero count of mantissa value of the input value and subtracts 2 therefrom to obtain the exponent value of the transform factor” limitation is a mathematical calculation that can be performed by adding the exponent bias value to the zero count of mantissa value of the input value and subtracting 2 therefrom by hand using pen and paper.
At step 2A Prong 2, the additional elements are bolded above. The “storing” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘storing’ in the context of the claim encompasses mere data gathering. The “output” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘output’ in the context of the claims encompasses mere data gathering. The remaining additional elements amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
Under Step 2B, the claim recites “a first register for storing the dividend”, “a second register for storing the divisor”, “a third register for storing an input value”, “an output of the zero anticipator and counter”, “outputting, by a zero anticipator and counter, an exponent value of the divisor”, “outputting, by the zero anticipator and counter, a zero count”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 15, it is directed to mental processes and/or mathematical concepts. The “wherein the first operation mode” limitation is an evaluation mental process that can be performed by choosing what the first operating mode is. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 16, it is directed to mental processes and/or mathematical concepts. The “wherein the divisor, the inverse value of the divisor,” limitation is an evaluation mental process that can be performed by choosing what the divisor, inverse of the divisor, and dividend comprise. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 17, at step 1, the claim is directed to a machine, which is a statutory category of invention.
At Step 2A Prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical concepts. The claim language has been reproduced below:
An integrated circuit, comprising: (mental process, evaluation)
a first register;
a second register;
a third register;
a fourth register;
a fifth register; and
a floating point operation circuit configured to:
generate, in a first operation mode, a first intermediate value by multiplying a value of the first register and a value of the second register together, (mathematical calculation) generate an output value by adding a value of the third register and the first intermediate value, and store the output value in the fourth register, (mathematical calculation)
generate, in a first phase of a second operation mode, a simplified value and a transform factor from a value of the second register, store the simplified value in the fourth register, and store the transform factor in the fifth register, (mathematical calculation) and
generate a second output value being an inverse value of the value of the second register by performing an inverse operation on the simplified value (mathematical calculation) during at least two cycles of the floating point operation circuit (mental process, evaluation) and performing an inverse transform operation based on the transform factor (mathematical calculation) in a last cycle of the at least two cycles, (mental process, evaluation)
wherein a value having a sign opposite to a sign of a value stored in the fourth register is transferred to the first register, (mental process, evaluation)
wherein the floating point operation circuit comprises: (mental process, evaluation)
a mantissa multiplier configured to (mental process, evaluation) multiply a mantissa of a value of the first register and a mantissa of a value of the second register (mathematical calculation) and transfer an output thereof to an alignment shifter; (mental process, evaluation)
an exponent adder configured to (mental process, evaluation) add an exponent of the value of the first register and an exponent of the value of the second register (mathematical calculation) and transfer an output thereof to the alignment shifter; (mental process, evaluation)
the alignment shifter configured to (mental process, evaluation) align a number of digits of a value of the third register, and a number of digits of the values of the outputs of the mantissa multiplier and exponent adder, (mathematical calculation) and output a mantissa of the value of the third register, and mantissa values calculated by the mantissa multiplier and exponent adder; (mental process, evaluation)
a mantissa adder configured to (mental process, evaluation) add mantissa values output from the alignment shifter; and (mathematical calculation)
an exponent extractor configured to (mental process, evaluation) generate the transform factor, (mathematical calculation)
wherein in response to the one input belonging to a subnormal range, the exponent extractor is configured to (mental process, evaluation) add an exponent bias value to a zero count of mantissa value of the one input and subtracting 2 therefrom to obtain an exponent value of the transform factor, (mathematical calculation)
wherein the exponent adder is further configured to (mental process, evaluation) add the exponent value of the transform factor, an exponent of the value of the first register, and an exponent of the value of the second register (mathematical calculation) in the last cycle of the at least two cycles (mental process, evaluation).
Each of the non-bolded limitations are mental processes and/or mathematical calculations. The “An integrated circuit, comprising:” limitation is an evaluation mental process that can be performed by choosing what the integrated circuit comprises. The “a floating point operation circuit configured to” limitation is an evaluation mental process that can be performed by choosing what the floating point operation circuit is configured to do. The “generate, in a first operation mode,” limitation is a mathematical calculation that can be performed by multiplying the values stored in the first and second registers together by hand using pen and paper. The “generate an output value” limitation is a mathematical calculation that can be performed by adding the intermediate value and the value sorted in the third register by hand using pen and paper. The “generate, in a first phase of a second operation mode” limitation is a mathematical calculation that can be performed by generating the simplified value and transform factor by hand using pen and paper. The “generate a second output value being an inverse value of the value of the” limitation is a mathematical calculation that can be performed by generating the second output by hand using pen and paper. The “during at least two cycles of” limitation is an evaluation mental process that can be performed by choosing when the generating occurs. The “and performing an inverse transform operation” limitation is a mathematical calculation that can be performed by performing the inverse transform operation by hand using pen and paper. The “in a last cycle of the at least two cycles” limitation is an evaluation mental process that can be performed by choosing when the inverse transform operation occurs. The “wherein a value having a sign opposite” limitation is an evaluation mental process that can be performed by choosing where the values are stored. The “wherein the floating point operation circuit comprises:” limitation is an evaluation mental process that can be performed by choosing what the floating point operation comprises. The “a mantissa multiplier configured to” limitation is an evaluation mental process that can be performed by choosing what the mantissa multiplier is configured to do. The “multiply a mantissa of a value of the first register and a mantissa of a value of the second register” limitation is a mathematical calculation that can be performed by multiplying the mantissa of a value of the first register and a mantissa of a value of the second register by hand using pen and paper. The “and transfer an output thereof to an alignment shifter” limitation is an evaluation mental process that can be performed by choosing where the values are output. The “an exponent adder configured to” limitation is an evaluation mental process that can be performed by choosing what the exponent adder is configured to do. The “add an exponent of the value of the first register and an exponent of the value of the second register” limitation is a mathematical calculation that can be performed by adding an exponent of the value of the first register and an exponent of the value of the second register by hand using pen and paper. The “and transfer an output thereof to the alignment shifter” limitation is an evaluation mental process that can be performed by choosing where the values are output. The “the alignment shifter configured to” limitation is an evaluation mental process that can be performed by choosing what the alignment shifter is configured to do. The “align a number of digits of a value of the third register, and a number of” limitation is a mathematical calculation that can be performed by aligning the values by hand using pen and paper. The “and output a mantissa of the value of the third register, and mantissa values” limitation is an evaluation mental process that can be performed by choosing where the values are output. The “a mantissa adder configured to” limitation is an evaluation mental process that can be performed by choosing what the mantissa adder is configured to do. The “add mantissa values output from the alignment shifter” limitation is a mathematical calculation that can be performed by add mantissa values output from the alignment shifter by hand using pen and paper. The “an exponent extractor configured to” limitation is an evaluation mental process that can be performed by choosing what the exponent extractor is configured to do. The “generate the transform factor,” limitation is a mathematical calculation that can be performed by generating the transform factor by hand using pen and paper. The “wherein in response to the one input belonging to a subnormal range, the exponent extractor is configured to” limitation is an evaluation mental process that can be performed by choosing what the exponent extractor is configured to do. The “add an exponent bias value to a zero count of mantissa value of the one input and subtracting 2 therefrom” limitation is a mathematical calculation that can be performed by adding an exponent bias value to a zero count of mantissa value of the one input and subtracting 2 therefrom by hand using pen and paper. The “wherein the exponent adder is further configured to” limitation is an evaluation mental process that can be performed by choosing what the exponent adder is configured to do. The “add the exponent value of the transform factor, an exponent of the value of the first register, and an exponent of the value of the second register” limitation is a mathematical calculation that can be performed by adding the exponent value of the transform factor, an exponent of the value of the first register, and an exponent of the value of the second register by hand using pen and paper. The “in the last cycle of the at least two cycles” limitation is an evaluation mental process that can be performed by choosing when to perform operation.
At step 2A Prong 2, the additional elements are bolded above. The “store” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘store’ in the context of the claim encompasses mere data gathering. The “stored” limitation, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘stored’ in the context of the claim encompasses mere data gathering. The “transferred” limitation, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘transferred’ in the context of the claim encompasses mere data gathering. The remaining additional elements amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
Under Step 2B, the claim recites “and store the output value in the fourth register”, “store the simplified value in the fourth register”, “store the transform factor in the fifth register”, “stored in the fourth register is transferred to the first register”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 18, it is directed to mental processes and/or mathematical concepts. The “the floating point operation circuit is further configured” limitation is an evaluation mental process that can be performed by choosing what the floating point operation circuit is further configured to do. The “repeat, in a second phase of the second operation mode, a calculation operation of adding” limitation is an evaluation mental process and mathematical calculation that can be performed by multiplying the value of the second and first register and then adding the value of the third register by hand using pen and paper. The “wherein a specific initial value is” limitation is an evaluation mental process that can be performed by choosing what the initial value is. Under step 2A Prong 2, the “stored” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘stored’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. floating point operation circuit, the first register, the second register, the third register, the fourth register, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “a value stored in the second register”, “a value stored in the first register”, “a value stored in the third register”, “to be stored in the fourth register”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 19, it is directed to mental processes and/or mathematical concepts. The “the floating point operation circuit is further configured” limitation is an evaluation mental process that can be performed by choosing what the floating point operation circuit is further configured to do. The “generate, in a third phase of the second operation mode, a second intermediate value by adding” limitation is a mathematical calculation that can be performed by multiplying the value stored in the second register and the value stored in the first register and adding the value stored in the third register my hand using pen and paper. The “and multiply the” limitation is a mathematical calculation that can be performed by multiplying the intermediate value and transform factor by hand using pen and paper. Under step 2A Prong 2, the “stored” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘stored’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. floating point operation circuit, the first register, the second register, the third register, the fourth register, the fifth register, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “a value stored in the second register”, “a value stored in the first register”, “a value stored in the third register”, “the transform factor stored in the fifth register”, “so as to be stored in the fourth register”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 20, it is directed to mental processes and/or mathematical concepts. The “wherein the first register” limitation is an evaluation mental process that can be performed by choosing how the first register, the second register, the third register, the fourth register, the fifth register, and the floating point operation circuit are implemented. None of the additional elements regarding the generic computer components (i.e. floating point operation circuit, the first register, the second register, the third register, the fourth register, the fifth register, the digital signal processor, the neural processor, the computer vision processor, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over US 20140067894 A1) hereinafter Plondke in view of Lutz et al. (US 20150199173 A1) hereinafter Lutz further in view of Ng et al. (US 20190114538 A1) hereinafter Ng further in view of Dance et al. (US 20070112902 A1) hereinafter Dance further in view of Guim et al. (WO 2017167398 A1) hereinafter Guim.
With regards to claim 14, Plondke teaches An operating method of a floating point operation circuit, comprising: calculating an inverse value of a divisor of a division operation, based on a second operation mode; (Plondke [0031]: With reference now to FIG. 1A, mathematical equations for division using the Newton-Raphson method are shown. In block 102, a fundamental step of refining the reciprocal estimate is shown, wherein an initial reciprocal estimate, r.sub.i is obtained. This initial reciprocal estimate is then multiplied by the denominator d)
and performing a multiplication operation of a dividend and an inverse value of the divisor, based on a first operation mode, (Plondke [0033]: As previously noted, the quotient estimate q can be computed by multiplying the finally converged reciprocal r with the numerator n)
wherein calculating the inverse value of the divisor of the division operation, based on the second operation mode comprises: generating a transform factor and a [simplified] value from the divisor, in the second operation mode (Plondke [0031]: With reference now to FIG. 1A, mathematical equations for division using the Newton-Raphson method are shown. In block 102, a fundamental step of refining the reciprocal estimate is shown, wherein an initial reciprocal estimate, r.sub.i is obtained. This initial reciprocal estimate is then multiplied by the denominator d; The denominator d being the one input and the initial reciprocal estimate being the transform factor)
performing an inverse operation on the simplified value during at least two cycles of the floating point operation circuit; (Plondke [0032]: Coming to block 104, an improvement to the next error term calculation is illustrated. In some instances, the next estimate for the error term, .epsilon..sub.i+1 can be generated by squaring the reciprocal estimate .epsilon..sub.i. Because the next error term .epsilon..sub.i+1 calculated in this manner, does not depend on the reciprocal estimate, like in the case of calculation of the error term in block 102, this approach to estimating .epsilon..sub.i+1 can be performed in parallel with computation of the reciprocal estimates, and can thus improve performance)
and performing, based on the transform factor, an inverse transform operation in a last cycle of the at least two cycles of the floating point operation circuit, (Plondke [0034]: Thereafter, subsequent iterations for the quotient, q.sub.i+1 an be obtained by adding the initially obtained quotient q.sub.i to the product of .delta..sub.i and r)
wherein the floating point operation circuit comprises: [a first register] for storing the dividend, (Plondke [0033]: As previously noted, the quotient estimate q can be computed by multiplying the finally converged reciprocal r with the numerator n; Plondke [0063]: One or more registers in a register file (not shown) may also be configured to store)
[a second register] for storing the divisor, (Plondke [0033]: As previously noted, the quotient estimate q can be computed by multiplying the finally converged reciprocal r with the numerator n; Plondke [0063]: One or more registers in a register file (not shown) may also be configured to store)
[and (ii) a mantissa] of an multiplication of [mantissa] values of the dividend and the divisor, (Plondke [0033]: As previously noted, the quotient estimate q can be computed by multiplying the finally converged reciprocal r with the numerator n)
[and an exponent adder for adding an exponent value] of the transform factor in the last cycle of the at least two cycles of the floating point operation circuit (Plondke [0032]: Coming to block 104, an improvement to the next error term calculation is illustrated. In some instances, the next estimate for the error term, .epsilon..sub.i+1 can be generated by squaring the reciprocal estimate .epsilon..sub.i. Because the next error term .epsilon..sub.i+1 calculated in this manner, does not depend on the reciprocal estimate, like in the case of calculation of the error term in block 102, this approach to estimating .epsilon..sub.i+1 can be performed in parallel with computation of the reciprocal estimates, and can thus improve performance; Plondke [0034]: Thereafter, subsequent iterations for the quotient, q.sub.i+1 an be obtained by adding the initially obtained quotient q.sub.i to the product of .delta..sub.i and r; (this shows that the reciprocal estimate is multiplied in the last cycle))
Plondke fails to teach a simplified value.
However, Ng does teach a simplified value (Ng [0055]: that would reduce the range of the A1 and B1 inputs).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Plondke with the simplified value as taught by Ng. One of ordinary skill in the art would be motivated to make this combination because it would make calculations quicker as the input would be smaller, also requiring less resources.
Plondke in view of Ng fails to teach and a third register for storing an input value, a zero anticipator and counter for determining a number of bits from among the first bits of two mantissa values are equal, the two mantissa values including: (i) a mantissa of the input value, and (ii) a mantissa [of a multiplication] of mantissa [values of the dividend and the divisor,], and generating an anticipated zero count, and an exponent adder for adding an exponent value [of the transform factor in the last cycle of the at least two cycles of the floating point operation circuit].
However, Lutz teaches [and a third register] for storing an input value; (Lutz [0043]: the mantissa of B)
a zero anticipator and counter for determining a number of bits from among the first bits of two mantissa values are equal, (Lutz [0029]-Lutz [0032]: first count-leading-zero circuitry configured to determine a count value CLZB of a number of leading zeros in a mantissa value of B… a first shifter configured to left shift said mantissa of B by CLZB places to form a shifted mantissa of B if CLZB is greater than zero... second count-leading-zero circuitry configured to determine a count value CLZC of a number of leading zeros in a mantissa value of C... a second shifter configured to left shift said mantissa of C by CLZC places to form a shifted mantissa of C if CLZC is greater than zero)
the two mantissa values including: (i) a mantissa of the input value, (Lutz [0043]: the mantissa of B)
and (ii) a mantissa [of a multiplication] of mantissa [values of the dividend and the divisor,] (Lutz [0049]: Shifters 48, 50 within stage E5 will apply shifts as determined by the alignment control circuitry 46 to form an aligned value of A and an aligned product value which can then be supplied to a bit adder 52 in the stage E6 of the adder 28 to form the result mantissa value)
and generating an anticipated zero count; (Lutz [0043]: In particular, the count-leading-zero circuitry 30 determines a count leading zero value CLZB for the mantissa of B. The count-leading-zero circuitry 34 determines a count leading zero value CLZC for the mantissa of C)
and an exponent adder for adding an exponent value [of the transform factor in the last cycle of the at least two cycles of the floating point operation circuit] (Lutz [0033]: In some embodiments the multiplier may be configured to form the product exponent as a sum of at least an exponent value of B, an exponent value of C).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Plondke in view of Ng with the fused multiply add operation and the zero anticipator as taught by Lutz. One of ordinary skill in the art would be motivated to make this combination because it would speed up calculations, as the output of the multiplication would not have to be rounded prior to the addition. Also, this increases the speed with which a multiply add operation may be performed as taught by Lutz (Lutz [0026]).
Plondke in view of Ng further in view of Lutz fails to teach fails to teach a first register [for storing the dividend,], a second register [for storing the divisor,], and a third register [for storing an input value;].
However, Guim teaches a first register [for storing the dividend,] (Guim [0026]: a first register… A second register… A third register… A fourth register… A fifth register)
a second register [for storing the divisor,] (Guim [0026]: a first register… A second register… A third register… A fourth register… A fifth register)
and a third register [for storing an input value;] (Guim [0026]: a first register… A second register… A third register… A fourth register… A fifth register).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Plondke in view of Ng further in view of Lutz with the registers of Guim. One of ordinary skill in the art would be motivated to make this combination because This would speed up calculations as the outputs could be stored for later use instead of having to be recalculated every time they need to be used.
Plondke in view of Ng further in view of Lutz further in view of Guim fails to teach and an exponent extractor for generating the transform value based on an output of the zero anticipator and counter, wherein generating the transform factor comprises: in response to the divisor belonging to a normal range, outputting, by the zero anticipator and counter, an exponent value of the divisor, and generating, by the exponent extractor, a normal transform factor from the exponent value of the divisor; and in response to the divisor belonging to a subnormal range, outputting, by the zero anticipator and counter, a zero count, and generating, by the exponent extractor, a subnormal transform factor, wherein the exponent extractor adds an exponent bias value to the zero count of mantissa value of the input value and subtracts 2 therefrom to obtain the exponent value of the transform factor.
However, Dance teaches and an exponent extractor for generating the transform value based on an output of the zero anticipator and counter, (Dance [0004]: The apparatus is adapted to, in response to the floating point pipeline logic receiving an input value having an exponent and a mantissa when represented as a floating point number on which a reciprocal estimate computation is to be performed (a) determine whether the exponent is one of a plurality of predetermined numbers; and (b) if the exponent is one of the plurality of predetermined numbers, adjust at least one of a plurality of modified mantissa bits (e.g., mantissa bits internal to LZA logic) and a result exponent based on the exponent)
wherein generating the transform factor comprises: in response to the divisor belonging to a normal range, outputting, by the zero anticipator and counter, an exponent value of the divisor, and generating, by the exponent extractor, a normal transform factor from the exponent value of the divisor; (Dance [0004]: The apparatus is adapted to, in response to the floating point pipeline logic receiving an input value having an exponent and a mantissa when represented as a floating point number on which a reciprocal estimate computation is to be performed (a) determine whether the exponent is one of a plurality of predetermined numbers; and (b) if the exponent is one of the plurality of predetermined numbers, adjust at least one of a plurality of modified mantissa bits (e.g., mantissa bits internal to LZA logic) and a result exponent based on the exponent)
in response to the divisor belonging to a subnormal range, outputting, by the zero anticipator and counter, a zero count, and generating, by the exponent extractor, a subnormal transform factor (Dance [0025]: In this manner, the FPU 102 may perform a reciprocal estimate on an input value, which may be sufficiently large enough to cause a reciprocal estimate underflow result using a conventional FPU, and output a denormal number)
wherein the exponent extractor adds an exponent bias value to the zero count of mantissa value of the input value and subtracts 2 therefrom to obtain the exponent value of the transform factor (Dance [0025]: In this manner, the FPU 102 may perform a reciprocal estimate on an input value, which may be sufficiently large enough to cause a reciprocal estimate underflow result using a conventional FPU, and output a denormal number).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Plondke in view of Ng further in view of Lutz further in view of Guim with the exponent extractor as taught by Dance. One of ordinary skill in the art would be motivated to make this combination because it would speed up the calculation of the reciprocal as the transform factor would be tailored to the input instead of being a generic starting point.
With regards to claim 15, Plondke in view of Ng further in view of Lutz further in view of Guim further in view of Dance teaches all of the limitations of claim 14 above. Plondke further teaches wherein the first operation mode supports a fused multiplication and addition operation (Plondke [0029]: Some embodiments may include exemplary formats of instructions such as fused multiply add (FMA)).
With regards to claim 16, Plondke in view of Ng further in view of Lutz further in view of Guim further in view of Dance teaches all of the limitations of claim 14 above. Plondke further teaches wherein the divisor, the inverse value of the divisor, and the dividend comprise a binary sign value, a binary exponent value, and a binary mantissa value, based on an IEEE (Institute of Electrical and Electronics Engineers) 754 standard (Plondke [0003]: The IEEE Standard for Binary Floating Point Arithmetic, IEEE 754, is portable across processor architectures, and commonly used in processors which implement floating point operations).
Allowable Subject Matter
Claim 1-10, 12-13, and 17-20 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 101 and 35 U.S.C. 112 set forth in this Office action and to include all of the limitations of the base claim and any intervening claims
While prior art teaches of obtaining the exponent value of a transform factor if the input is in the subnormal range, it fails to teach of finding said exponent by adding an exponent bias value to a zero count of a mantissa value of the one input and subtracting two therefrom.
Conclusion
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/J.O.G./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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