Prosecution Insights
Last updated: August 18, 2026
Application No. 17/698,032

Branch-History Mode Trace Encoder

Final Rejection §112
Filed
Mar 18, 2022
Priority
Mar 29, 2021 — provisional 63/167,516
Examiner
BERMAN, STEPHEN DAVID
Art Unit
2192
Tech Center
2100 — Computer Architecture & Software
Assignee
SiFive Inc.
OA Round
8 (Final)
78%
Grant Probability
Favorable
9-10
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
268 granted / 342 resolved
+23.4% vs TC avg
Strong +58% interview lift
Without
With
+58.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
23 currently pending
Career history
364
Total Applications
across all art units

Statute-Specific Performance

§101
12.9%
-27.1% vs TC avg
§103
48.1%
+8.1% vs TC avg
§102
14.8%
-25.2% vs TC avg
§112
17.5%
-22.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 342 resolved cases

Office Action

§112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office action is filed in response to Applicant’s arguments and amendment dated May 18, 2026. Claims 1, 6, 10, 16, and 19 are currently amended and claims 1, 3-4, 6, 8-10, 12-16, and 18-20 remain pending in the application and have been fully considered by Examiner. In view of Applicant’s amendments, the 35 USC 112(b) rejections of claims 6 and 19 are withdrawn. In view of Applicant’s amendments and remarks, the prior art rejections are withdrawn. Examiner Notes Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1, 3-4, 6, 8-10, 12-16, and 18-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. With respect to claim 1, as currently amended, lines 10-14 recite, with emphasis added, “responsive to determining that the subsequent branch executed by the processor core is not-taken, send a message including the count and a trace identifier associated with the processor core, clear the history buffer of previous branch results, and subsequently store, in the history buffer, individual results of one or more branches subsequently executed by the processor core.” In support of this amendment, Applicant cites their Fig. 4 and associated text at paragraphs [0042]-[0043]1. While this is the most relevant portion of Applicant’s original disclosure, these portions do not disclose clearing the history buffer of previous branch results responsive to determining that the subsequent branch executed by the processor core is not-taken. Rather, these portions disclose clearing a branch count from the history buffer responsive to determining that the subsequent branch executed by the processor core is not-taken. In detail, paragraphs [0042]-[0043] of Applicant’s specification state: “With the repeat branch optimization, the trace encoder 400 may maintain a count of branches that are consecutively taken, and/or a count of branches that are consecutively not-taken, when executed by the processor core. For example, when the history buffer 440 fills with branches having a same result (e.g., all branches consecutively taken, or all branches consecutively not-taken), the trace encoder 400 may start a count of the branches (e.g., branch count) associated with the same result without sending an RFM. In some implementations, the trace encoder 400 may clear the history buffer 440 of the individual branch results, store the branch count in the history buffer 440, and continue to update (e.g., maintain) the branch count stored in the history buffer 440 when a next branch generates the same result (e.g., increment the count). The trace encoder 400 may continue in this way, updating the count when a next branch generates the same result, until a next branch is executed by the processor core with an opposite result (e.g., until a branch is not-taken after multiple branches have been taken, or until a branch is taken after multiple branches have not been taken). When this opposite result occurs (e.g., responsive to a branch executing with the opposite result), the trace encoder 400 may send an RFM indicating the branch count (e.g., stored as a count in the history buffer 440). … after the RFM including the branch count is sent, the encoder logic 410 may clear the history buffer 440 …” (emphasis added). Thus, according to Applicant’s original disclosure, “previous branch results” are cleared from the history buffer when the buffer fills with consecutive branch results, which is entirely different from “responsive to determining that the subsequent branch executed by the processor core is not-taken … clear the history buffer of previous branch results”, as currently claimed (emphasis added). Furthermore, the specification quoted above discloses that a count of the consecutive branch results is then maintained in the cleared history buffer until a subsequent branch with an opposite result occurs (e.g., a subsequent branch that is not-taken, as in claim 1), at which point the encoder clears the history buffer of the stored count. As the “count” and “previous branch results”, as currently claimed, are entirely different and the original application only discloses clearing the count responsive to determining that the subsequent branch executed by the processor core is not-taken (see above), the claim limitation “responsive to determining that the subsequent branch executed by the processor core is not-taken … clear the history buffer of previous branch results” was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventors, at the time the application was filed, had possession of the claimed invention. Claim 1 is therefore rejected under 35 USC 112(a). With respect to claim 10, the limitations are similar to those discussed above with respect to claim 1 and thus claim 10 is also rejected under 35 USC 112(a) for the same reasons set forth above with respect to claim 1. With respect to claim 16, the limitations are substantively similar to those discussed above with respect to claim 1, except that claim 16 recites “consecutively not-taken … the subsequent branch executed by the processor core is taken” (emphasis added), whereas claim 1 recites “consecutively taken … the subsequent branch executed by the processor core is not-taken” (emphasis added). However, the same reasoning applied above with respect to claim 1 nonetheless applies to claim 16 as well. In short, Applicant’s original application only discloses responsive to a subsequent branch having an opposite result (e.g., “taken”, as in claim 16), clear the count from the history buffer, which is entirely different from claim 16 as currently amended, which recites “responsive to determining that the subsequent branch executed by the processor core is taken … clear the history buffer of previous branch results” (emphasis added). As the “count” and “previous branch results”, as currently claimed, are entirely different, claim 16 is rejected under 35 USC 112(a). For a more detailed explanation, please see the rejection of claim 1 above. With respect to all remaining dependent claims, each inherits the 35 USC 112(a) deficiency of its respective base claim (see the rejections of claim 1, 10, and 16 above). The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 3 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. With respect to claim 3, line 1 recites “the branches”. It is unclear whether this means “branches that are consecutively taken when executed by the processor core”, as recited on line 5 of parent claim 1, or “one or more branches subsequently executed by the processor core”, as recited on the last two lines of parent claim 1. This ambiguity renders the scope of claim 3 indefinite. For purposes of compact prosecution only, Examiner has interpreted claim 3 consistent with Applicant’s specification2 as reciting -- the branches that are consecutively taken --. With respect to claim 12, line 1 recites “the branches”. It is unclear whether this means “branches that are consecutively taken when executed by a processor core”, as recited on lines 2-3 of parent claim 10, or “one or more branches subsequently executed by the processor core”, as recited on the last two lines of parent claim 10. This ambiguity renders the scope of claim 12 indefinite. For purposes of compact prosecution only, Examiner has interpreted claim 12 consistent with Applicant’s specification3 as reciting -- the branches that are consecutively taken --. Conclusion The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure. Specifically, (1) Weiss et al. US 20150143343 A1 discloses compressing and decompressing trace messages for debugging; (2) Moyer et al. US 20100211827 A1 discloses compressing fields of debug messages and merging multiple messages; (3) Singh et al. US 7155570 B1 discloses trace compression for loops; and (4) Uzelac et al. “Real-time unobtrusive program execution trace compression using branch predictor events” discloses compressing traces by maintaining branch predictor-like structures that are updated during program execution similar to regular branch predictors. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN DAVID BERMAN whose telephone number is (571) 272-7206. The examiner can normally be reached M-F, 9-6 Eastern. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hyung S. Sough can be reached on 571-272-6799. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEPHEN D BERMAN/ Examiner, Art Unit 2192 1 See Remarks at pp. 9-10. 2 See Applicant’s specification at paragraphs [0067] and [0068]. 3 See Applicant’s specification at paragraphs [0067] and [0068].
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Prosecution Timeline

Show 15 earlier events
Feb 20, 2026
Request for Continued Examination
Mar 04, 2026
Response after Non-Final Action
Mar 11, 2026
Non-Final Rejection mailed — §112
May 06, 2026
Interview Requested
May 18, 2026
Applicant Interview (Telephonic)
May 18, 2026
Response Filed
May 28, 2026
Examiner Interview Summary
Aug 05, 2026
Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

9-10
Expected OA Rounds
78%
Grant Probability
99%
With Interview (+58.3%)
2y 8m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 342 resolved cases by this examiner. Grant probability derived from career allowance rate.

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