DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-14 and 16-19 are pending in this application. Claims 1 and 17-18 are currently amended; claims 2, 4, 7-12, 14 and 16 are original; claims 3, 5-6 and 13 are previously presented; claim 19 is new; claim 15 is canceled.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 and 16-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “wherein the data processing apparatus is configured to control the clock signal provided to the multiplier arrays to select which of the multiplier arrays is activated based on a data type on which multiplication is to be performed by the data processing apparatus” in lines 17-20. This limitation is unclear because it merely states a function (that the data processing apparatus must somehow control the clock signal provided to the multiplier arrays to select which of the multiplier arrays is activated based on a data type on which multiplication is to be performed) that is not performed by any structure recited in the claim. The recited function does not follow from the structure recited in the claim, i.e., the plurality of multiplier arrays, and the addition circuitry, so it is unclear whether the function requires some other structure or is simply a result of operating the apparatus in a certain manner. Further, clarification is required. Examiner suggest reciting the specific structure of the data processing apparatus configured to perform the claimed functions instead of the overall apparatus. See MPEP 2173.05(g) for more information. Claims 2-14 and 16-19 inherit the same deficiency as claim 1 by reason of dependence.
Further, claim 17 recites “the clock signal” in line 17. It is unclear whether this is supposed to be interpreted to the first clock signal, the second clock signal or to both. For purposes of examination, this is interpreted as “clock signals” instead. Claims 17-18 recite a similar limitation and are rejected for the same reason. Claims 2-14 and 16-19 inherit the same deficiency as claim 1 by reason of dependence.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-11 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Shekhar et al. (US 20210157603 A1), hereinafter Shekhar, in view of Tannenbaum et al. (US 20150169289 A1), hereinafter Tannenbaum.
Regarding claim 1, Shekhar teaches a data processing apparatus comprising a plurality of multiplier arrays (Shekhar Fig. 4 and paragraph [0035] plurality of multiplier arrays – 410-413) including:
an AxB multiplier array comprising a first plurality of logic gates clocked by a first clock signal, where A and B are both integers (Shekhar Figs. 2 and 4a, paragraphs [0016-0017, 0020, 0034] AxB multiplier array – one of multipliers 410-413; first plurality of logic gates – AND gates in the one of the multipliers 410-413; first clock signal – clock signal supplied to the one of the multipliers 410-413);
a CxD multiplier array, separate from the AxB multiplier array, comprising a second plurality of logic gates clocked by a second clock signal, where C and D are both integers (Shekhar Figs. 2 and 4a, paragraphs [0016-0017, 0020, 0034] CxD multiplier array – another one of multipliers 410-413; second plurality of logic gates – AND gates in the another one of the multipliers 410-413; second clock signal – clock signal supplied to the another one of the multipliers 410-413); and
addition circuitry configured to perform an addition operation between a first at least partial product produced by the AxB multiplier array and a second at least partial product produced by the CxD multiplier array (Shekhar Figs. 3 and 4B and paragraphs [0027, 0038] addition circuitry - the partial product compression circuitry 300 and the blocks or cells of the multiplier circuitry 400B).
Shekhar does not explicitly teach wherein the data processing apparatus is operable in a first mode with the AxB multiplier array activated and the CxD multiplier array deactivated to perform a multiplication of a first size, and operable in a second mode with the AxB multiplier array and the CxD multiplier array activated to perform a multiplication of a second larger size; wherein the data processing apparatus is configured to control the clock signal provided to the multiplier arrays to select which of the multiplier arrays is activated based on a data type on which multiplication is to be performed by the data processing apparatus.
However, on the same field of endeavor, Tannenbaum discloses a data processing apparatus comprising a plurality of multiplier arrays; wherein the data processing apparatus is operable in a first mode with a first multiplier array activated and a second multiplier array deactivated to perform a multiplication of a first size, and operable in a second mode with the first multiplier array and the second multiplier array activated to perform a multiplication of a second larger size; wherein the data processing apparatus is configured to select which of the multiplier arrays is activated based on a data type on which multiplication is to be performed by the data processing apparatus (Tannenbaum Figs. 2A-3B and paragraphs [0026-0028] “A first operating mode performs a 32-bit floating-point multiply-accumulate (MAC) operation using three 32-bit floating-point input operands … A second operating mode performs two 16-bit floating-point multiply-accumulate (MAC) operations using six 16-bit floating-point input operands that are encoded in three 32-bit input operands … A third operating mode performs a 16-bit floating-point sum of two products (dot-product, DP) operation using four 16-bit floating-point input operands that are encoded in the two 32-bit input operands”; paragraph [0036] “A configuration unit 210 receives the operating mode and generates control signal(s) 215 that are used to configure the various units within the dual-mode floating-point arithmetic unit 200 differently to perform 32-bit floating-point operations or 16-bit floating-point operations and/or to perform MAC or DP operations”; paragraph [0051] “When the dual-mode multiplier array unit 250 is configured to perform 32-bit floating-point multiplication, the entire circuit is needed. However, when the dual-mode multiplier array unit 250 is configured to perform 16-bit floating-point multiplication, the dual-mode multiplier array unit 250 is effectively separated into four quadrants, two of which are used to perform the 16-bit floating-point multiplication operations … The logic circuitry within the dual-mode multiplier array unit 250 that is not used when the dual-mode multiplier array unit 250 is configured to perform 16-bit floating-point multiplication may be disabled to reduce power consumption”; paragraphs [0053-0056]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Shekhar using Tannenbaum and configure the multiplier circuitry of Shekhar as a dual-mode multiplier array by separating the multiplier circuitry into four quadrants (multiplier arrays ) similar to the configuration shown in Fig. 4a of Shekhar with one/two of which are used to perform one/two independent 4-bit multiplications while the other quadrants (multiplier arrays) are deactivated in a first mode; and activating all four quadrants (multiplier arrays) to perform the 8-bit multiplication in a second mode. Furthermore, configure the multiplier circuitry to control the clock signal provided to each quadrant (multiplier array) based on the precision of the operands in order to gate/disable quadrants (multiplier arrays) not being used in the current multiplication operation to reduce power consumption (Tannenbaum paragraph [0051]). Shekhar paragraph [0017] discloses clock gating three out of the four 4x4 multipliers when the operands are 4-bit numbers. Therefore, the multiplier circuitry of Shekhar can be configured as a dual-mode multiplier array for performing 4-bit and 8-bit multiplications.
Therefore, the combination of Shekhar as modified in view of Tannenbaum teaches wherein the data processing apparatus is operable in a first mode with the AxB multiplier array activated and the CxD multiplier array deactivated to perform a multiplication of a first size, and operable in a second mode with the AxB multiplier array and the CxD multiplier array activated to perform a multiplication of a second larger size; wherein the data processing apparatus is configured to control the clock signal provided to the multiplier arrays to select which of the multiplier arrays is activated based on a data type on which multiplication is to be performed by the data processing apparatus.
Regarding claim 2, Shekhar as modified in view of Tannenbaum teaches all the limitations of claim 1 as stated above. Further, Shekhar as modified in view of Tannenbaum teaches wherein in an AxB mode of operation, the first clock signal operates at a higher frequency than the second clock signal (Shekhar paragraphs [0016-0017] AxB mode of operation – AxB multiplier is not gated while CxD multiplier is gated).
Regarding claim 3, Shekhar as modified in view of Tannenbaum teaches all the limitations of claim 2 as stated above. Further, Shekhar as modified in view of Tannenbaum teaches wherein in the AxB mode of operation, the first clock signal is such that the addition operation includes the first at least partial product and excludes the second at least partial product (Shekhar paragraph [0017]).
Regarding claim 4, Shekhar as modified in view of Tannenbaum teaches all the limitations of claim 1 as stated above. Further, Shekhar as modified in view of Tannenbaum teaches wherein in a CxD mode of operation, the second clock signal operates at a higher frequency than the first clock signal (Shekhar paragraphs [0016-0017] CxD mode of operation – CxD multiplier is not gated while AxB multiplier is gated).
Regarding claim 5, Shekhar as modified in view of Tannenbaum teaches all the limitations of claim 4 as stated above. Further, Shekhar as modified in view of Tannenbaum teaches wherein in the CxD mode of operation, the second clock signal is such that the addition operation excludes the first at least partial product and includes the at least second partial product (Shekhar paragraph [0017]).
Regarding claim 6, Shekhar as modified in view of Tannenbaum teaches all the limitations of claim 1 as stated above. Further, Shekhar as modified in view of Tannenbaum teaches wherein in a combined mode of operation, the first clock signal and the second clock signal operate at frequencies such that the addition operation includes the first at least partial product and the second at least partial product (Shekhar Figs. 4B-4C and paragraphs [0035-0038 and 0040]; combined mode of operation – 8x8 multiplication using four 4x4 multipliers).
Regarding claim 8, Shekhar as modified in view of Tannenbaum teaches all the limitations of claim 6 as stated above. Further, Shekhar as modified in view of Tannenbaum teaches wherein in the combined mode of operation, the AxB multiplier array and the CxD multiplier array cooperate to perform an MxN multiplication where M=A+C and N=B+D (Shekhar Fig. 4A and paragraphs [0034-0038]).
Regarding claim 9, Shekhar as modified in view of Tannenbaum teaches all the limitations of claim 6 as stated above. Further, Shekhar as modified in view of Tannenbaum teaches wherein in the combined mode of operation, A bits of a first operand are processed by the AxB multiplier array, B bits of a second operand are processed by the AxB multiplier array, C bits of the first operand are processed in the CxD multiplier array, and D bits of the second operand are processed in the CxD multiplier array (Shekhar Fig. 4A and paragraphs [0034 and 0036-0037]).
Regarding claim 10, Shekhar as modified in view of Tannenbaum teaches all the limitations of claim 6 as stated above. Further, Shekhar as modified in view of Tannenbaum teaches wherein in the combined mode of operation, an upper A bits of a first operand and a lower B bits of a second operand are processed in the AxB multiplier array, and a lower C bits of the first operand and an upper D bits of the second operand are processed in the CxD multiplier array (Shekhar Fig. 4a and paragraphs [0036-0037] AxB multiplier array – 410 which processes A[7:4]*b[3:0]; CxD multiplier array – 413 which processes A[3:0]*B[7:4]; first operand – A; second operand – B).
Regarding claim 11, Shekhar as modified in view of Tannenbaum teaches all the limitations of claim 6 as stated above. Further, Shekhar as modified in view of Tannenbaum teaches comprising: an ExF multiplier array, separate from the AxB multiplier array and the CxD multiplier array, comprising a third plurality of logic gates clocked by a third clock signal, where E and F are both integers (Shekhar Figs. 2 and 4A, paragraphs [0016-0017, 0020, 0034] ExF multiplier array – different one of multipliers 410-413 different from the AxB and CxD multiplier; third plurality of logic gates – AND gates in the different one of the multipliers 410-413; third clock signal – clock signal supplied to the different one of the multipliers 410-413).
Regarding claim 17, it is directed to a method practiced by the apparatus of claim 1. All steps performed by the method of claim 17 would be practiced by the apparatus of claim 1. Claim 1analysis applies equally to claim 17.
Regarding claim 18, it is directed to a non-transitory computer-readable medium to store computer-readable code for fabricating the apparatus of claim 1. Claim 1 analysis applies equally to claim 18.
Claims 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Shekhar in view of Tannenbaum as applied to claims 11 and 1 above, and further in view of Langhammer et al. (US 7,698,358 B1), hereinafter Langhammer.
Regarding claim 12, Shekhar as modified in view of Tannenbaum teaches all the limitations of claim 11 as stated above.
Shekhar does not explicitly teach wherein the CxD multiplier array and the ExF multiplier array are multiplier array fragments and are non-square.
However, on the same field of endeavor, Langhammer discloses a first multiplier and a second multiplier that are multiplier array fragments and are non-square (Langhammer Fig. 5 and col 7 lines 39-44 and col 8 lines 34-37; multiplier array – multipliers 516 and 616 which are 6x18 multipliers).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Shekhar using Langhammer and configure the CxD multiplier array and the ExF multiplier array as multiplier array fragments that are non-square in order to perform a more efficient multiplication operation with non-power-of-two input operands (Langhammer col 8 lines 61-65).
Therefore, the combination of Shekhar as modified in view of Tannenbaum and Langhammer teaches wherein the CxD multiplier array and the ExF multiplier array are multiplier array fragments and are non-square.
Regarding claim 16, Shekhar as modified in view of Tannenbaum teaches all the limitations of claim 1 as stated above. Further, Shekhar as modified in view of Tannenbaum teaches wherein the addition circuitry comprises first addition circuit for combining a first combination of at least partial products and a second addition circuit for combining a second combination of at least partial products (Shekhar Figs. 3-4B and paragraphs [0027, 0038] first addition circuit –partial product compression circuitry; second addition circuit – multiplier circuitry 400B).
Shekhar does not explicitly teach wherein the addition circuitry comprises first addition circuit for combining a first combination of at least partial products and a second addition circuit for combining a second combination of at least partial products in dependence on a selection signal.
However, on the same field of endeavor, Langhammer discloses an addition circuitry comprising first addition circuit for combining a first combination of at least partial products and a second addition circuit for combining a second combination of at least partial products in dependence on a selection signal (Langhammer Fig. 1 and col 4 lines 46-55; first addition circuit – first level adders 15 and 16; second addition circuit – second level adder 17; selection signal – multiplexer selection signal).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Shekhar using Langhammer and include multiplexers between the partial product compression circuitry and the multiplier circuitry 400B to allow the output of each partial product compression circuitry to be output directly when performing independent multiplication or to be provided to the multiplier circuitry 400B to be added together based on a selection signal input to the multiplexer (Langhammer col 4 lines 46-48).
Therefore, the combination of Shekhar as modified in view of Tannenbaum and Langhammer teaches wherein the addition circuitry comprises first addition circuit for combining a first combination of at least partial products and a second addition circuit for combining a second combination of at least partial products in dependence on a selection signal.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Shekhar in view of Tannenbaum as applied to claim 11 above, and further in view of Leung et al. (US 8,307,023 B1), hereinafter Leung.
Regarding claim 13, Shekhar as modified in view of Tannenbaum teaches all the limitations of claim 11 as stated above. Further, Shekhar as modified in view of Tannenbaum teaches wherein in the combined mode of operation, the AxB multiplier array and the CxD multiplier array and the ExF multiplier array cooperate to perform the MxN multiplication (Shekhar Fig. 4A and paragraphs [0034-0038]).
Shekhar does not explicitly teach where M=A+C+E and N=B+D+F.
However, on the same field of endeavor, Leung discloses performing an MxN multiplication where M=A+C+E and N=B+D+F (Leung Fig. 2 and col 5 lines 38-65; MxN multiplication – SxT multiplication where S= A3|A2|A1 and T = B3|B2|B1).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Shekhar using Leung and configure the apparatus to perform an MxN multiplication where M=A+C+E and N=B+D+F in order to be able to implement higher precision multiplication operation using lower precision multipliers by decomposing the multiplication operation into smaller sub-multiplication operations (Leung col 5 lines 50-65).
Therefore, the combination of Shekhar as modified in view of Tannenbaum and Leung teaches wherein in the combined mode of operation, the AxB multiplier array and the CxD multiplier array and the ExF multiplier array cooperate to perform the MxN multiplication where M=A+C+E and N=B+D+F.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Shekhar in view of Tannenbaum and Leung as applied to claim 13 above, and further in view of Langhammer.
Regarding claim 14, Shekhar as modified in view of Tannenbaum and Leung teaches all the limitations of claim 13 as stated above.
Shekhar does not explicitly teach wherein M and N are both 24.
However, on the same field of endeavor, Langhammer discloses performing a 24-bit-by-24-bit multiplication that is decomposed into smaller multiplications (Langhammer Figs. 4-5 and col 5 line 61 to col 6 line 7).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Shekhar using Langhammer and configure the apparatus to perform the 24-bit-by-24-bit multiplication using 8x8 multipliers to construct the 24x24 multiplier in order to implement higher precision multiplication operation using lower precision multipliers by decomposing the multiplication operation into smaller sub-multiplication operations (Leung col 5 lines 50-65). Furthermore, decomposing a larger multiplication into smaller multiplication operations is well-known in the art (Langhammer col 5 lines 4-6).
Therefore, the combination of Shekhar as modified in view of Tannenbaum, Leung and Langhammer teaches wherein M and N are both 24.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Shekhar as modified in view of Tannenbaum as applied to claim 6 above, and further in view of Gopal et al. (US 20080140753 A1), hereinafter Gopal.
Regarding claim 7, Shekhar as modified in view of Tannenbaum teaches all the limitations of claim 6 as stated above. Further, Shekhar as modified in view of Tannenbaum wherein in the combined mode of operation, the first clock signal and the second clock signal operate at a (Shekhar paragraphs [0035-0036]).
Shekhar does not explicitly teach wherein in the combined mode of operation, the first clock signal and the second clock signal operate at a same frequency.
However, on the same field of endeavor, Gopal discloses a first and second multiplier operating at a same frequency (Gopal paragraphs [0016, 0032]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Shekhar using Gopal and configure the multipliers to operate at the same frequency in order to simultaneously determine the partial products and increase performance (Gopal paragraphs [0014, 0032]).
Therefore, the combination of Shekhar as modified in view of Tannenbaum and Gopal teaches wherein in the combined mode of operation, the first clock signal and the second clock signal operate at a same frequency.
Allowable Subject Matter
Claim 19 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to overcome the 35 U.S.C. 112(b) rejection discussed above.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art references cited explicitly teach or suggest, in combination with other limitation of the claims, the concept of a 24-bit-by24-bit multiplier comprising at least three 8x8 multiplier arrays, at least two 11x11 multiplier arrays, at least one 2x11 multiplier array, and at least one 24x5 multiplier array. Therefore, none of the prior art references cited explicitly teach or suggest “wherein the plurality of multiplier arrays comprises at least three 8x8 multiplier arrays, at least two 11x11 multiplier arrays, at least one 2x11 multiplier array, and at least one 24x5 multiplier array such that at least one combination of a plurality of the multiplier arrays is 24x24, the combination comprising the at least three 8x8 multiplier arrays, the at least two 11x11 multiplier arrays, the at least one 2x11 multiplier array, and the at least one 24x5 multiplier array” as recited in claim 19.
Response to Arguments
Applicant’s arguments, see remarks page 7-9, filed 08/12/2026, with respect to the rejection(s) of claim(s) 1-14 and 16-18 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of amendments made and previously cited prior art references.
Applicant argues the following:
A.) None of the prior art references cited teach or suggest the controlling of a clock signal to selectively activate the multiplier arrays based on a data type on which multiplication is to be performed because Shekhar’s gating signal is based on the data values being multiplied (e.g., if certain portions of them are zeroes) rather than a data type to be multiplied.
Response: Examiner agrees in part. Examiner agrees that paragraph [0015] of Shekhar discloses using the values of the multiplier and multiplicand to generate the gating signal. However, paragraph [0017] of Shekhar discloses in part “in reference to FIG. 1, an 8x8 multiplier may be implemented using four 4x4 multipliers, and when the input weight and feature are only 4-bit numbers (i.e., less than 15), the input to three out of the four 4x4 multipliers may be gated, thus reducing activity in that section of the multiplier to zero”. Therefore, Shekhar also discloses gating the multipliers based on the data type. Furthermore, Tannenbaum discloses a data processing apparatus comprising a plurality of multiplier arrays; wherein the data processing apparatus is operable in a first mode with a first multiplier array activated and a second multiplier array deactivated to perform a multiplication of a first size, and operable in a second mode with the first multiplier array and the second multiplier array activated to perform a multiplication of a second larger size; wherein the data processing apparatus is configured to select which of the multiplier arrays is activated based on a data type on which multiplication is to be performed by the data processing apparatus in Figs. 2A-3B and paragraphs [0026-0028, 0036, 0051 and 0053-0056]. Therefore, it would have been obvious to combine Shekhar and Tannenbaum and configure the multiplier circuitry of Shekhar as a dual-mode multiplier array that can be used to perform 4-bit and 8-bit multiplications; and gating the clock signal to each multiplier array not being used in the 4-bit multiplication mode to reduce power consumption (Tannenbaum paragraph [0051] and Shekhar paragraph [0017]). Therefore, the combination of Shekhar and Tannenbaum teaches wherein the data processing apparatus is operable in a first mode with the AxB multiplier array activated and the CxD multiplier array deactivated to perform a multiplication of a first size, and operable in a second mode with the AxB multiplier array and the CxD multiplier array activated to perform a multiplication of a second larger size; wherein the data processing apparatus is configured to control the clock signal provided to the multiplier arrays to select which of the multiplier arrays is activated based on a data type on which multiplication is to be performed by the data processing apparatus.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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