DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the RCE and amendment filed on 6/11/2026.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/11/2026 has been entered.
Claims 1-5, 8-10, 12-13, 16-18, 20-21, and 24 have been amended.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/11/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
In view of the amendment to claims 1, 3-5, 9, 12-13, 17, and 20-21, replacing “first logic” and “second logic” with “circuit” the claims now recite sufficient structure to entirely perform the recited functions and interpretation under 35 U.S.C. 112(f) is no longer invoked.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-6, 9-14, and 17-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2023/0289291), Ranganathan et al. (US 2021/0149763), Gu et al. (US 2021/0397934), and Talukdar et al. (US 2016/0239422).
With respect to claim 1, Lee teaches of an apparatus comprising: a plurality of compute units to perform machine learning operations (fig. 3, items 314; paragraph 49-50; where each of the neural engines performs machine learning operations);
a cache subsystem comprising a hierarchy of cache levels, at least some of the cache levels shared by two or more of the plurality of compute units (fig. 2-3, item 240, 334; paragraph 35, 50, 53, 55-56, 61; buffer 334 and cache circuit makeup the claimed cache hierarchy of cache levels. The cache circuit caches data from the system memory for faster access by the neural processor circuit. The buffer stores data input and output to/from the neural engines. As the neural engines perform operations on the data, the buffer and cache can be considered to be shared by the neural engines); and
a circuit to stream machine learning data in and out of the cache subsystem based on the machine learning operations (fig. 3, 6; paragraph 55-56, 61, 85-94; where the data processor circuit, cache access circuit and system memory access circuit prefetch large datasets from the system memory into the cache to more efficiently utilize the available bandwidth, which are then loaded into the buffer to be input to the neural engines and output data from the neural engines to the buffer),
the circuit to load data into the cache subsystem from memory before the data is needed by a first portion of the machine learning operations (fig. 3, 6; paragraph 61, 85-94; where the cache access circuit and system memory access circuit prefetch large datasets from the system memory into the cache to more efficiently utilize the available bandwidth) and
Lee fails to explicitly teach of (1), each compute unit of the plurality of compute units to execute a thread in a thread group to perform single instruction, multiple threads (SIMT) operations (2) wherein results produced by the first portion of the machine learning operations are maintained in the cache subsystem until being used by a second portion of the machine learning operations.
However, Ranganathan teaches of each compute unit of the plurality of compute units to execute a thread in a thread group to perform single instruction, multiple threads (SIMT) operations (fig. 2c; paragraph 67, 68, 167; where each processing cluster supports SIMT in order to enable parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each one of the processing clusters);
The combination of Lee and Ranganathan teaches of a cache subsystem comprising a hierarchy of cache levels, at least some of the cache levels shared by threads executed on two or more of the plurality of compute units (Lee, fig. 2-3, item 240, 334; paragraph 35, 50, 53, 55-56, 61; Ranganathan, fig. 2c; paragraph 67, 68, 167; where in the combination, the cache system of Lee is used in the execution of threads of Ranganathan).
The combination of Lee and Ranganathan fails to explicitly teach of wherein results produced by the first portion of the machine learning operations are maintained in the cache subsystem until being used by a second portion of the machine learning operations.
However, Gu teaches of wherein results produced by the first portion of the machine learning operations are maintained in the cache subsystem until being used by a second portion of the machine learning operations (fig. 2; paragraph 25-26; where the results of the first layer calculations are retained in the cache memory until after second layer calculations on those results are performed).
The combination of Lee, Ranganathan, and Gu fails to explicitly teach of wherein maintaining the results produced by the first portion causes corresponding cache lines to be excluded from cache replacement operations.
However, Talukdar teaches of wherein maintaining the results produced by the first portion causes corresponding cache lines to be excluded from cache replacement operations (paragraph 38; where when a cache line is locked, the replacement selection does not select that particular cache line for replacement and checks the next cache line).
Lee and Ranganathan are analogous art because they are from the same field of endeavor, as they are directed to caching data used in machine learning.
It would have been obvious to one of ordinary skill in the art having the teachings of Lee and Ranganathan before the time of the effective filing of the claimed invention to implement the SIMT of Ranganathan into the neural engines of Lee. Their motivation would have been to increase processing efficiency (Ranganathan, paragraph 167).
Lee, Ranganathan, and Gu are analogous art because they are from the same field of endeavor, as they are directed to caching data used in machine learning.
It would have been obvious to one of ordinary skill in the art having the teachings of Lee, Ranganathan, and Gu before the time of the effective filing of the claimed invention to retain the results of the operation in the cache until they are used by a later operation in the combination of Lee and Ranganathan as taught in Gu. Their motivation would have been to more efficiently utilize the cache and processing resources via minimizing data transmission between the cache and main memory (Gu; paragraph 5-6, 9).
Lee, Ranganathan, Gu, and Talukdar are analogous art because they are from the same field of endeavor, as they are directed to caching data.
It would have been obvious to one of ordinary skill in the art having the teachings of Lee, Ranganathan, Gu, and Talukdar before the time of the effective filing of the claimed invention to use the lock bits of Talukdar to ensure that the data is locked in the cache and not replaced in the combination of Lee, Ranganathan, and Gu as taught in Talukdar. Their motivation would have been to more efficiently manage the cache lines.
With respect to claim 9, the combination of Lee, Ranganathan, Gu, and Talukdar teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
With respect to claim 17, the combination of Lee, Ranganathan, Gu, and Talukdar teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
The combination of Lee, Ranganathan, Gu, and Talukdar also teaches of a non-transitory machine-readable medium having program code stored thereon which when executed by a machine, causes the machine to perform the operations of claim 1 (Lee, 27, 87, 105-106; Gu, paragraph 47-48; where code is compiled and executed to carry out the operations. Since the code is compiled and executed, it must be stored in a memory in order for compilation and execution to occur).
The reasons for obviousness are the same as indicated above with respect to claim 1.
With respect to claims 2, 10, and 18, Lee teaches of wherein the first portion of the machine learning operations comprises a forward-propagation sequence of operations to produce activation results (paragraph 42-48; where forward propagation occurs with an activation function that weights the output of the node) and
the second portion of the machine learning operations comprise a back-propagation sequence of operations which are to use the activation results (paragraph 42-48; where back propagation is performed on the results to adjust the coefficients in order to improve the value of the loss function).
With respect to claims 3, 11, and 19, the combination of Lee, Ranganathan, Gu, and Talukdar teaches of wherein the circuit is to cause the activation results to be flushed from the cache subsystem following use by the back-propagation sequence of operations (Gu, fig. 2; paragraph 25-26; where after the second calculation is completed (back propagation of Lee), the first calculation result retained in the cache is invalidated).
The reasons for obviousness are the same as indicated above with respect to claim 1.
With respect to claims 4, 12, and 20, Lee teaches of wherein the circuit is to be programmed to stream the machine learning data in and out of the cache subsystem (fig. 3, 6; paragraph 53, 55-56, 61, 85-94; where the neural task manager, data processor circuit, cache access circuit and system memory access circuit prefetch large datasets from the system memory into the cache to more efficiently utilize the available bandwidth, which are then loaded into the buffer to be input to the neural engines and output data from the neural engines to the buffer).
With respect to claims 5, 13, and 21, Lee teaches of wherein one or more commands are issued to the circuit to cause the circuit to stream the machine learning data in and out of the cache subsystem (fig. 3, 6; paragraph 53, 55-56, 61, 85-94; where the neural task manager, data processor circuit, cache access circuit and system memory access circuit prefetch large datasets from the system memory into the cache to more efficiently utilize the available bandwidth, which are then loaded into the buffer to be input to the neural engines and output data from the neural engines to the buffer. The neural task manager issues commands for the prefetching and the other operations that are to occur within the neural processor circuit).
With respect to claims 6, 14, and 22, Lee teaches of wherein the one or more commands are to indicate a particular set of data to be prefetched or maintained in the cache subsystem (fig. 6; paragraph 53, 85-90; where the instructions indicate to prefetch the second input data of the second task).
Claim(s) 7, 15, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Gu, and O’Connor as applied to claims 6, 14, and 22 above, and further in view of Moyer (US 20210182214).
With respect to claims 7, 15, and 23 the combination of Lee, Ranganathan, Gu, and Talukdar fails to explicitly teach of wherein the one or more commands are to further indicate a particular cache level in which to prefetch or maintain the particular set of data.
However, Moyer teaches of wherein the one or more commands are to further indicate a particular cache level in which to prefetch or maintain the particular set of data (paragraph 23; where the instructions can include explicit instructions to prefetch certain data to a particular specified level of cache).
Lee, Ranganathan, Gu, Talukdar, and Moyer are analogous art because they are from the same field of endeavor, as they are directed to caching.
It would have been obvious to one of ordinary skill in the art having the teachings of Lee, Ranganathan, Gu, Talukdar, and Moyer before the time of the effective filing of the claimed invention to incorporate the specifying the cache level to prefetch data into in the combination of Lee, Ranganathan, Gu, and Talukdar as taught in Moyer. Their motivation would have been to increase the flexibility and control over the caching of data.
Claim(s) 8, 16, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Gu, O’Connor, and Moyer as applied to claims 7, 15, and 23 above, and further in view of Favela et al. (US 2020/0174761).
With respect to claims 8, 16, and 24 the combination of Lee, Gu, O’Connor, and Moyer fails to explicitly teach of wherein the cache subsystem comprises a Level 2 (L2) cache, a Level 1(L1) cache, and a Level 0 (L0) cache.
However, Favela teaches of wherein the cache subsystem comprises a Level 2 (L2) cache, a Level 1(L1) cache, and a Level 0 (L0) cache, and wherein the shared cache is a L2 cache (fig. 1; paragraph 14; where L0 is a private cache in each compute unit and L1 and L3 are shared among the compute units).
Lee, Ranganathan, Gu, Talukdar, Moyer and Favela are analogous art because they are from the same field of endeavor, as they are directed to caching.
It would have been obvious to one of ordinary skill in the art having the teachings of Lee, Ranganathan, Gu, Talukdar, Moyer, and Favela before the time of the effective filing of the claimed invention to incorporate the L0, L1, and L2 caches of Favela into the cache system of the combination of Lee, Ranganathan, Gu, Talukdar, and Moyer. Their motivation would have been to reduce the latency in accessing stored information.
Response to Arguments
Applicant’s arguments with respect to claim(s) independent claims 1, 9, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 6/11/2026 have been fully considered but they are not persuasive.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
In this case, Lee and Ranganathan are analogous art because they are from the same field of endeavor, as they are directed to caching data used in machine learning. It would have been obvious to one of ordinary skill in the art having the teachings of Lee and Ranganathan before the time of the effective filing of the claimed invention to implement the SIMT of Ranganathan into the neural engines of Lee. Their motivation would have been to increase processing efficiency (Ranganathan, paragraph 167).
Lee, Ranganathan, and Gu are analogous art because they are from the same field of endeavor, as they are directed to caching data used in machine learning. It would have been obvious to one of ordinary skill in the art having the teachings of Lee, Ranganathan, and Gu before the time of the effective filing of the claimed invention to retain the results of the operation in the cache until they are used by a later operation in the combination of Lee and Ranganathan as taught in Gu. Their motivation would have been to more efficiently utilize the cache and processing resources via minimizing data transmission between the cache and main memory (Gu; paragraph 5-6, 9).
Lee, Ranganathan, Gu, and Talukdar are analogous art because they are from the same field of endeavor, as they are directed to caching data. It would have been obvious to one of ordinary skill in the art having the teachings of Lee, Ranganathan, Gu, and Talukdar before the time of the effective filing of the claimed invention to use the lock bits of Talukdar to ensure that the data is locked in the cache and not replaced in the combination of Lee, Ranganathan, and Gu as taught in Talukdar. Their motivation would have been to more efficiently manage the cache lines.
Thus, the combination of Lee, Ranganathan, Gu, and Talukdar is proper and reads on the limitations at issue as detailed in the rejections set forth above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Puthoor et al. (US 2021/0173796) discloses a memory hierarchy including local L0 caches, global data shares, and shared L1 and L2 caches.
Rajamony et al. (US 2011/0022773) discloses cache line locking where the lock bit for the cache line(s) prevents the cache line from being replaced by the cache controller.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138
/Michael Krofcheck/Primary Examiner, Art Unit 2138
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