Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 8/19/2025 have been fully considered but they are not persuasive.
With respect to claim 1, Applicant argues, “
However, as shown above, the dies 114 of Chiu are disposed over the fan-out portion 104 of Chiu, not in the fan-out portion 104 of Chiu as claimed. Accordingly, Chiu is silent regarding the limitation “memory array regions in the memory interposer”, much less “wherein among the memory array regions, a number of the memory having NAND architecture is greater than a number of the volatile memory.
Remarks 8.
Applicant’s memory M1-M3 are in the interposer 210, see Applicant fig. 7b below left. In the same way the memory dies 102 are in the same outer coating 132 with the memory interposer 104, see Chiu fig. 1 below. Both Chiu and the claims have the memory in one silicon package.
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Applicant fig. 7b.
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Chiu fig. 1.
Further, Feng fig. 1 shows having two NAND and one volatile DRAM, see below.
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Therefore, the elements of Applcant’s claim 1 are taught by the prior art. The prior art is obvious to combine for the reasons stated in the rejection.
With respect to claim 11, Applicant argues, “However, as disclosed in paragraph [0079] of Chiu, the vertical interconnect portion 128 of Chiu is disposed on side surface of the memory die 114(6), not extending through the memory die 114(6) as claimed.” Remarks 11. Chiu has several arrangements for the interconnect. The interconnect 128 is through the second chip, see fig. 9b [906] below, which gives another view of how the “vertical interconnect 906” goes through dies. Chiu para 99.
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Therefore, the prior art teaches the claim element.
Claim Objections
Claim 21 is objected to because of the following informalities: “the memory having NAND architecture has volatile property.” It should probably be, has volatile properties”. Appropriate correction is required.
Claim 22 is objected to because of the following informalities: “wherein the memory having NAND architecture and the volatile memory at disposed at a same level in the memory interposer.” The word “at” should probably be are. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over US20180366429A1 to Chiu et al, US11694940B1 to Mathuriya et al, and US 20150339064 A1 to Feng et al.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US20180366429A1 to Chiu et al, US11694940B1 to Mathuriya et al, US 20150339064 A1 to Feng et al and US 20150171098 A1 to Simsek-Ege et al.
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over US20180366429A1 to Chiu et al, US11694940B1 to Mathuriya et al, US 20150339064 A1 to Feng et al, US 20150171098 A1 to Simsek-Ege et al and US 20140310445 A1 to Fitzpatrick et al
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over US20180366429A1 to Chiu et al, US11694940B1 to Mathuriya et al, US 20150339064 A1 to Feng et al, US 20150171098 A1 to Simsek-Ege et al, US 20140310445 A1 to Fitzpatrick et al and US 5602782 A to Akiyama et al.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US20180366429A1 to Chiu et al, US11694940B1 to Mathuriya et al, US 20150339064 A1 to Feng et al and TILE-Gx100 ManyCore Processor: Acceleration Interfaces and Architecture by Carl Ramey (TILE).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over US20180366429A1 to Chiu et al, US11694940B1 to Mathuriya et al, US 20150339064 A1 to Feng et al and US 20100296342 A1 to Takizawa et al.
Claims 11 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over US20180366429A1 to Chiu et al and US 20100296342 A1 to Takizawa et al.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over US20180366429A1 to Chiu et al, US 20100296342 A1 to Takizawa et al and US 20150171098 A1 to Simsek-Ege et al.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over US20180366429A1 to Chiu et al, US 20100296342 A1 to Takizawa et al, US 20150171098 A1 to Simsek-Ege et al and US 20140310445 A1 to Fitzpatrick et al.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US20180366429A1 to Chiu et al, US 20100296342 A1 to Takizawa et al, US 20150171098 A1 to Simsek-Ege et al, US 20140310445 A1 to Fitzpatrick et al and US 5602782 A to Akiyama et al.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over US20180366429A1 to Chiu et al, US11694940B1 to Mathuriya et al, US 20150339064 A1 to Feng et al and NAND-type DRAM-on-SGT by Nakamura et al.
Chiu teaches claim 1. A memory device, comprising:
a memory interposer; (Chiu fig 1 fan-out portion 104)
memory array regions in the memory interposer, wherein the memory array regions comprises at least one memory having NAND architecture and at least one volatile memory different from the memory having NAND architecture, and wherein among the memory array regions, a number of the memory having NAND architecture (Chiu para 57 “As described in further detail below, the dies 114 of the die stack 102 may be configured to communicate with the dies of the fan-out portion 104” Chiu para 61 “the multi-die stack structure 100 may be a volatile memory device or may be a component of a volatile memory device, such as a dynamic random access memory (“DRAM”) or a static random access memory (“SRAM”) device, a non-volatile memory device,… configured in a NAND or a NOR configuration.”)
logic chips(The die 124 are logic chips, see para 85 “controller die 124(1) may be configured to send both the first data set and the second data set to the routing fan-out die 124(2), “)
interconnection lines connecting the logic chips to each other and connecting the logic chips to the memory array regions. (Chiu para 40 “where the first die is configured as a controller for the plurality of memory dies and the second die is configured as a routing die configured to route signals in between the controller and the memory dies.” Chiu para 78 “shows a first vertical interconnect 126(1) vertically extending through the first fan-out die 124(1) and the second fan-out die 124(2)…”) Chiu doesn’t teach the number of NAND being greater than the volatile memory.
However, Feng teaches a number of the memory having NAND architecture is greater than a number of the volatile memory. (Feng abs “a first DRAM array, a first and a second NAND array…”)
Feng, Chiu and the claims are all memory devices. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to multiply the non-volatile elements because “this can give the impression of more available memory.” Feng para 8.
Chiu doesn’t teach the logic chips are over the memory interposer.
However, Mathuriya teaches logic chips over the memory interposer. (Mathuriya 21:37 “Each PE is above a corresponding memory unit cell.”)
Chen, Mathuriya and the claims are all memory devices. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to use Mathuriya’s architecture because it can “break up the memory of memory die 701 into as many channels as desired, and assists with increased bandwidth, lower latency, and lower access energy.” Mathuriya 21:40.
Chiu teaches claim 3. The memory device of claim 1, wherein the volatile memory is a DRAM. (Chiu para 61 “the dies 114 may be referred to as memory dies. As a semiconductor memory device, the multi-die stack structure 100 may be a volatile memory device or may be a component of a volatile memory device, such as a dynamic random access memory (“DRAM”)…”)
Chiu teaches claim 5. The memory device of claim 1, further comprising a controller chip (Chiu para 40 “where the first die is configured as a controller for the plurality of memory dies and the second die is configured as a routing die configured to route signals in between the controller and the memory dies.” Chiu para 61 “the dies 114 may be referred to as memory dies… configured in a NAND or a NOR configuration.”) Chiu doesn’t teach the controller chip is over the memory interposer, and it doesn’t teach a refresh operation.
However, Mathuriya teaches chip over the memory interposer. (Mathuriya 21:37 “Each PE is above a corresponding memory unit cell.”) refresh the memory. (Mathuriya 20:67 “refresh logic 826”)
Chiu teaches claim 6. The memory device of claim 1, wherein an endurance of the memory having NAND architecture is in a range (Chiu para 61 “NAND”). Chiu doesn’t teach endurance numbers for the NAND memory.
However, Simsek-Ege teaches a range from about 106 to about 1010. (Simsek-Ege para 37 “the 3D NAND memory structure can have a cycling endurance of from about 500 cycles to about 10,000 cycles…”)
Chen, Simsek-Ege and the claims are a 3D NAND memory. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to use lower endurance NAND memory “having an improved process margin and enhanced performance…” Simsek-Ege para 24.
Chiu teaches claim 7. The memory device of claim 6, wherein a retention of the memory having NAND architecture is in a range (Chiu para 61 “NAND”). Chiu doesn’t teach retention numbers for the NAND memory.
However, Fitzpatrick teaches a range from 1 second to about 1 year. (Fitzpatrick para 26 “Now that MLC NAND devices with P/E cycles with as little as 3,000 or less and retention of 3 months or less are being used, the need to recycling for data retention is critical.”)
Fitzpatrick, Chiu and the claims are all NAND memory. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to use low retention flash memory “to reduce costs…” Fitzpatrick para 5.
Chiu teaches claim 8. The memory device of claim 7, wherein a number of inputs/outputs of the memory having NAND architecture. (Chiu para 61 “NAND”). Chiu doesn’t teach numbers for the NAND memory.
However, Akiyama teaches input/outputs is equal to or greater than 1024. (Akiyama 6:40 “The data for the selected word line is read out of the memory array 11 and output onto two or more columns of bit lines, for example, 1024 columns.”)
Chen, Akiyama and the claims are memory devices. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to have more I/O for “easily realizing several kinds of multi-bit output arrangements.” Akiyama 1:31.
Chiu teaches claim 9. The memory device of claim 1, wherein each of the logic chips includes about (Chiu para 40 “where the first die is configured as a controller for the plurality of memory dies and the second die is configured as a routing die configured to route signals in between the controller and the memory dies.”) Chiu doesn’t teach 100 cores.
However, TILE teaches about 100 to about 104 cores. (TILE p. 3 title “System-on-a-Chip with 100 64-bit cores”)
Chen, TILE and the claims are all systems on chips. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to include 100 cores because it provides “required performance for complex operations…” TILE p. 4.
Chiu teaches claim 10. The memory device of claim 1, wherein the memory having NAND architecture comprises:
a bit line; (Chiu para 63 “bit line.)
word lines; (Chiu para 65 “The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.”)
memory units connected in series, wherein the word lines are electrically connected to the memory units, respectively; and (Chiu para 63 “flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series.” Chiu para 65 “The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.”)
(Chiu para 63 “ A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group.” Chiu para 60 “The die 200 may include various active and/or passive circuit elements such as transistors… The signal paths may extend horizontally and/or vertically be used to interconnect the other circuit elements, such as the transistors…”) Chiu doesn’t teach the transistor connection between the memory and bit line.
However, Takizawa teaches a transistor connecting one of the memory units to the bit line. (Takizawa fig. 2 bit line driver transistor.)
Chen, Takizawa and the claims are NAND memory. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to connect the bit lines with a transistor in the Takizawa way for “greatly shortening the test time.” Takizawa para 7.
Chiu teaches claim 11. A memory device, comprising:
a first memory chip; (Chiu fig. 1 memory die 114(7))
a second memory chip stacked over the first memory chip and electrically connected to the first memory chip, (Chiu fig. 1 memory die 114(6) wherein the first and second memory chips each comprises:
a bit line; (Chiu 65 “The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.”)
word lines; (Chiu 65 “The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.”)
memory units connected in series, wherein the word lines are electrically connected to the memory units, respectively; and (Chiu para 63 “(NAND memory) typically contain memory elements connected in series…” Chiu 65 “The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.”)
(Chiu para 63 “ A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group.” Chiu para 60 “The die 200 may include various active and/or passive circuit elements such as transistors… The signal paths may extend horizontally and/or vertically be used to interconnect the other circuit elements, such as the transistors…”)
a third memory chip stacked over the second memory chip, wherein the third memory chip is electrically connected to the first memory chip via through silicon vias vertically extending through the second memory chip. (Chiu para 88 “the vertical interconnect portion 128.” Chiu fig. 1 114(5) is the third memory. The interconnect 128 is through the second chip, see fig. 9b which gives another view of how the vertical interconnect 906 goes through dies.)
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Chiu doesn’t teach the transistor connection between the memory and bit line.
However, Takizawa teaches a transistor connecting one of the memory units to the bit line. (Takizawa fig. 2 bit line driver transistor.)
Chen, Takizawa and the claims are NAND memory. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to connect the bit lines with a transistor in the Takizawa way for “greatly shortening the test time.” Takizawa para 7.
Chiu teaches claim 16. The memory device of claim 11, wherein the third memory chip comprises a volatile memory. (Chiu para 61 “the dies 114 may be referred to as memory dies. As a semiconductor memory device, the multi-die stack structure 100 may be a volatile memory device or may be a component of a volatile memory device, such as a dynamic random access memory (“DRAM”)…”)
Chiu teaches claim 17. The memory device of claim 16, wherein the volatile memory is a DRAM. (Chiu para 61 “the dies 114 may be referred to as memory dies. As a semiconductor memory device, the multi-die stack structure 100 may be a volatile memory device or may be a component of a volatile memory device, such as a dynamic random access memory (“DRAM”)…”)
Chiu teaches claim 18. The memory device of claim 11, wherein an endurance of the first memory chip is in a range (Chiu para 61 “NAND”). Chiu doesn’t teach endurance numbers for the NAND memory.
However, Simsek-Ege teaches a range from about 106 to about 1010. (Simsek-Ege para 37 “the 3D NAND memory structure can have a cycling endurance of from about 500 cycles to about 10,000 cycles…”)
Chen, Simsek-Ege and the claims are a 3D NAND memory. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to use lower endurance NAND memory “having an improved process margin and enhanced performance…” Simsek-Ege para 24.
Chiu teaches claim 19. The memory device of claim 18, wherein a retention of the first memory chip is in a range (Chiu para 61 “NAND”). Chiu doesn’t teach retention numbers for the NAND memory.
However, Fitzpatrick teaches a range from 1 second to about 1 year. (Fitzpatrick para 26 “Now that MLC NAND devices with P/E cycles with as little as 3,000 or less and retention of 3 months or less are being used, the need to recycling for data retention is critical.”)
Fitzpatrick, Chiu and the claims are all NAND memory. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to use low retention flash memory “to reduce costs…” Fitzpatrick para 5.
Chiu teaches claim 20. The memory device of claim 19, wherein a number of inputs/outputs of the first memory chip (Chiu para 61 “NAND”). Chiu doesn’t teach numbers for the NAND memory.
However, Akiyama teaches input/outputs is equal to or greater than 1024. (Akiyama 6:40 “The data for the selected word line is read out of the memory array 11 and output onto two or more columns of bit lines, for example, 1024 columns.”)
Chen, Akiyama and the claims are memory devices. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to have more I/O for “easily realizing several kinds of multi-bit output arrangements.” Akiyama 1:31.
Chiu teaches claim 21. (New) The memory device of claim 1, wherein the memory having NAND architecture(Chiu para 61 “the multi-die stack structure 100 may be a volatile memory device or may be a component of a volatile memory device, such as a dynamic random access memory (“DRAM”)…) Chiu doesn’t teach a NAND with a volatile property.
However, Nakamura teaches NAND architecture has volatile property. (Nakamura abs. “a novel NAND-type DRAM-on-surrounding-gate transistor (SGT)architecture for high-density and low-voltage memory.”)
Nakamura, the claims and Chiu all teach volatile memory. It would have been obvious to a person having ordinary skill in the art, at the time of filing, to use a NAND architecture in volatile memory “for high-density and low-voltage memory.” Nakamura abs.
Chiu teaches claim 22. (New) The memory device of claim 1, wherein the memory having NAND architecture and the volatile memory at disposed at a same level in the memory interposer. (Chiu fig 1 fan-out portion 104 (interposer) is in the same vertical level as the memory die 102. The memory die are volatile and NAND, see Chiu para 61.)
Chiu teaches claim 23. (New) The memory device of claim 1, wherein the interconnection lines are embedded in the memory interposer. (Chiu fig. 1 Interconnection 128 is in the memory interposer 104)
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AUSTIN HICKS/Primary Examiner, Art Unit 2124