Detailed Action
The instant application having Application No. 17/700,651 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the claims filed 2/17/26. Claims 1-20 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/17/26 has been entered.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-7, 10-11 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Li (U.S. Patent Application Publication No. 2022/0206915), herein referred to as Li in view of Alwala (U.S. Patent Application Publication No. 2021/0365200), herein referred to as Alwala and in view of Agombar et al. (U.S. Patent Application Publication No. 2017/0315745), herein referred to as Agombar et al. and in view of Nakanishi et al. (U.S. Patent Application Publication No. 2010/0017557), herein referred to as Nakanishi et al.
Referring to claim 1, Li discloses as claimed, A method, comprising: receiving, by a controller of a storage device from a host, a write command and a write data (see fig. 1b, showing a host sending read/write commands to a storage device. Also see para. 46. See fig. 2b showing superblocks being written to in a storage device), wherein the write command indicates that the write data is to be written to a first superblock of the storage device (see para. 46 and 56 where the host specifies blocks and superblocks during a write operation); determining that the protocol for writing data to the first superblock has been violated by the write command from the host; and in response to determining that the protocol for writing data to the first superblock has been violated by the write command from the host, programming the write data to at least one of a reserved capacity of the first superblock or a second superblock (see para. 65 and fig. 6a, where the system attempts to write data to a superblock, if there is available capacity. The protocol for writing data would be writing data if the superblock has the available capacity. It is determined in step 610 that a superblock is full, or that the write command has violated the protocol for writing data to a superblock, and then allocating another superblock to write data to, which would constitute a second superblock).
Li discloses the claimed invention except for where the determining and programming are performed by a controller of the storage device; configuring, by a controller of a storage device, first and second superblocks to each have a declared capacity and a reserve capacity; programming, by the controller, the write data to the reserved capacity of the first superblock; and wherein a protocol for writing data to the first superblock in accordance with the declared capacity has been communicated to the host by the controller.
However, Alwala discloses where the determining and programming are performed by a controller of the storage device (See fig. 1, where Alwala also involves host to storage device communication. See para. 43, where the storage device controller creates and manages superblocks. In response to an error when reading or writing a block, the controller identifies a bad block which would result in not enough capacity. The controller then creates new superblocks without the bad blocks which would be used for reading/writing in the future as stipulated in para. 38. Therefore Alwala teaches that superblock management may be performed by the controller instead of the host. Combining Li and Alwala would result in Li’s controller doing the determining and programming steps instead of the host).
Li and Alwala are analogous art because they are from the same field of endeavor of superblocks (see Li, abstract and Alwala., abstract, regarding superblocks).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li to comprise where the determining and programming are performed by a controller of the storage device, as taught by Alwala, in order to allow for increased processing resources on the host, as it would not have to perform superblock management.
Li and Alwala disclose the claimed invention except for configuring, by a controller of a storage device, first and second superblocks to each have a declared capacity and a reserve capacity; programming, by the controller, the write data to the reserved capacity of the first superblock; and wherein a protocol for writing data to the first superblock in accordance with the declared capacity has been communicated to the host by the controller.
However, Agombar et al. discloses configuring, by a controller of a storage device, first and second superblocks to each have a declared capacity and a reserve capacity (see para. 32-33, where a controller manages the used and spare space on the drives. Also see para. 44-49, where the controller re-distributes spare space in the array and would configure both the declared and reserve spaces. Also see fig. 3a-3b); (see para. 21, where a total capacity of the first storage unit is provided to the user, which would be the declared capacity. The available capacity of the storage area would constitute a protocol of how much the host could write to the superblock, as a write to a superblock would depend on the available capacity. Note that Chang is being combined with ); Programming, by the controller, the write data to the reserved capacity of the first superblock (see para. 2, where when a drive fails, a spare drive may be provided. See para. 44-46 and fig. 3a-3b, where a drive failure causes spare space to be used. See fig. 1, showing a storage pool with each drive containing spare space and usable space. When a drive failure occurs, the reserved/spare capacity drive would be used).
Li and Agombar et al. are analogous art because they are from the same field of endeavor of storage systems (see Li, abstract and Agombar et al., abstract, regarding storage systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li to comprise wherein a protocol for writing data to the first superblock has been communicated to the host by the controller, as taught by Agombar et al., in order to have a spare capacity in case of error or needing extra capacity in some way in order to not decrease performance. Having a reserve capacity in storage devices is well known in the art and would be obvious to implement in Li.
Li, Alwala and Agombar et al. disclose the claimed invention except for wherein a protocol for writing data to the first superblock in accordance with the declared capacity has been communicated to the host by the controller.
However, Nakanishi et al. disclose wherein a protocol for writing data to the first superblock in accordance with the declared capacity has been communicated to the host by the controller (see para. 8, where an address space has both a normal and a spare region. See para. 73, where a capacity parameter indicates the number of physical blocks able to be used as the normal region. See para. 25, where an access device or host is notified of the capacity parameter, which would be the declared capacity).
Li and Nakanishi et al. are analogous art because they are from the same field of endeavor of storage devices (see Li, abstract and Nakanishi et al., abstract, regarding storage devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li to comprise wherein a protocol for writing data to the first superblock has been communicated to the host by the controller, as taught by Nakanishi et al., in order to make sure that the host’s write requests may be completed and so that the host doesn’t have to predict a capacity of a superblock and have increased efficiency.
Claims 12 and 20 recite similar limitations and would be rejected using the same rationale.
As to claim 2, Li, Alwala, Agombar et al. and Nakanishi et al. also disclose the method of claim 1, wherein the write command identifies a set of data that corresponds to a tenant of the host, an application of the host, or a data grouped by the host for placement (see Li, para. 46, where application can send requests to write data, and therefore the write command would correspond to an application of the host).
Claim 13 recites similar limitations and would be rejected using the same rationale.
As to claim 3, Li, Alwala, Agombar et al. and Nakanishi et al. also disclose the method of claim 1, wherein determining that the protocol for writing data to the first superblock has been violated comprises determining that a remainder of a declared capacity of the first superblock is less than a size of the write data (see Li, fig. 6a and para. 65, where it is determined if the superblock is full and therefore lacks the capacity to write the data).
Claim 14 recites similar limitations and would be rejected using the same rationale.
As to claim 4, Li, Alwala, Agombar et al. and Nakanishi et al. also disclose the method of claim 1, wherein determining that the protocol for writing data to the first superblock has been violated comprises determining that an entirety of a declared capacity of the first superblock is occupied (see Li, fig. 6a and para. 65, where it is determined if the superblock is full and therefore lacks the capacity to write the data ).
Claim 15 recites similar limitations and would be rejected using the same rationale.
As to claim 9, Li, Alwala, Agombar et al. and Nakanishi et al. also disclose the method of claim 1, wherein the first superblock is determined to lack the sufficient capacity to store the write data by a backend of the controller (see Li, fig. 2b, where the controller has a block sealer component in it. Also see para. 56-57, where the controller watches a superblock to determine when to seal it).
Claims 5-7, 10-11 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Alwala, Agombar et al. and Nakanishi et al. and in view of Shim et al. (U.S. Patent Application No. 2023/0153001), herein referred to as Shim et al.
As to claim 5, Li, Alwala, Agombar et al. and Nakanishi et al. disclose the claimed invention except for the method of claim 1, wherein the reserved capacity comprises one or more blocks configured to replace one or more bad blocks of the first superblock.
However Shim et al. disclose , wherein the reserved capacity comprises one or more blocks configured to replace one or more bad blocks of the first superblock (see para. 76-77, where a group of blocks or superblock contain some spare or reserved blocks to replace bad blocks).
Li and Shim et al. are analogous art because they are from the same field of endeavor of non-volatile memory (see Li, abstract and Shim et al., abstract, regarding non-volatile memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li to comprise wherein the reserved capacity comprises one or more blocks configured to replace one or more bad blocks of the first superblock, as taught by Shim et al., in order to allow for redundancy and increase the life of the storage.
Claim 16 recites similar limitations and would be rejected using the same rationale.
As to claim 6, Li, Alwala, Agombar et al. and Nakanishi et al. disclose the claimed invention except for the method of claim 1, wherein a portion of the write data is programmed to the reserved capacity; and another portion of the write data is programmed to the second superblock.
However Shim et al. disclose , wherein a portion of the write data is programmed to the reserved capacity; and another portion of the write data is programmed to the second superblock (see para. 76-77, where a group of blocks or superblock contain some spare or reserved blocks to replace bad blocks. See fig. 8, where if a bad block is detected is step 110, then first spare blocks are used from a first superblock. If there are not sufficient spare blocks, then in step 132 the write data is written to a different plane or superblock).
Li and Shim et al. are analogous art because they are from the same field of endeavor of non-volatile memory (see Li, abstract and Shim et al., abstract, regarding non-volatile memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li to comprise wherein a portion of the write data is programmed to the reserved capacity; and another portion of the write data is programmed to the second superblock, as taught by Shim et al., in order to allow for continued operation. If one superblock is full (including the reserved capacity), there would need to be somewhere to continue writing data.
Claim 17 recites similar limitations and would be rejected using the same rationale.
As to claim 7, Li, Alwala, Agombar et al. and Nakanishi et al. also disclose wherein a first portion of the write data is programmed to a remainder of the declared capacity of the first superblock (see Li, fig. 6a, where writes are programmed to a first superblock until it is full).
Li disclose the claimed invention except for a second portion of the write data is programmed to the reserved capacity; and a third portion of the write data is programmed to the second superblock.
However Shim et al. disclose a second portion of the write data is programmed to the reserved capacity; and a third portion of the write data is programmed to the second superblock (see para. 76-77, where a group of blocks or superblock contain some spare or reserved blocks to replace bad blocks. See fig. 8, where if a bad block is detected is step 110, then first spare blocks are used from a first superblock. If there are not sufficient spare blocks, then in step 132 the write data is written to a different plane or superblock).
Li and Shim et al. are analogous art because they are from the same field of endeavor of non-volatile memory (see Li, abstract and Shim et al., abstract, regarding non-volatile memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li to comprise a second portion of the write data is programmed to the reserved capacity; and a third portion of the write data is programmed to the second superblock, as taught by Shim et al., in order to allow for continued operation. If one superblock is full (including the reserved capacity), there would need to be somewhere to continue writing data.
As to claim 10, Li, Alwala, Agombar et al. and Nakanishi et al. disclose the claimed invention except for the method of claim 1, wherein programming the write data to the at least one of the reserved capacity of the first superblock or the second superblock comprises: determining, by the controller, that the reserved capacity of the first superblock is available; and in response to determining that the reserved capacity of the first superblock is available, storing the write data to the reserved capacity.
However Shim et al. disclose wherein programming the write data to the at least one of the reserved capacity of the first superblock or the second superblock comprises: determining, by the controller, that the reserved capacity of the first superblock is available; and in response to determining that the reserved capacity of the first superblock is available, storing the write data to the reserved capacity (see para. 76-77, where a group of blocks or superblock contain some spare or reserved blocks to replace bad blocks. See fig. 8, where if a bad block is detected is step 110, then first spare blocks are used from a first superblock. If there are not sufficient spare blocks, then in step 132 the write data is written to a different plane or superblock).
Li and Shim et al. are analogous art because they are from the same field of endeavor of non-volatile memory (see Li, abstract and Shim et al., abstract, regarding non-volatile memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li to comprise wherein programming the write data to the at least one of the reserved capacity of the first superblock or the second superblock comprises: determining, by the controller, that the reserved capacity of the first superblock is available; and in response to determining that the reserved capacity of the first superblock is available, storing the write data to the reserved capacity, as taught by Shim et al., in order to allow for continued operation and also utilizing space. If one superblock still has capacity, it would sense to utilize that capacity before closing it in order to maximize storage space.
Claim 18 recites similar limitations and would be rejected using the same rationale.
As to claim 11, Li, Alwala, Agombar et al. and Nakanishi et al. disclose the claimed invention except for the method of claim 1, wherein programming the write data to the at least one of the reserved capacity of the first superblock or the second superblock comprises: determining, by the controller, that the reserved capacity of the first superblock is not available; and in response to determining that the reserved capacity of the first superblock is not available, storing the write data to the second superblock.
However Shim et al. disclose wherein programming the write data to the at least one of the reserved capacity of the first superblock or the second superblock comprises: determining, by the controller, that the reserved capacity of the first superblock is not available; and in response to determining that the reserved capacity of the first superblock is not available, storing the write data to the second superblock (see para. 76-77, where a group of blocks or superblock contain some spare or reserved blocks to replace bad blocks. See fig. 8, where if a bad block is detected is step 110, then first spare blocks are used from a first superblock. If there are not sufficient spare blocks, then in step 132 the write data is written to a different plane or superblock).
Li and Shim et al. are analogous art because they are from the same field of endeavor of non-volatile memory (see Li, abstract and Shim et al., abstract, regarding non-volatile memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li to comprise wherein programming the write data to the at least one of the reserved capacity of the first superblock or the second superblock comprises: determining, by the controller, that the reserved capacity of the first superblock is not available; and in response to determining that the reserved capacity of the first superblock is not available, storing the write data to the second superblock, as taught by Shim et al., in order to allow for continued operation. If one superblock is full (including the reserved capacity), there would need to be somewhere to continue writing data.
Claim 19 recites similar limitations and would be rejected using the same rationale.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Alwala, Agombar et al. and Nakanishi et al. and in view of Jean et al. (U.S. Patent Application No. 2019/0066775), herein referred to as Jean et al.
As to claim 8, Li, Alwala, Agombar et al. and Nakanishi et al. disclose the claimed invention except for the method of claim 1, further comprising sending, by the storage device to the host, a soft error notification indicating that the first superblock lacks the sufficient capacity to store the write data.
However Jean et al. disclose sending, by the storage device to the host, a soft error notification indicating that the first superblock lacks the sufficient capacity to store the write data (see para. 28, where if an instruction to write data would exceed the capacity of a portion of memory, then an error message is sent to the host).
Li and Shim et al. are analogous art because they are from the same field of endeavor of memory devices (see Li, abstract and Jean et al., abstract, regarding memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li to comprise sending, by the storage device to the host, a soft error notification indicating that the first superblock lacks the sufficient capacity to store the write data, as taught by Jean et al., in order to allow the host to send a different instruction or also to notify it as storage is filled up to know what capacity is available.
Response to Arguments
Applicant's arguments filed 2/17/26 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Nakanishi et al. and Agombar et al.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 stand rejected.
b. DIRECTION OF FUTURE CORRESPONDENCES
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/A.O/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132