Prosecution Insights
Last updated: April 19, 2026
Application No. 17/701,899

QUANTUM CASCADE LASER

Final Rejection §103
Filed
Mar 23, 2022
Examiner
NELSON, HUNTER JARED
Art Unit
2828
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hamamatsu Photonics K K
OA Round
4 (Final)
17%
Grant Probability
At Risk
5-6
OA Rounds
2y 6m
To Grant
29%
With Interview

Examiner Intelligence

Grants only 17% of cases
17%
Career Allow Rate
2 granted / 12 resolved
-51.3% vs TC avg
Moderate +12% lift
Without
With
+12.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
51 currently pending
Career history
63
Total Applications
across all art units

Statute-Specific Performance

§103
51.5%
+11.5% vs TC avg
§102
14.4%
-25.6% vs TC avg
§112
33.7%
-6.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 12 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/18/2025 was filed after the mailing date of the Non-Final Rejection on 08/01/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Response to Amendment Examiner acknowledges the amendments made to claim 1 and the addition of new claim 24. Claims 3,8-10,16 and 19 stand as withdrawn and claims 5,11-14 and 23 stand as cancelled. Response to Arguments Applicant’s arguments with respect to claim(s) 1-2,4,6-7,15,17-18,20-22 and 24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1,4,15,17,18 and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Kakuno et al. (hereinafter Kakuno) (US 20180069374 A1) in view of Takagi (JP 2001085781 A) (Examiner notes an attached machine translation will be used for the claim mapping of Takagi for the remainder of the instant Office Action. See PTO-892 form) Regarding claim 1, Kakuno discloses in figures (3A-4C) A quantum cascade laser (Para. [0008]) comprising: a semiconductor substrate [10 Fig. 4B] including a first surface [top of 10 Fig. 4B] and a second surface [bottom of 10 Fig. 4B] opposite to the first surface;(Para. [0017]) an optical waveguide [40 Fig. 4C] including an active layer [12 Fig. 4C] having a quantum cascade structure (Para. [0019]) and a pair of clad layers [11 and 14 Fig. 4C] interposing the active layer [12 Fig.4C] therebetween, the optical waveguide [40 Fig. 4C] being formed on the first surface of the semiconductor substrate [top of 10 Fig. 4C] and being provided with a diffraction grating structure (Para. [0023]; and a temperature adjusting member [50 and 52] (Fig. 4B), wherein the optical waveguide [40] includes a first region [14a Fig. 4B] and a second region [14b Fig. 4B] located on one side with respect to the first region [14a Fig. 4B] in an optical waveguide direction of the optical waveguide (14a located to the left of 14b in waveguide direction), the first region [14a Fig. 4B] generates a first light [G1 Fig. 4B] having a first wavelength [λ1] and the second region [14b Fig. 4B] generates a second light [G2 Fig. 4B] having a second wavelength [λ2] (Para. [0033]), and the optical waveguide [40] generates an output light [TH Fig. 4B] having a frequency corresponding to a difference between the first wavelength [λ1] and the second wavelength [λ2] by difference-frequency generation, (Para. [0040]) wherein the temperature adjusting member [50 and 52 Fig. 4B] includes a first temperature adjusting member [52 Fig. 4B] for adjusting the temperature of the second region [14b Fig. 4B]. (Para. [0036]) and, wherein the semiconductor substrate [10 Fig. 4B] further includes an end surface [10a Fig. 4B] that intersects a plane parallel to the second surface [bottom of 10 Fig. 4B], and the quantum cascade laser is configured such that the output light [TH] is emitted from the end surface [10a]. (Para. [0020]) Kakuno fails to disclose, wherein a recess for suppressing heat transfer between the first region and the second region is formed at the second surface of the semiconductor substrate, wherein the recess has a rectangular or trapezoidal cross section and a bottom surface wherein a center of the recess does not overlap with the first temperature adjusting member when viewed from a thickness direction of the semiconductor substrate Takagi discloses in Fig. 9, A recess [921] (Para. [0050]) for suppressing thermal transfer between a first region and a second region (Para. [0051]) formed at a second surface [back surface of 2] (Para. [0051]) of a semiconductor substrate [2] (Para. [0051]) wherein the recess [92a] has a rectangular cross section (See Fig. 9) and a bottom surface [top of 92a toward 22] (Para. [0051]) wherein a center of the recess [92a] does not overlap with a first temperature adjusting member [12] (Para. [0047]) when viewed from a thickness direction of the semiconductor substrate [2] It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the recess of Takagi between the first and second regions of Kakuno for the purpose of reducing thermal interference between the two regions. (Takagi Para. [0051]) Regarding claim 4, Kakuno in view of Takagi as applied to claim 1 above further discloses in Takagi Fig. 9, wherein the recess [92a] (Para. [0050]) is a groove extending along a predetermined direction (Para. [0050]). Regarding claim 15, Kakuno in view of Takagi as applied to claim 1 above further discloses in Fig. 4B of Kakuno wherein the first temperature adjusting member [52] is arranged on the second surface of the semiconductor substrate [bottom of 10] (Para. [0036]) Regarding claim 17, Kakuno in view of Takagi as applied to claim 1 above further discloses in Fig. 4B of Kakuno wherein the temperature adjusting member further includes a second temperature adjusting member [50] for adjusting the temperature of the first region [14a] (Para. [0036]) Regarding claim 18, Kakuno in view of Takagi as applied to claim 1 above further discloses in Fig. 4B of Kakuno, wherein the second temperature adjusting member [50] is arranged on the second surface of the semiconductor substrate [bottom of 10] (Para. [0036]) Regarding claim 20, Kakuno in view of Takagi as applied to claim 1 above further discloses in Fig. 4B of Kakuno wherein the first temperature adjusting member [52] is a Peltier element (Para. [0036]) Regarding claim 21, Kakuno in view of Takagi as applied to claim 1 above further discloses in Fig. 4B of Kakuno wherein the second temperature adjusting member [50] is a Peltier element (Para. [0036]) Regarding claim 22, Kakuno in view of Takagi as applied to claim 1 above further discloses in Figs. 3A and 3B of Kakuno wherein the diffraction grating structure includes a first diffraction grating structure (D1 and λ1 shown in figure 3A) formed in the first region [14a] (Para. [0033]) and a second diffraction grating structure (D2 and λ2 shown in figure 3B) formed in the second region [14b], and (Para. [0033]) wherein the first diffraction grating structure includes a plurality of grooves (Fig. 3A) arranged at a pitch [D1] corresponding to the first wavelength [λ1], and the second diffraction grating structure includes a plurality of grooves (Fig. 3B) arranged at a pitch [D2] corresponding to the second wavelength [λ2]. (Para [0033,0034]) Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kakuno in view of Takagi as applied to claim 1 above, and further in view of Park et al. (hereinafter Park) (US 20100142571 A1). Regarding claim 2, Kakuno in view of Takagi discloses the device outlined in the rejection of claim 1 above but fails to disclose, wherein the recess is arranged so as to overlap a boundary between the first region and the second region when viewed from a direction perpendicular to the second surface. Park discloses in Fig. 1, a recess [130] (Para. [0037]) arranged so as to overlap a boundary between a first region [DFB1] (Para. [0037]) and a second region [P] (Para. [0037]) when viewed from a direction perpendicular to the second surface (cross section of Fig. 1) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to place the recess of the modified device of Kakuno overlapping a boundary between the two regions as shown in Park for the purpose of allowing independent operation of the distinct regions. (Park Para. [0037]) Claims 6 and 7 rejected under 35 U.S.C. 103 as being unpatentable over Kakuno in view of Takagi as applied to claim 1 above, and further in view of Kwon et al. (hereinafter Kwon) (US 20180205199 A1) Regarding claim 6, Kakuno in view of Takagi discloses the device outlined in the rejection of claim 1 above but fails to disclose, Wherein a length of the recess in the optical waveguide direction is 100 µm or more and 500 µm or less Kwon discloses in Fig. 15, A recess [108a] wherein a length of the recess [108a] in the optical waveguide direction [left and right Fig. 15] is 100µm or more and 500µm or less (Para. [0060]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the length of the recesses of Kwon into the bottom surface of Kakuno for the purpose of tuning the thermal transfer and thermal isolation efficiency of the device. (Kwon Para. [0058]) Regarding claim 7, Kakuno in view of Takagi discloses the device outlined in the rejection of claim 1 but fails to disclose, Wherein a depth of the recess is ½ or more of a distance between a bottom surface of the recess and the first surface Kwon discloses in Fig. 15, wherein a depth [D] (See Fig. 11) of the recess [108a] is ½ or more of a distance between a bottom surface of the recess [top layer surface of 108a] and the first surface [top surface of 10] (Para. [0056]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the depth relationships of the recesses of Kwon into the recesses of the modified device of Kakuno for the purpose of tuning the thermal transfer and thermal isolation efficiency of the device. (Kwon Para. [0058]) Para. [0056] of Kwon discloses that when the layer [10] has a thickness of about 100µm, the depth [D] can be about 10µm to 80µm. Therefore, in the range of 50µm-80µm of the depth [D], the depth of the recess is ½ or more of a distance between a bottom surface of the recess and the first surface. Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Kakuno in view of Takagi as applied to claim 1 above, and further in view of Shigihara et. al (hereinafter Shigihara) (EP 0590232 A1). Regarding claim 24, Kakuno in view of Takagi discloses the device outlined in the rejection of claim 1 above but fails to disclose, wherein the recess has a trapezoidal cross section (Page 8, lines 46-49) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the trapezoidal shape of the grooves of Shigihara as the shape of the recesses of the modified device of Takagi for the purpose of improved heat radiation. (Shigihara Page 8, lines 46-49) Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNTER J NELSON whose telephone number is (571)270-5318. The examiner can normally be reached Mon-Fri. 8:30am-5:00 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MinSun Harvey can be reached at (571) 272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /H.J.N./Examiner, Art Unit 2828 /TOD T VAN ROY/Primary Examiner, Art Unit 2828
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Prosecution Timeline

Mar 23, 2022
Application Filed
Jan 14, 2025
Non-Final Rejection — §103
Mar 21, 2025
Response Filed
Apr 03, 2025
Final Rejection — §103
May 21, 2025
Examiner Interview Summary
May 21, 2025
Applicant Interview (Telephonic)
Jun 26, 2025
Examiner Interview Summary
Jun 26, 2025
Applicant Interview (Telephonic)
Jul 08, 2025
Response after Non-Final Action
Jul 22, 2025
Request for Continued Examination
Jul 23, 2025
Response after Non-Final Action
Jul 30, 2025
Non-Final Rejection — §103
Sep 03, 2025
Applicant Interview (Telephonic)
Sep 03, 2025
Examiner Interview Summary
Oct 17, 2025
Response Filed
Jan 12, 2026
Final Rejection — §103
Mar 10, 2026
Examiner Interview Summary
Mar 10, 2026
Applicant Interview (Telephonic)

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Prosecution Projections

5-6
Expected OA Rounds
17%
Grant Probability
29%
With Interview (+12.5%)
2y 6m
Median Time to Grant
High
PTA Risk
Based on 12 resolved cases by this examiner. Grant probability derived from career allow rate.

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