Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is final and is in response to claims filed on 11/12/2025 via amendment. Claims 1-9 and 11-20 are pending for examination. Claims 1, 3, 7-8, 16, and 19-20 are currently amended. Claims 2, 4-6, 9, 11-15, and 17-18 are as originally filed.
Response to Arguments
Objection to the abstract
The amended abstract is 154 words, still over the limit of 150 words. Therefore, the objection to the abstract is maintained.
Claim Interpretation
Applicant has amended claims 3 and 16 to remove the contingent limitations. Therefore, the interpretation for claims 3 and 16 have been withdrawn.
The amendments to claims 1, 7, and 8 fail to overcome the contingent limitations.
Claim 1 still recites the limitations “if the first component of the vector result is non-zero then” and “if the first component of the vector result is zero and if the second component of the vector result is non-zero then”. A potential way to overcome the contingent language of claim 1 would be to recite multiple components of the ray tracing system, one for processing the non-zero first components and one for processing the zero first components.
Claim 7 recites “for a received floating point value that is zero” which is still a contingent limitation. A potential way to overcome the contingent language of claim 7 would be to recite “receiving a floating point value that is zero”.
Claim 8 recites “for a received floating point value that is infinity” which is still a contingent limitation. A potential way to overcome the contingent language of claim 7 would be to recite “receiving a floating point value that is infinity”.
Therefore, the interpretation for claims 1, 7, and 8 are maintained.
Rejections Under 35 U.S.C. 101
Applicant’s arguments regarding the 35 U.S.C. 101 rejections have been fully considered. Regarding the rejection under 35 U.S.C. 101, Applicant argues “that the method is applied to the technological field of computer graphics processing, and is clearly “integrated” into the practical application of computer graphics processing.” See Remarks 9.
Examiner respectfully disagrees with applicant arguments. Saying that the math and mental processes of the claims are integrated into the practical integration by stating the use of the math and mental processes is clearly generally linking the use of the judicial exception to a particular field of use. see MPEP 2106.05(h).
Applicant further argues that “replacing a floating point zero values with a very small, but non-zero, number and floating point infinity values can be replaced by a very large, but finite number, can avoid the need for exception handling logic, thus reducing the size and complexity of the processing module.” See Remarks 10-11.
Examiner respectfully disagrees with applicant arguments. This purported improvements to the size and complexity of the processing module are not recited in the claims.
Applicant further argues that “the claims set forth a practical application of using the outputted result of the particular comparison operation to render an image.” See Remarks 11. Applicant further argues that “the processing module is implemented as part of a ray tracing system in which the outputted result is used to render an image.” See Remarks 11.
Examiner respectfully disagrees with applicant arguments. Rendering an image is a well understood, routine, conventional activity. See TLI Communications LLC v. AV Automotive LLC, 823 F.3d 607, 118 USPQ2d 1744 (Fed. Cir. 2016). See also Bishop et al. (EP 0259971 A1) published 03/16/1988, which recites “Most computer image generation systems represent curved surfaces as a mesh of planar polygons, because polygons can be transformed and rendered quickly with well known algorithms” (Bishop et al. Page 2 Lines 6-7).
Applicant further argues that “the processing module is integrated into a ray tracing system and thus the ray tracing system is not a generic computing element.” See Remarks 12.
Examiner respectfully disagrees with applicant arguments. The processing module is a clear “apply it” scenario using generic computing elements recited at a high level of generality. MPEP 2106.05(f). The processing module does not denote any specific structure and is merely a generic circuit performing the abstract ideas (performing a particular comparison operation, promoting the received floating point values, determining a scalar result, etc.). The ray tracing system is recited at a high level of generality and is clearly generally linking the use of the judicial exception to a particular field of use. see MPEP 2106.05(h).
It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements. See the discussion of Diamond v. Diehr, 450 U.S. 175, 187 and 191-92, 209 USPQ 1, 10 (1981)) in subsection II, below. In addition, the improvement can be provided by the additional element(s) in combination with the recited judicial exception... However, it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology...”. See MPEP 2106.05(a).
Rejections Under 35 U.S.C. 103
Applicant’s arguments with respect to claims 1-2, 4-5, and 7, 9-15, and 17-18 have been fully considered. Applicant argues that “claim 1 has been amended to recite corresponding features to those of claim 19 and 20 which were deemed allowable subject matter if rewritten to overcome the rejections under 35 U.S.C. 101 set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.” See Remarks 13.
Examiner respectfully disagrees with applicant arguments. See the Claim Interpretation sub-heading above.
Applicant further argues that Saleh, Montrym, Brown, Kulisch, and Malik are not analogous art. See Remarks 14.
Examiner respectfully disagrees with applicant arguments. In response to applicant's argument that Saleh, Montrym, Brown, Kulisch, and Malik are nonanalogous art, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case, the art is all of the field of data processing. Furthermore, Saleh, Montrym, and Brown are all in the field of graphics processing. Kulisch and Malik deal with processing of floating point numbers which is in the field of Saleh, Montrym, and Brown as well as the instant application.
Applicant further argues that “the only reason to combine said references would be hindsight.” See Remarks 14.
Examiner respectfully disagrees with applicant arguments. The previous office action presented the reasons for combining said references. In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Applicant’s arguments with respect to claim 8 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 10/06/2025 is in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Specification
The abstract of the disclosure is objected to because it is 154 word long. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Interpretation
Claims 1, and 7-8 are directed to a method that recites conditional language. Claim 1 recites “and wherein if the first component of the vector result is zero and if the second component of the vector result is non-zero”. Claim 7 recites “wherein said setting a second component of one or more of the vector floating point values to a non-zero, finite value comprises: if a received floating point value is zero”. Claim 8 recites “wherein said setting a second component of one or more of the vector floating point values to a non-zero, finite value comprises: if a received floating point value is infinity”. The conditional nature of this claim language allows for an interpretation where any prior art meets the broadest reasonable interpretation of the claim without having the conditional language even occurring (and thus only the preceding limitations required by the prior art).
The conditional nature of this claim language allows for an interpretation where any prior art meets the broadest reasonable interpretation of the claim without having the conditional language even occurring (and thus only the preceding limitations required by the prior art). For example, in claim 1, the “then the sign of the scalar result equals the sign of the second component of the vector result” limitation is not required to be taught by the prior art. For claim 7, the “setting the second component of the corresponding vector floating point value to a non-zero, finite value” limitation is not required to be taught by the prior art. For claim 8, the “setting the second component of the corresponding vector floating point value to a non-zero, finite value” limitation is not required to be taught by the prior art. For claim 16, the “setting the sign of the signed parameter to match the sign of a predetermined one of the floating point values used in the 2D cross product” limitation is not required to be taught by the prior art. See MPEP 2111.04(II); see also Ex parte Schulhauser. Examiner notes that the broadest reasonable interpretation of the method of claims 1 and 7-8 require none of those “if” or “in response” conditions to occur and thus the claim language ends. Examiner encourages claim amendments that specifically removes the conditional language of the claims and thus expressly has the claimed scenarios occur. Examiner respectfully reiterates that without changing the conditional nature of the claim, the method claims carry no patentable weight as noted above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-9 and 11-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more.
With regards to claim 1, at step 1, the claim is directed to a method, which is a statutory category of invention.
At Step 2A Prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical concepts. The claim language has been reproduced below:
A method of performing, in a processing module, a particular comparison operation using floating point values, wherein the processing module is implemented as part of a ray tracing system (mental process, evaluation), wherein the particular comparison operation is part of an intersection testing process performed by the ray tracing system (mental process, evaluation), the method comprising: (Mental process, evaluation; Mathematical relationship)
receiving the floating point values in a scalar format; (Mental process, evaluation; Mathematical relationship)
promoting the received floating point values to a vector format, wherein the received floating point values are used as a first component of the vector floating point values; (Mental process, evaluation; Mathematical calculation)
setting a second component of one or more of the vector floating point values to a non-zero, finite value; (Mental process, evaluation; Mathematical relationship)
performing the particular comparison operation using the vector floating point values to determine a vector result having first and second components; (Mathematical calculation)
determining a scalar result of the particular comparison operation, wherein the magnitude of the scalar result is given by the magnitude of the first component of the vector result, (Mental process, evaluation; Mathematical relationship) and wherein the processing module is configured to (mental process, evaluation) determine the sign of the scalar result such that: (mathematical relationship)
if the first component of the vector result is non-zero then the sign of the scalar result equals the sign of the first component of the vector result; (Mental process, evaluation; Mathematical relationship)
if the first component of the vector result is zero and if the second component of the vector result is non-zero then the sign of the scalar result equals the sign of the second component of the vector result; and (Mental process, evaluation; Mathematical relationship)
outputting the scalar result of the particular comparison operation, (mathematical relationship) wherein the outputted result of the particular comparison operation is used in the ray tracing system (mental process, evaluation) to render an image.
Each of the non-bolded limitations are mental processes and/or mathematical calculations. The “wherein the processing module is implemented as part of” limitation is an evaluation mental process that can be performed by choosing what the processing module is a part of. The “wherein the particular comparison operation” limitation is an evaluation mental process that can be performed by choosing what the comparison operation is a part of. The “the method comprising” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the method comprises. The “floating point values in a scalar format” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the format of the values are. The “promoting the received floating point values to a vector format, wherein” limitation is an evaluation mental process and mathematical calculation that can be performed by converting the value to a vector by hand using pen and paper. The “setting a second component of one or more” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what to set the second component to. The “performing the particular comparison operation using” is a mathematical calculation that can be performed by performing the comparison by hand using pen and paper. The “determining a scalar result of the particular” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the magnitude of the scalar result is. The “and wherein the processing module is configured to” limitation is an evaluation mental process that can be performed by choosing what the processing module is configured to do. The “determine the sign of the scalar result” limitation is a mathematical relationship that can be performed by determining the sign by hand using pen and paper. The “if the first component of the vector result is non-zero” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the sign of the scalar result is. The “and wherein if the first component of the vector result is zero” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the sign of the scalar result is. The “outputting the scalar result of the particular comparison operation” is a mathematical relationship that can be performed by outputting the result by hand using pen and paper. The “wherein the outputted result of the particular comparison operation is used” limitation is an evaluation mental process that can be performed by choosing what the output is used for.
At step 2A Prong 2, the additional elements are bolded above. The “receiving” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘receiving’ in the context of the claim encompasses mere data gathering for the claimed promoting step. The “received” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘received’ in the context of the claim encompasses mere data gathering for the claimed promoting step. The “outputting” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘outputting’ in the context of the claim encompasses mere data gathering. The remaining additional elements amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
Under Step 2B, the claim recites “to render an image”. The process of rendering an image is well understood, routine, and conventional function claimed in a generic matter. See TLI Communications LLC v. AV Automotive LLC, 823 F.3d 607, 118 USPQ2d 1744 (Fed. Cir. 2016). See also Bishop et al. (EP 0259971 A1) published 03/16/1988, which recites “Most computer image generation systems represent curved surfaces as a mesh of planar polygons, because polygons can be transformed and rendered quickly with well known algorithms” (Bishop et al. Page 2 Lines 6-7). The claim recites “receiving the floating point values in a scalar format”, “promoting the received floating point values”, “outputting the scalar result of the particular comparison operation”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 19, it recites similar language to claim 1 and is rejected for, at least, the same reasons therein. Herein claim 19 is directed towards the statutory category of a machine, thus also satisfying step 1. Moreover under step 2A prong 2 and 2B, the claim does not recite any additional
elements that integrate the abstract idea into a practical application, nor do they amount to significantly
more than the judicial exception.
With regards to claim 20, it recites similar language to claim 1 and is rejected for, at least, the same reasons therein. Herein claim 20 is directed towards the statutory category of an article of manufacture, thus also satisfying step 1. Moreover under step 2A prong 2 the additional elements are “A non-transitory computer-readable medium”. These are no more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). The limitations “integrated circuit manufacturing system” are no more than generally linking the use of the judicial exception to a field of use. see MPEP 2106.05(h). The additional element “stored”, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘stored’ in the context of the claim encompasses mere data gathering. Under Step 2B, the claim recites “having stored thereon an integrated circuit definition dataset”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 2, It is directed to mental processes and/or mathematical concepts. The “wherein each vector floating point value has three components” limitation is an evaluation mental process that can be performed by choosing how many components the vector has. The “wherein for a first set of the floating point values” limitation is an evaluation mental process and mathematical calculation that can be performed by setting the second component by hand using pen and paper. The “and wherein for a second set” limitation is an evaluation mental process and mathematical calculation that can be performed by setting the third component by hand using pen and paper. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 3, It is directed to mental processes and/or mathematical concepts. The “wherein the first and second components of the vector result” limitation is an evaluation mental process that can be performed by choosing what the sign of the scalar result is. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 4, It is directed to mental processes and/or mathematical concepts. The “wherein for each of the vector floating point values, either” limitation is an evaluation mental process and mathematical calculation that can be performed by setting the second or third component by hand using pen and paper. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 5, It is directed to mental processes and/or mathematical concepts. The “wherein said non-zero, finite value is 1” limitation is an evaluation mental process that can be performed by choosing what the non-zero, finite value is. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 6, It is directed to mental processes and/or mathematical concepts. The “wherein each vector floating point value has only two components” limitation is an evaluation mental process that can be performed by choosing how many components the vector has. The “wherein for a first set of the floating point values the second component” limitation is an evaluation mental process and mathematical calculation that can be performed by setting the second component to 1 by hand using pen and paper. The “wherein for a second set of the floating point values the” limitation is an evaluation mental process and mathematical calculation that can be performed by setting the second component to e2/e1 by hand using pen and paper. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 7, It is directed to mental processes and/or mathematical concepts. The “for a received floating point value that is zero, setting the” limitation is an evaluation mental process and mathematical calculation that can be performed by setting the second component to a non-zero, finite value by hand using pen and paper. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 8, It is directed to mental processes and/or mathematical concepts. The “for a received floating point value that is infinity, setting the” limitation is an evaluation mental process and mathematical calculation that can be performed by setting the second component to a non-zero, finite value by hand using pen and paper. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 9, It is directed to mental processes and/or mathematical concepts. The “wherein each vector floating point value has only two components” limitation is an evaluation mental process that can be performed by choosing how many components the vector has. The “wherein said setting a second component of one or more of the vector floating point values to a non-zero” limitation is an evaluation mental process and mathematical calculation that can be performed by setting the second component to a non-zero, finite value by hand using pen and paper. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 11, It is directed to mental processes and/or mathematical concepts. The “wherein the particular comparison operation comprises” limitation is an evaluation mental process and mathematical calculation that can be performed by comparing the result of multiplying two floating point values with the result of multiplying two other floating point values by hand using pen and paper. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 12, It is directed to mental processes and/or mathematical concepts. The “wherein the processing module is implemented as part” limitation is an evaluation mental process that can be performed by choosing what the processing module is a part of. The “and wherein the particular comparison operation is part of” limitation is an evaluation mental process that can be performed by choosing what the comparison operation is a part of. The “projecting the vertices of the convex polygon onto a pair of axes” is a mathematical calculation that can be performed by projecting the vertices by hand using pen and paper. The “wherein the origin of the pair of axes corresponds” is an evaluation mental process that can be performed by choosing what the origin is. The “for each edge of the convex polygon defined by two of the projected vertices, using the particular comparison operation” limitation is a mathematical calculation that can be performed by performing the 2D cross product by hand using pen and paper. The “determining whether the ray intersects” limitation is an evaluation mental process and mathematical calculation that can be performed by determining if the ray intersects by hand using pen and paper. Under Steps 2A Prong 2 the “ray tracing system” is generally linking the use of the judicial exception to a particular field of use. see MPEP 2106.05(h). None of the remaining additional elements regarding the generic computer components (i.e. processing module, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 13, It is directed to mental processes and/or mathematical concepts. The “wherein said determining whether the ray intersects the convex polygon comprises: determining that the ray intersects” limitation is an evaluation mental process that can be performed by seeing if the signs of the results are the same. The “and determining that the ray does not intersect” limitation is an evaluation mental process that can be performed by seeing if the signs of the results are different. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 14, It is directed to mental processes and/or mathematical concepts. The “determining that the ray intersects the convex polygon if” limitation is an evaluation mental process that can be performed by seeing if the ray is within all of the edges. The “and determining that the ray does not intersect” imitation is an evaluation mental process that can be performed by seeing if the ray is not within all of the edges. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 15, It is directed to mental processes and/or mathematical concepts. The “wherein the 2D cross product, f(vi,vj), of the positions of the two projected vertices, vi and vj, defining an” limitation is an evaluation mental process that can be performed by choosing what the 2D cross product is defined as. The “and wherein the comparison operation comprises performing” limitation is a mathematical calculation that can be performed by performing the 2D cross product by hand using pen and paper. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 16, It is directed to mental processes and/or mathematical concepts. The “determining that the result of the 2D cross product” limitation is an evaluation mental process and mathematical relationship that can be performed by determining that the result of the 2D cross product is zero by hand using pen and paper. The “in response to determining that the result of the 2D cross product is zero,” limitation is an evaluation mental process that can be performed by setting the sign by hand using pen and paper. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 17, It is directed to mental processes and/or mathematical concepts. The “wherein the outputted indication is used in” limitation is an evaluation mental process that can be performed by choosing how the indication is used. Under step 2A, The “outputting” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘outputting’ in the context of the claim encompasses mere data gathering. The “wherein the outputted indication is used in the ray tracing system” limitation is generally linking the use of the judicial exception to a particular field of use, as well as being merely an intended use of the abstract idea. see MPEP 2106.05(h). Under Step 2B, the claim recites “for rendering an image of a 3D scene”. The process of rendering an image is well understood, routine, and conventional function claimed in a generic matter. See TLI Communications LLC v. AV Automotive LLC, 823 F.3d 607, 118 USPQ2d 1744 (Fed. Cir. 2016). See also Bishop et al. (EP 0259971 A1) published 03/16/1988, which recites “Most computer image generation systems represent curved surfaces as a mesh of planar polygons, because polygons can be transformed and rendered quickly with well known algorithms” (Bishop et al. Page 2 Lines 6-7). The claim recites “outputting an indication of a result of the determination”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 18, It is directed to mental processes and/or mathematical concepts. The “wherein the method is performed” limitation is an evaluation mental process that can be performed by choosing where the method is performed. Under step 2A Prong 2, The “in fixed function circuitry of the processing module” limitation is generally linking the use of the judicial exception to a particular technological environment. see MPEP 2106.05(h). Under Step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, and 7, 9-15, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Saleh et al. (US 20210287421 A1) hereinafter Saleh in view of Montrym et al. (US 20030103054 A1) hereinafter Montrym further in view of Brown et al. (US 8134566 B1) hereinafter Brown further in view of Malik et al. (“Importance of Vector Processing”) hereinafter Malik further in view of Kulisch et al. (“The Fifth Floating Point Operation for Top Performance Computers”) hereinafter Kulisch.
With regards to claim 1, Saleh teaches A method of performing, in a processing module, a particular comparison operation (Saleh [0047]: Next, barycentric coordinates for the triangle, U, V, W (shown in FIG. 6) are calculated in the following manner: U=area(Triangle CBT)=0.5*(C×B); Saleh [0048]: Here, the “x” indicates a cross-product and A, B, and C are the transformed vertices A.sub.trf, B.sub.trf, and C.sub.trf; (The cross product being the comparison))
wherein the processing module is implemented as part of a ray tracing system, (Saleh [0012]: A technique for performing a ray tracing operation for a ray is provided)
wherein the particular comparison operation is part of an intersection testing process performed by the ray tracing system, the method comprising: (Saleh [0012]: The method includes performing one or more ray-box intersection tests for the ray against one or more bounding boxes)
performing the particular comparison operation using the vector floating point values to determine a vector result having first and second components; (Saleh [0047]: Next, barycentric coordinates for the triangle, U, V, W (shown in FIG. 6) are calculated in the following manner: U=area(Triangle CBT)=0.5*(C×B); Saleh [0048]: Here, the “x” indicates a cross-product and A, B, and C are the transformed vertices A.sub.trf, B.sub.trf, and C.sub.trf; (The cross product being the comparison))
the processing module is configured to determine the sign of the scalar result such that: (Saleh [0048]: Here, the “x” indicates a cross-product and A, B, and C are the transformed vertices A.sub.trf, B.sub.trf, and C.sub.trf, which are shown in FIG. 6. The signs of U, V, and W indicate whether the ray intersects the triangle)
wherein the outputted result of the particular comparison operation is used in the ray tracing system to render an image (Saleh [0023]: The compute units 132 implement ray tracing, which is a technique that renders a 3D scene by testing for intersection between simulated light rays and objects in a scene).
Saleh fails to teach using floating point values, receiving the floating point values in a scalar format; promoting the received floating point values to a vector format, wherein the received floating point values are used as a first component of the vector floating point values; setting a second component of one or more of the vector floating point values to a non-zero, finite value; determining a scalar result of the particular comparison operation and outputting the scalar result of the particular comparison operation.
However, Montrym teaches using floating point values, (Montrym [0092]: a plurality of vertex attributes that are all IEEE 32 bit floats)
receiving the floating point values in a scalar format; (Montrym [0092]: a plurality of vertex attributes that are all IEEE 32 bit floats; Montrym [0130]: In use the conversion module 514 serves to convert scalar vertex data to vector vertex data)
promoting the received floating point values to a vector format, wherein the received floating point values are used as a first component of the vector floating point values; (Montrym [0092]: a plurality of vertex attributes that are all IEEE 32 bit floats; Montrym [0130]: For example, a scalar A, after conversion, may become a vector (A,A,A,A))
setting a second component of one or more of the vector floating point values to a [non-zero], finite value; (Montrym [0092]: a plurality of vertex attributes that are all IEEE 32 bit floats; Montrym [0130]: For example, a scalar A, after conversion, may become a vector (A,A,A,A))
determining a scalar result of the particular comparison operation, (Montrym [0184]: vector vertex data is processed by a vector processing module, i.e. adder, multiplier, etc., which outputs scalar vertex data)
and outputting the scalar result of the particular comparison operation (Montrym [0184]: vector vertex data is processed by a vector processing module, i.e. adder, multiplier, etc., which outputs scalar vertex data).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Saleh with scalar to vector promotion as taught by Montrym. One of ordinary skill in the art would be motivated to make this combination because it would allow for the intersection test to be performed efficiently, as only one vector would be received per vertex instead of one number per coordinate. Also, their performance derives from a heavily pipelined architecture which operations on vectors and matrices can efficiently exploit as taught by Malik (Malik Page 163 Right Column).
Saleh in view of Montrym does not teach [setting a second component of one or more of the vector floating point values to] a non-zero, [finite value] and wherein the magnitude of the scalar result is given by the magnitude of the first component of the vector result, and if the first component of the vector result is non-zero then the sign of the scalar result equals the sign of the first component of the vector result; and if the first component of the vector result is zero and if the second component of the vector result is non-zero then the sign of the scalar result equals the sign of the second component of the vector result.
However, Brown does teach [setting a second component of one or more of the vector floating point values to] a non-zero, [finite value] (Brown Col. 37 Line 13: The "w" component is filled with 1.0)
wherein the magnitude of the scalar result is given by the magnitude of the first component of the vector result, (Brown Col. 47 Lines 45-50: The <scalarSuffix> grammar rule converts a vector to a scalar by selecting a single component. The <scalarSuffix>; rule is similar to the swizzle selector, except that only a single component is selected. If the scalar suffix is ".y" and the specified source contains {2,8,9,0}, the value is the scalar value 8)
and if the first component of the vector result is non-zero then the sign of the scalar result equals the sign of the first component of the vector result; (Brown Col. 47 Lines 50-53: Next, a component-wise negate operation is performed on the operand if the <operandNeg> grammar rule matches "-". Negation is not performed if the operand has no sign prefix, or is prefixed with "+")
and if the first component of the vector result is zero and if the second component of the vector result is non-zero then the sign of the scalar result equals the sign of the second component of the vector result; (Brown Col. 47 Lines 50-53: Next, a component-wise negate operation is performed on the operand if the <operandNeg> grammar rule matches "-". Negation is not performed if the operand has no sign prefix, or is prefixed with "+")
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Saleh in view of Montrym with the magnitude of the scalar and sign of the scalar as taught by Brown. One of ordinary skill in the art would be motivated to make this combination because converting to a scalar would speed up any calculations that need to use the number because they would not have to deal with all of the different components of the vector. Also, the advantages of floating-point arithmetic such as the abendening of tiresome (problem) scalings, i.e. their automatization as taught by Kulisch (Kulisch Page 13 Section 9).
With regards to claim 2, Saleh in view of Montrym further in view of Brown teaches all of the limitations of claim 1 above. Sale fails to teach wherein each vector floating point value has three components, wherein for a first set of the floating point values the second component is set to a non-zero, finite value, and wherein for a second set of the floating point values the third component is set to a non-zero, finite value.
However, Montrym does teach wherein each vector floating point value has three components, (Montrym [0130]: For example, a scalar A, after conversion, may become a vector (A,A,A,A))
wherein for a first set of the floating point values the second component is set to a [non-zero], finite value, (Montrym [0130]: For example, a scalar A, after conversion, may become a vector (A,A,A,A))
and wherein for a second set of the floating point values the third component is set to a [non-zero], finite value (Montrym [0130]: For example, a scalar A, after conversion, may become a vector (A,A,A,A)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Saleh with vectors having 3 components and setting the components as taught by Montrym. One of ordinary skill in the art would be motivated to make this combination because it would allow for the intersection test to be performed efficiently, as only one vector would be received per vertex instead of one number per coordinate. Also, their performance derives from a heavily pipelined architecture which operations on vectors and matrices can efficiently exploit as taught by Malik (Malik Page 163 Right Column).
Saleh in view of Montrym fails to teach the components being non-zero.
However, Brown does teach the components being non-zero (Brown Col. 37 Line 13: The "w" component is filled with 1.0).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Saleh in view of Montrym with the components being non-zero as taught by Brown. One of ordinary skill in the art would be motivated to make this combination because for at least the same reasons as claim 1 above.
With regards to claim 4, Saleh in view of Montrym further in view of Brown teaches all of the limitations of claim 2 above. Saleh fails to teach wherein for each of the vector floating point values, either the second component or the third component is set to a non-zero, finite value.
However, Montrym teaches wherein for each of the vector floating point values, either the second component or the third component is set to a [non-zero], finite value (Montrym [0130]: For example, a scalar A, after conversion, may become a vector (A,A,A,A)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Saleh with vectors components being set as taught by Montrym. One of ordinary skill in the art would be motivated to make this combination because it would allow for the intersection test to be performed efficiently, as only one vector would be received per vertex instead of one number per coordinate. Also, their performance derives from a heavily pipelined architecture which operations on vectors and matrices can efficiently exploit as taught by Malik (Malik Page 163 Right Column).
Saleh in view of Montrym fails to teach the components being non-zero.
However, Brown does teach the components being non-zero (Brown Col. 37 Line 13: The "w" component is filled with 1.0).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Saleh in view of Montrym with the components being non-zero as taught by Brown. One of ordinary skill in the art would be motivated to make this combination because for at least the same reasons as claim 1 above.
With regards to claim 5, Saleh in view of Montrym further in view of Brown teaches all of the limitations of claim 1 above. Saleh fails to teach wherein said non-zero, finite value is 1.
However, Brown does teach wherein said non-zero, finite value is 1 (Brown Col. 37 Line 13: The "w" component is filled with 1.0).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Saleh with the non-zero, finite value being 1 as taught by Brown. One of ordinary skill in the art would be motivated to make this combination because for at least the same reasons as claim 1 above.
With regards to claim 7, Saleh in view of Montrym further in view of Brown teaches all of the limitations of claim 1 above. Saleh fails to teach wherein said setting a second component of one or more of the vector floating point values to a non-zero, finite value comprises: for a received floating point value that is zero, setting the second component of the corresponding vector floating point value to a non-zero, finite value.
However, Montrym teaches wherein said setting a second component of one or more of the vector floating point values to a [non-zero], finite value comprises: for a received floating point value that is zero, setting the second component of the corresponding vector floating point value to a [non-zero], finite value (Montrym [0130]: For example, a scalar A, after conversion, may become a vector (A,A,A,A)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Saleh with vectors components being set as taught by Montrym. One of ordinary skill in the art would be motivated to make this combination because it would allow for the intersection test to be performed efficiently, as only one vector would be received per vertex instead of one number per coordinate. Also, their performance derives from a heavily pipelined architecture which operations on vectors and matrices can efficiently exploit as taught by Malik (Malik Page 163 Right Column).
Saleh in view of Montrym fails to teach the components being non-zero.
However, Brown does teach the components being non-zero (Brown Col. 37 Line 13: The "w" component is filled with 1.0).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Saleh in view of Montrym with the components being non-zero as taught by Brown. One of ordinary skill in the art would be motivated to make this combination because for at least the same reasons as claim 1 above.
With regards to claim 9, Saleh in view of Montrym further in view of Brown teaches all of the limitations of claim 1 above. Saleh further teaches wherein each vector floating point value has only two components, (Saleh [0037]: The vertices of the triangle are transformed into this coordinate system. Such a transform allows the test for intersection to be made by simply asking whether the x, y coordinates of the ray fall within the triangle defined by the x, y coordinates of the vertices of the triangle).
Saleh fails to teach wherein said setting a second component of one or more of the vector floating point values to a non-zero, finite value comprises setting a second component of all of the vector floating point values to non-zero, finite floating point values.
However, Montrym teaches wherein said setting a second component of one or more of the vector floating point values to a [non-zero], finite value comprises setting a second component of all of the vector floating point values to [non-zero], finite floating point values (Montrym [0130]: For example, a scalar A, after conversion, may become a vector (A,A,A,A)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Saleh with vectors components being set as taught by Montrym. One of ordinary skill in the art would be motivated to make this combination because it would allow for the intersection test to be performed efficiently, as only one vector would be received per vertex instead of one number per coordinate. Also, their performance derives from a heavily pipelined architecture which operations on vectors and matrices can efficiently exploit as taught by Malik (Malik Page 163 Right Column).
Saleh in view of Montrym fails to teach the components being non-zero.
However, Brown does teach the components being non-zero (Brown Col. 37 Line 13: The "w" component is filled with 1.0).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Saleh in view of Montrym with the components being non-zero as taught by Brown. One of ordinary skill in the art would be motivated to make this combination because for at least the same reasons as claim 1 above.
With regards to claim 11, Saleh in view of Montrym further in view of Brown teaches all of the limitations of claim 1 above. Saleh further teaches wherein the particular comparison operation comprises comparing the result of multiplying two [floating point] values with the result of multiplying two other [floating point] values (Saleh [0047]: Next, barycentric coordinates for the triangle, U, V, W (shown in FIG. 6) are calculated in the following manner: U=area(Triangle CBT)=0.5*(C×B); Saleh [0048]: Here, the “x” indicates a cross-product and A, B, and C are the transformed vertices A.sub.trf, B.sub.trf, and C.sub.trf; (The cross product being the comparison))
Saleh fails to teach that the values are floating point.
However, Montrym does teach that the values are floating point (Montrym [0092]: a plurality of vertex attributes that are all IEEE 32 bit floats).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Saleh with values being floating points as taught by Montrym. One of ordinary skill in the art would be motivated to make this combination because it would allow for efficient calculations, as the coordinates of the vertices could be accurately stored. Also, the advantages of floating-point arithmetic such as the abendening of tiresome (problem) scalings, i.e. their automatization as taught by Kulisch (Kulisch Page 13 Section 9).
With regards to claim 12, Saleh in view of Montrym further in view of Brown teaches all of the limitations of claim 1 above. Saleh further teaches wherein the processing module is implemented as part of a ray tracing system, and wherein the particular comparison operation is part of an intersection testing process to determine whether a ray intersects a convex polygon defined by an ordered set of vertices, the method further comprising: (Saleh [0037]: More specifically, projecting the triangle into the viewspace of the ray transforms the coordinate system so that the ray points downwards in the z direction and the x and y components of the ray are 0 (although in some modifications, the ray may point upwards in the z direction, or in the positive or negative x or y directions, with the components in the other two axes being zero). The vertices of the triangle are transformed into this coordinate system. Such a transform allows the test for intersection to be made by simply asking whether the x, y coordinates of the ray fall within the triangle defined by the x, y coordinates of the vertices of the triangle)
projecting the vertices of the convex polygon onto a pair of axes orthogonal to the ray direction, (Saleh [0037]: More specifically, projecting the triangle into the viewspace of the ray transforms the coordinate system so that the ray points downwards in the z direction and the x and y components of the ray are 0 (although in some modifications, the ray may point upwards in the z direction, or in the positive or negative x or y directions, with the components in the other two axes being zero). The vertices of the triangle are transformed into this coordinate system. Such a transform allows the test for intersection to be made by simply asking whether the x, y coordinates of the ray fall within the triangle defined by the x, y coordinates of the vertices of the triangle)
wherein the origin of the pair of axes corresponds with the ray origin; (Saleh [0037]: More specifically, projecting the triangle into the viewspace of the ray transforms the coordinate system so that the ray points downwards in the z direction and the x and y components of the ray are 0 (although in some modifications, the ray may point upwards in the z direction, or in the positive or negative x or y directions, with the components in the other two axes being zero). The vertices of the triangle are transformed into this coordinate system. Such a transform allows the test for intersection to be made by simply asking whether the x, y coordinates of the ray fall within the triangle defined by the x, y coordinates of the vertices of the triangle)
for each edge of the convex polygon defined by two of the projected vertices, using the particular comparison operation to determine a sign of a signed parameter by performing a 2D cross product of the positions of the two projected vertices defining the edge; (Saleh [0047]: Next, barycentric coordinates for the triangle, U, V, W (shown in FIG. 6) are calculated in the following manner: U=area(Triangle CBT)=0.5*(C×B) V=area(Triangle ACT)=0.5*(A×C) W=area(Triangle BAT)=0.5*(B×A); Saleh [0048]: Here, the “x” indicates a cross-product and A, B, and C are the transformed vertices A.sub.trf, B.sub.trf, and C.sub.trf)
and determining whether the ray intersects the convex polygon based on the signs of the signed parameters determined for the edges of the convex polygon (Saleh [0048]: The signs of U, V, and W indicate whether the ray intersects the triangle).
With regards to claim 13, Saleh in view of Montrym further in view of Brown teaches all of the limitations of claim 12 above. Saleh further teaches wherein said determining whether the ray intersects the convex polygon comprises: determining that the ray intersects the convex polygon if the signed parameters determined for the edges of the convex polygon all have the same sign; (Saleh [0048]: More specifically, if U, V, and W are all positive, or if U, V, and W are all negative, then the ray is considered to intersect the triangle)
and determining that the ray does not intersect the convex polygon if it is not the case that the signed parameters determined for the edges of the convex polygon all have the same sign (Saleh [0048]: If the signs of U, V, and W are different, then the ray does not intersect the triangle).
With regards to claim 14, Saleh in view of Montrym further in view of Brown teaches all of the limitations of claim 12 above. Saleh further teaches wherein said determining whether the ray intersects the convex polygon comprises: determining that the ray intersects the convex polygon if it is determined that the ray passes on the inside of all of the edges of the convex polygon; (Saleh [0048]: More specifically, if U, V, and W are all positive, or if U, V, and W are all negative, then the ray is considered to intersect the triangle because the point T is inside the triangle in FIG. 6)
and determining that the ray does not intersect the convex polygon if it is determined that the ray passes on the outside of one or more of the edges of the convex polygon (Saleh [0048]: If the signs of U, V, and W are different, then the ray does not intersect the triangle because the point T is outside of the triangle).
With regards to claim 15, Saleh in view of Montrym further in view of Brown teaches all of the limitations of claim 12 above. Saleh further teaches wherein the 2D cross product, f(vi,vj), of the positions of the two projected vertices, vi and vj, defining an edge, is defined as f(vi,vj) = piqj - qipj, where pi and qi are components of the projected vertex vi along the respective axes of the pair of axes, and where pj and qj are components of the projected vertex vj along the respective axes of the pair of axes, (Saleh [0037]: The vertices of the triangle are transformed into this coordinate system. Such a transform allows the test for intersection to be made by simply asking whether the x, y coordinates of the ray fall within the triangle defined by the x, y coordinates of the vertices of the triangle; Saleh [0047]: Next, barycentric coordinates for the triangle, U, V, W (shown in FIG. 6) are calculated in the following manner: U=area(Triangle CBT)=0.5*(C×B) V=area(Triangle ACT)=0.5*(A×C) W=area(Triangle BAT)=0.5*(B×A); Saleh [0048]: Here, the “x” indicates a cross-product and A, B, and C are the transformed vertices A.sub.trf, B.sub.trf, and C.sub.trf)
and wherein the comparison operation comprises performing the 2D cross product and determining the sign of the result (Saleh [0048]: Here, the “x” indicates a cross-product and A, B, and C are the transformed vertices A.sub.trf, B.sub.trf, and C.sub.trf, which are shown in FIG. 6. The signs of U, V, and W indicate whether the ray intersects the triangle).
With regards to claim 17, Saleh in view of Montrym further in view of Brown teaches all of the limitations of claim 12 above. Saleh further teaches further comprising outputting an indication of a result of the determination of whether the ray intersects the convex polygon, wherein the outputted indication is used in the ray tracing system for rendering an image of a 3D scene (Saleh [0023]: The compute units 132 implement ray tracing, which is a technique that renders a 3D scene by testing for intersection between simulated light rays and objects in a scene).
With regards to claim 18, Saleh in view of Montrym further in view of Brown teaches all of the limitations of claim 12 above. Saleh further teaches wherein the method is performed in fixed function circuitry of the processing module (Saleh [0026]: In some examples, testing a ray against boxes and triangles (inside the acceleration structure traversal stage 304) is hardware accelerated (meaning that a fixed function hardware unit performs the steps for those tests)).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Saleh in view of Montrym further in view of Brown further in view of Malik further in view of Kulisch further in view of Nystad et al. (US 20120078987 A1) hereinafter Nystad.
With regards to claim 8, Saleh in view of Montrym further in view of Brown teaches all of the limitations of claim 1 above. Saleh fails to teach wherein said setting a second component of one or more of the vector floating point values to a non-zero, finite value comprises: for a received floating point value that is infinity, setting the second component of the corresponding vector floating point value to a non-zero, finite value.
wherein said setting a second component of one or more of the vector floating point values to a non-zero, finite value comprises: for a received floating point value [that is infinity, setting the second component of the corresponding vector floating point value to a non-zero, finite value] (Montrym [0092]: a plurality of vertex attributes that are all IEEE 32 bit floats; Montrym [0130]: In use the conversion module 514 serves to convert scalar vertex data to vector vertex data).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Saleh with the input floating point number as taught by Montrym. One of ordinary skill in the art would be motivated to make this combination because it would allow for the intersection test to be performed efficiently, as only one vector would be received per vertex instead of one number per coordinate. Also, their performance derives from a heavily pipelined architecture which operations on vectors and matrices can efficiently exploit as taught by Malik (Malik Page 163 Right Column).
Saleh in view of Montrym fails to teach [wherein said setting a second component of one or more of the vector floating point values to a non-zero, finite value comprises: for a received floating point value] that is infinity, setting the second component of the corresponding vector floating point value to a non-zero, finite value.
However, Nystad teaches [wherein said setting a second component of one or more of the vector floating point values to a non-zero, finite value comprises: for a received floating point value] that is infinity, setting the second component of the corresponding vector floating point value to a non-zero, finite value (Nystad [0066]: The overall action of FIG. 8 is to set components corresponding to negative infinity values to be -1 and values corresponding to positive infinity values to be +1).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Saleh in view of Montrym with setting the second component of the corresponding vector floating point value to a non-zero, finite value as taught by Nystad. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of the system as it could process infinite numbers.
Allowable Subject Matter
Claims 3, 6, 16, and 19-20 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 101 set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
While prior art teaches of handling zeros, prior art fails to teach setting the sign of the scalar result equal to the sign of the third component of the vector result.
While prior art teaches of promoting a scalar floating point to a vector floating point and setting a component equal to 1, prior art fails to teach setting a component equal to e2/e1, wherein e1>>e2.
While prior art teaches determining that the result of the 2D cross product is zero, prior art fails to teach setting the sign of the signed parameter to match the sign of a predetermined one of the floating point values used in the 2D cross product.
While prior art teaches of receiving a scalar floating point, promoting it to a vector, performing a comparison operation, and converting the vector result back to a scalar, prior art fails to teach setting the sign of the scalar result to the sign of the second component in the event that the first component’s magnitude is 0.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jakob O Gudas whose telephone number is (571)272-0695. The examiner can normally be reached Monday-Thursday: 7:30AM-5:00PM Friday: 7:30AM-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.O.G./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
Prosecution Insights