DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7-8, 10, 12, 14, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Terasawa (US Pat. 5942797) in view of Fisher (US Pub. 20110036234).
Regarding claims 1 and 3, Terasawa discloses in Fig. 1, column 5, lines 55-65, column 6, lines 9-15 a semiconductor device, comprising:
a substrate [22, 21, 23] including:
a ceramic substrate [21];
a top copper layer [22] on a top side of the ceramic substrate [21] including at least one lead; and
a bottom copper layer [23] on a bottom side of the ceramic substrate
at least one semiconductor die [1] having a bond pad electrically connected [by wires 51] to the at least one lead.
Terasawa fails to disclose
a plurality of metal filled dimples in the ceramic substrate;
wherein the plurality of metal filled dimples include a first portion under the top copper layer and a second portion on the bottom copper layer and wherein the first portion and the second portion of the plurality of metal filled dimples are separated by the ceramic substrate;
wherein the second portion of the plurality of metal filled dimples is not electrically connected to the at least one semiconductor die;
wherein positions of the first portion are offset relative to positions of the second portion.
Fisher discloses in Fig. 3, claims 1-2, 5, 6, paragraph [0053]-[0055], [0063]
a plurality of metal filled dimples [5 and 6] in the ceramic substrate [2];
wherein the plurality of metal filled dimples [5 and 6] include a first portion under a top metal layer [top layer 7] and a second portion on a bottom metal layer [bottom layer 7] and wherein the first portion and the second portion of the plurality of metal filled dimples [5 and 6] are separated by the ceramic substrate [2].
wherein the second portion of the plurality of metal filled dimples [5 and 6] is not electrically connected to the top metal layer [top layer 7];
wherein positions of the first portion are offset relative to positions of the second portion.
PNG
media_image1.png
271
493
media_image1.png
Greyscale
Terasawa discloses the top metal layer is the top copper layer, the bottom metal layer is the bottom copper layer and the top copper layer is electrically connected to the at least one semiconductor die [1]. Fisher discloses the second portion of the plurality of metal filled dimples [5 and 6] is not electrically connected to the top metal layer [top layer 7]. Thus, the combination of Fisher and Terasawa would result to “wherein the plurality of metal filled dimples include a first portion under the top copper layer and a second portion on the bottom copper layer; wherein the second portion of the plurality of metal filled dimples is not electrically connected to the at least one semiconductor die.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Fisher into the method of Terasawa to include a plurality of metal filled dimples in the ceramic substrate; wherein the plurality of metal filled dimples include a first portion under the top copper layer and a second portion on the bottom copper layer and wherein the first portion and the second portion of the plurality of metal filled dimples are separated by the ceramic substrate; wherein the second portion of the plurality of metal filled dimples is not electrically connected to the at least one semiconductor die; wherein positions of the first portion are offset relative to positions of the second portion. The ordinary artisan would have been motivated to modify Terasawa in the above manner for the purpose of providing a lighter, equally resistant ceramic structure without increasing its thickness; providing an improved ceramic substrate having a higher degree of protection against impact and improved security against multiple impact, at a reduced weight [paragraph [0017], [0021] of Fisher].
Regarding claims 7 and 18, Terasawa further discloses in Fig. 1, column 6, lines 1-15
wherein the top copper layer [22] further comprises a die pad, wherein the semiconductor die [1] is attached with a top side up on the die pad, and wherein the bond pad is electrically connected to the at least one lead by a bond wire [51].
Regarding claims 8 and 19, Terasawa discloses in Fig. 1
wherein the at least one semiconductor die [1] comprises a first semiconductor die [1 left] and a second semiconductor die [1 right], and wherein the top copper layer [22] further comprises a plurality of die pads.
Regarding claims 10, 12 and 14, Terasawa discloses in Fig. 1, column 5, lines 55-65, column 6, lines 9-15 a method of forming a semiconductor device, comprising:
forming a substrate [22, 21, 23] including:
providing a ceramic substrate [21];
bonding a top copper layer [22] on a top side of the ceramic substrate;
patterning the top copper layer [120] to form at least one lead;
bonding a bottom copper layer [23] on a bottom side of the ceramic substrate [21];
and attaching a semiconductor die to the substrate [22, 21, 23],
electrically connecting [by wires 51] a bond pad of the semiconductor die [1] to the at least one lead.
Terasawa fails to disclose
forming a plurality of indentations in the ceramic substrate;
wherein the plurality of metal filled dimples include a first portion under the top copper layer and a second portion on the bottom copper layer and wherein the first portion and the second portion of the plurality of metal filled dimples are separated by the ceramic substrate;
the second portion of the plurality of metal filled dimples is not electrically connected to the semiconductor die;
wherein positions of the first portion are offset relative to positions of the second portion.
Fisher discloses in Fig. 3, claims 1-2, 5, 6, paragraph [0053]-[0055], [0063]
forming a plurality of metal filled dimples [5 and 6] in the ceramic substrate [2];
wherein the plurality of metal filled dimples [5 and 6] include a first portion under a top metal layer [top layer 7] and a second portion on a bottom metal layer [bottom layer 7] and wherein the first portion and the second portion of the plurality of metal filled dimples [5 and 6] are separated by the ceramic substrate [2].
wherein the second portion of the plurality of metal filled dimples [5 and 6] is not electrically connected to the top metal layer [top layer 7];
wherein positions of the first portion are offset relative to positions of the second portion.
PNG
media_image1.png
271
493
media_image1.png
Greyscale
Terasawa discloses the top metal layer is the top copper layer, the bottom metal layer is the bottom copper layer and the top copper layer is electrically connected to the at least one semiconductor die [1]. Fisher discloses the second portion of the plurality of metal filled dimples [5 and 6] is not electrically connected to the top metal layer [top layer 7]. Thus, the combination of Fisher and Terasawa would result to “wherein the plurality of metal filled dimples include a first portion under the top copper layer and a second portion on the bottom copper layer; wherein the second portion of the plurality of metal filled dimples is not electrically connected to the at least one semiconductor die.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Fisher into the method of Terasawa to include forming a plurality of metal filled dimples in the ceramic substrate; wherein the plurality of metal filled dimples include a first portion under the top copper layer and a second portion on the bottom copper layer and wherein the first portion and the second portion of the plurality of metal filled dimples are separated by the ceramic substrate; wherein the second portion of the plurality of metal filled dimples is not electrically connected to the at least one semiconductor die; wherein positions of the first portion are offset relative to positions of the second portion. The ordinary artisan would have been motivated to modify Terasawa in the above manner for the purpose of providing a lighter, equally resistant ceramic structure without increasing its thickness; providing an improved ceramic substrate having a higher degree of protection against impact and improved security against multiple impact, at a reduced weight [paragraph [0017], [0021] of Fisher].
Claims 4, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Terasawa (US Pat. 5942797) in view of Fisher (US Pub. 20110036234) as applied to claims 1 and 10 above and further in view of Tanei et al. (US Pat. 5825632)
Regarding claims 4 and 13, Fisher discloses in Fig. 3, paragraph [0059]
wherein thicknesses of the plurality of metal filled dimples are 30% to 45% of a thickness of the ceramic substrate [“The depressions 5 may have a depths of 20-50% of the thickness of the ceramic tile 2”].
Terasawa, and Fisher fails to disclose
wherein the plurality of metal filled dimples comprise copper.
Tanei et al. discloses in Fig. 16, column 17, column 20, lines 57-61
wherein the plurality of metal filled dimples [9] comprise copper.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Tanei et al. into the method of Terasawa, and Fisher to include wherein the plurality of metal filled dimples comprise copper. The ordinary artisan would have been motivated to modify Terasawa, and Fisher in the above manner for the purpose of providing suitable metal material to fill dimples. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Terasawa (US Pat. 5942797) in view of Fisher (US Pub. 20110036234) as applied to claims 1 and 10 above and further in view of Hortaleza et al. (US Pub. 20030214049).
Regarding claim 5 and claim 15, Terasawa fails to disclose
wherein the plurality of metal filled dimples collectively extend over an entire area of the (at least one) semiconductor die.
However, Terasawa discloses an entire area of the top copper layer [22] extend over an entire area of the (at least one) semiconductor die [1]. Fisher discloses in Fig. 3 the plurality of metal filled dimples [5 and 6] collectively extend over an entire area of the top metal layer [7].
Thus, the combination of Fisher and Terasawa would result to “wherein the plurality of metal filled dimples collectively extend over an entire area of the (at least one) semiconductor die.”
For further support, Hortaleza et al. is cited.
Hortaleza et al. discloses in Fig. 1, paragraph [0016]
wherein the plurality of metal filled dimples [26] collectively extend over an entire area of the (at least one) semiconductor die [14].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Hortaleza et al. into the method of Fisher and Terasawa to include wherein the plurality of metal filled dimples collectively extend over an entire area of the (at least one) semiconductor die. The ordinary artisan would have been motivated to modify Fisher and Terasawa in the above manner for the purpose of allowing heat to dissipate from the die through the ceramic substrate [paragraph [0016] of Hortaleza et al.].
Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Terasawa (US Pat. 5942797) in view of Fisher (US Pub. 20110036234) as applied to claim 8 and claim 19 above and further in view of Bayan et al. (US Pub. 20120119343).
Regarding claims 9 and 20, Terasawa and Fisher fails to disclose
wherein the first semiconductor die comprises a discrete power transistor, and wherein the second semiconductor die comprises a power integrated circuit (IC).
Bayan et al. discloses in Fig. 1a, paragraph [0003]-[0005]
wherein the first semiconductor die [11 or 13] comprises a discrete power transistor, and wherein the second semiconductor die [14] comprises a power integrated circuit (IC).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Bayan et al. into the method of Terasawa and Fisher to include wherein the first semiconductor die comprises a discrete power transistor, and wherein the second semiconductor die comprises a power integrated circuit (IC). The ordinary artisan would have been motivated to modify Terasawa and Fisher in the above manner for the purpose of providing power module that can be used in power level shifters. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Terasawa (US Pat. 5942797) in view of Fisher (US Pub. 20110036234) as applied to claim 10 above and further in view of Hortaleza et al. (US Pub. 20030214049) and Brongersma (US Pub. 7088449)
Regarding claim 16, Terasawa and Fisher fails to disclose
determining positions for the metal filled dimples from identified high stress areas of the semiconductor device based on thermo-mechanical simulations or empirical test results.
Hortaleza et al. discloses the metal filled dimples [26] are formed in identified areas of the semiconductor device that extend over an entire area of a semiconductor die [14] similar to the positions of the claimed metal filled dimples shown in Applicant’s Fig. 2B. Therefore, the identified areas of the semiconductor device disclosed by Hortaleza et al. is equivalent to the claimed “identified high stress areas of the semiconductor device.”
In other words, Hortaleza et al. discloses
positions for the metal filled dimples are from identified high stress areas of the semiconductor device.
Brongersma discloses in column 3, lines 53-67, column 4, lines 5-15
determining positions for metal containing structures from identified areas of the semiconductor device based on empirical test results.
Thus, the combination of Brongersma and Hortaleza et al. would result to “determining positions for the metal filled dimples from identified high stress areas of the semiconductor device based on thermo-mechanical simulations or empirical test results.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Brongersma and Hortaleza et al. into the method of Terasawa and Fisher to include determining positions for the metal filled dimples from identified high stress areas of the semiconductor device based on empirical test results. The ordinary artisan would have been motivated to modify Terasawa and Fisher in the above manner for the purpose of providing fast, accurate and non-invasive measurement for identifying the metal-containing structure that allows heat to dissipate from the die through the ceramic substrate [column 3, lines 53-67, column 4, lines 5-15 and paragraph [0016] of Hortaleza et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant's arguments filed 12/11/2025 have been fully considered but they are not persuasive.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
In addition, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
The examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
In this case, Terasawa discloses a ceramic substrate [21]. Fisher discloses in Fig. 3, claims 1-2, 5, 6, paragraph [0053]-[0055], [0063] a plurality of metal filled dimples [5 and 6] in the ceramic substrate [2] to provide a lighter, equally resistant ceramic structure without increasing its thickness, to provide an improved ceramic substrate having a higher degree of protection against impact and improved security against multiple impact, at a reduced weight. In addition, Applicant’s assertion that “such modification is unnecessary and would make the structure of the ceramic insulating board of Terasawa more complicated without any practical benefits” without providing any evidence that a ceramic substrate for forming semiconductor device should not be made lighter and should never be subjected to any impact. The fact that Applicant might find the modification is unnecessary cannot prevent others from finding the modification is unnecessary. The fact that Applicant cannot recognize the benefit of combining Fisher and Terasawa does not mean there is no benefit of combining Fisher and Terasawa. "The fact that appellant has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious." Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985). Therefore, Applicant’s argument is Applicant’s own opinion and is not persuasive.
In contrast to Applicant’s assertion, as stated in the rejection there are benefits when incorporate the teachings of Fisher to Terasawa: “It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Fisher into the method of Terasawa to include a plurality of metal filled dimples in the ceramic substrate… for the purpose of providing a lighter, equally resistant ceramic structure without increasing its thickness; providing an improved ceramic substrate having a higher degree of protection against impact and improved security against multiple impact, at a reduced weight [paragraph [0017], [0021] of Fisher]”.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893