DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7-10, 12, 14, 18-22 are rejected under 35 U.S.C. 103 as being unpatentable over Terasawa (US Pat. 5942797) in view of Fisher (US Pub. 20110036234) and Robert (US Pub. 20120218714).
Regarding claims 1 and 3, Terasawa discloses in Fig. 1, column 5, lines 55-65, column 6, lines 9-15 a semiconductor device, comprising:
a substrate [22, 21, 23] including:
a ceramic substrate [21];
a top copper layer [22] on a top side of the ceramic substrate [21] including at least one lead and at least one die pad; and
a bottom copper layer [23] on a bottom side of the ceramic substrate
at least one semiconductor die [1] having a bond pad electrically connected [by wires 51] to the at least one lead.
Terasawa fails to disclose
a plurality of metal filled dimples in the ceramic substrate;
wherein the plurality of metal filled dimples include a first portion under the top copper layer and a second portion on the bottom copper layer and wherein the first portion and the second portion of the plurality of metal filled dimples are separated by the ceramic substrate;
wherein the second portion of the plurality of metal filled dimples is not electrically connected to the at least one semiconductor die;
wherein the first portion of the plurality of metal filled dimples locates only along edges of the at least one die pad;
wherein positions of the first portion are offset relative to positions of the second portion.
Fisher discloses in Fig. 3, claims 1-2, 5, 6, paragraph [0053]-[0055], [0063]
a plurality of metal filled dimples [5 and 6] in the ceramic substrate [2];
wherein the plurality of metal filled dimples [5 and 6] include a first portion under a top metal layer [top layer 7] and a second portion on a bottom metal layer [bottom layer 7] and wherein the first portion and the second portion of the plurality of metal filled dimples [5 and 6] are separated by the ceramic substrate [2].
wherein the second portion of the plurality of metal filled dimples [5 and 6] is not electrically connected to the top metal layer [top layer 7];
wherein positions of the first portion are offset relative to positions of the second portion.
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Robert discloses in Fig. 1, Fig. 3A-3B, Fig. 5B, Fig. 5C, paragraph [0022]-[0023], [0029], [0037]-[0038]
a plurality of filled dimples [115, 117 or 117’] in the ceramic substrate [114];
wherein the first portion of the plurality of filled dimples [115, 117 or 117’] locates only along edges of the at least one die pad [112].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Robert and Fisher into the method of Terasawa to include a plurality of metal filled dimples in the ceramic substrate; wherein the plurality of metal filled dimples include a first portion under the top copper layer and a second portion on the bottom copper layer and wherein the first portion and the second portion of the plurality of metal filled dimples are separated by the ceramic substrate; wherein the second portion of the plurality of metal filled dimples is not electrically connected to the at least one semiconductor die; wherein the first portion of the plurality of metal filled dimples locates only along edges of the at least one die pad; wherein positions of the first portion are offset relative to positions of the second portion. The ordinary artisan would have been motivated to modify Terasawa in the above manner for the purpose of providing a lighter, equally resistant ceramic structure without increasing its thickness; providing an improved ceramic substrate having a higher degree of protection against impact, improved security against multiple impact, at a reduced weight and reduced stresses along edges of the at least one die pad resulting from particular applications and operational conditions [paragraph [0017], [0021] of Fisher, paragraph [0035], [0038] of Robert].
Terasawa and Robert disclose the top metal layer is the top copper layer, the bottom metal layer is the bottom copper layer and the top copper layer is electrically connected to the at least one semiconductor die [1]. Fisher discloses the second portion of the plurality of metal filled dimples [5 and 6] is not electrically connected to the top metal layer [top layer 7]. Thus, the combination of Fisher, Robert and Terasawa would result to “wherein the second portion of the plurality of metal filled dimples is not electrically connected to the at least one semiconductor die.”
Regarding claims 7 and 18, Terasawa further discloses in Fig. 1, column 6, lines 1-15
wherein the semiconductor die [1] is attached with a top side up on the at least one die pad, and wherein the bond pad is electrically connected to the at least one lead by a bond wire [51].
Regarding claims 8 and 19, Terasawa discloses in Fig. 1, column 1
wherein the at least one semiconductor die [1] comprises a first semiconductor die [1 left] and a second semiconductor die [1 right], and wherein the first semiconductor die and the second semiconductor die comprise a discrete power transistor.
Robert also discloses in Fig. 1, paragraph [0024]
wherein the at least one semiconductor die [120] comprises a first semiconductor die [120 left] and a second semiconductor die [120 right], and wherein the first semiconductor die [120 left] and the second semiconductor die [120right] comprise a discrete power transistor.
Regarding claims 9 and 20, Robert discloses in Fig. 1, paragraph [0024]
wherein the at least one first semiconductor die [120] comprises a power integrated circuit (IC) [“the semiconductor devices of one or more power electronics assemblies are electrically coupled to form an inverter circuit”].
Regarding claims 10, 12 and 14, Terasawa discloses in Fig. 1, column 5, lines 55-65, column 6, lines 9-15 a method of forming a semiconductor device, comprising:
forming a substrate [22, 21, 23] including:
providing a ceramic substrate [21];
bonding a top copper layer [22] on a top side of the ceramic substrate;
patterning the top copper layer [120] to form at least one lead and at least one die pad;
bonding a bottom copper layer [23] on a bottom side of the ceramic substrate [21];
and attaching a semiconductor die to the substrate [22, 21, 23],
electrically connecting [by wires 51] a bond pad of the semiconductor die [1] to the at least one lead.
Terasawa fails to disclose
forming a plurality of indentations in the ceramic substrate;
wherein the plurality of metal filled dimples include a first portion under the top copper layer and a second portion on the bottom copper layer and wherein the first portion and the second portion of the plurality of metal filled dimples are separated by the ceramic substrate;
the second portion of the plurality of metal filled dimples is not electrically connected to the semiconductor die;
wherein the first portion of the plurality of metal filled dimples locates only along edges of the at least one die pad;
wherein positions of the first portion are offset relative to positions of the second portion.
Fisher discloses in Fig. 3, claims 1-2, 5, 6, paragraph [0053]-[0055], [0063]
forming a plurality of metal filled dimples [5 and 6] in the ceramic substrate [2];
wherein the plurality of metal filled dimples [5 and 6] include a first portion under a top metal layer [top layer 7] and a second portion on a bottom metal layer [bottom layer 7] and wherein the first portion and the second portion of the plurality of metal filled dimples [5 and 6] are separated by the ceramic substrate [2].
wherein the second portion of the plurality of metal filled dimples [5 and 6] is not electrically connected to the top metal layer [top layer 7];
wherein positions of the first portion are offset relative to positions of the second portion.
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Robert discloses in Fig. 1, Fig. 3A-3B, Fig. 5B, Fig. 5C, paragraph [0022]-[0023], [0029], [0037]-[0038]
a plurality of filled dimples [115, 117 or 117’] in the ceramic substrate [114];
wherein the first portion of the plurality of filled dimples [115, 117 or 117’] locates only along edges of the at least one die pad [112].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Robert and Fisher into the method of Terasawa to include a plurality of metal filled dimples in the ceramic substrate; wherein the plurality of metal filled dimples include a first portion under the top copper layer and a second portion on the bottom copper layer and wherein the first portion and the second portion of the plurality of metal filled dimples are separated by the ceramic substrate; wherein the second portion of the plurality of metal filled dimples is not electrically connected to the at least one semiconductor die; wherein the first portion of the plurality of metal filled dimples locates only along edges of the at least one die pad; wherein positions of the first portion are offset relative to positions of the second portion. The ordinary artisan would have been motivated to modify Terasawa in the above manner for the purpose of providing a lighter, equally resistant ceramic structure without increasing its thickness; providing an improved ceramic substrate having a higher degree of protection against impact, improved security against multiple impact, at a reduced weight and reduced stresses along edges of the at least one die pad resulting from particular applications and operational conditions [paragraph [0017], [0021] of Fisher, paragraph [0035], [0038] of Robert].
Terasawa and Robert disclose the top metal layer is the top copper layer, the bottom metal layer is the bottom copper layer and the top copper layer is electrically connected to the at least one semiconductor die [1]. Fisher discloses the second portion of the plurality of metal filled dimples [5 and 6] is not electrically connected to the top metal layer [top layer 7]. Thus, the combination of Fisher, Robert and Terasawa would result to “wherein the second portion of the plurality of metal filled dimples is not electrically connected to the at least one semiconductor die.”
Regarding claims 21-22, Robert discloses in Fig. 5B, Fig. 5C, paragraph [0038]
wherein the first portion of the plurality of filled dimples [117’] locates only at corners of the at least one die pad [112][Robert discloses “stress-relief through-features 117' may be located near the corners of the first and second metal layers 112, 116 to aid in relieving thermally-induced stress located at such corners…The stress-relief through-features 117' that fully extend through all of the layers of the insulated metal substrate.” Therefore, first portion/top portion of the plurality of filled dimples formed in layer 114 locates only at corners of die pad 112].
Fisher discloses the filled dimples are metal filled dimples.
Thus, the combination of Fisher and Robert suggests “the first portion of the plurality of metal filled dimples locates only at corners of the at least one die pad.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Robert into the method of Terasawa to include wherein the first portion of the plurality of metal filled dimples locates only at corners of the at least one die pad. The ordinary artisan would have been motivated to modify Terasawa in the above manner for the purpose of reducing stresses at corners of the at least one die pad [paragraph [0035], [0038] of Robert].
Claims 4, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Terasawa (US Pat. 5942797) in view of Fisher (US Pub. 20110036234) and Robert (US Pub. 20120218714) as applied to claims 1 and 10 above and further in view of Tanei et al. (US Pat. 5825632).
Regarding claims 4 and 13, Fisher discloses in Fig. 3, paragraph [0059]
wherein thicknesses of the plurality of metal filled dimples are 30% to 45% of a thickness of the ceramic substrate [“The depressions 5 may have a depths of 20-50% of the thickness of the ceramic tile 2”].
Terasawa, Robert and Fisher fails to disclose
wherein the plurality of metal filled dimples comprise copper.
Tanei et al. discloses in Fig. 16, column 17, column 20, lines 57-61
wherein the plurality of metal filled dimples [9] comprise copper.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Tanei et al. into the method of Terasawa, Robert and Fisher to include wherein the plurality of metal filled dimples comprise copper. The ordinary artisan would have been motivated to modify Terasawa, Robert and Fisher in the above manner for the purpose of providing suitable metal material to fill dimples. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant's arguments filed 09/16/2026 have been fully considered but they are not persuasive.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The rejection does not modify Fisher to incorporate the teachings of Robert. Robert is cited to teach forming filled dimples only along edges of the at least one die pad. Fisher is cited to teach the layout of the filled dimples.
The rejection modified Terasawa by incorporating the teachings of Robert and Fisher. The rejection stated “It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Robert and Fisher into the method of Terasawa to include a plurality of metal filled dimples in the ceramic substrate; wherein the plurality of metal filled dimples include a first portion under the top copper layer and a second portion on the bottom copper layer and wherein the first portion and the second portion of the plurality of metal filled dimples are separated by the ceramic substrate; wherein the second portion of the plurality of metal filled dimples is not electrically connected to the at least one semiconductor die; wherein the first portion of the plurality of metal filled dimples locates only along edges of the at least one die pad; wherein positions of the first portion are offset relative to positions of the second portion. The ordinary artisan would have been motivated to modify Terasawa in the above manner for the purpose of providing a lighter, equally resistant ceramic structure without increasing its thickness; providing an improved ceramic substrate having a higher degree of protection against impact, improved security against multiple impact, at a reduced weight and reduced stresses along edges of the at least one die pad resulting from particular applications and operational conditions [paragraph [0017], [0021] of Fisher, paragraph [0035], [0038] of Robert].”
In addition, “[d]isclosed examples and preferred embodiments do not constitute a teaching away from a broader disclosure or nonpreferred embodiments. In re Susi, 440 F.2d 442, 169 USPQ 423 (CCPA 1971)… "[t]he prior art’s mere disclosure of more than one alternative does not constitute a teaching away from any of these alternatives because such disclosure does not criticize, discredit, or otherwise discourage the solution claimed…." In re Fulton, 391 F.3d 1195, 1201, 73 USPQ2d 1141, 1146 (Fed. Cir. 2004).” MPEP 2123 II.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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