Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Remarks
The Examiner acknowledges and generally agrees with the short summary of the previous office action. The Examiner acknowledges amendments to the claims and specification.
35 U.S.C. 112(B)
The Examiner acknowledges the amendments to the claims, however, the Examiner notes that the applicant seemingly made no further arguments or remarks regarding the 112(b) rejections beyond that the claims have been amended, and thus the rejections should be withdrawn. The Examiner respectfully disagrees in regards to claims 7, and 14. The Examiner withdraws 112(b) rejections related to claims 3, 4, and 17. See new reasons for rejection due to amendments below.
35 U.S.C. 103
The applicant argues that an amendment was made to claim 1 which was indicated as allowable subject matter (remarks page 15 paragraph 5). The Examiner respectfully disagrees that the amendment resembles the indicated allowable subject matter. The Examiner respectfully points out that the claim they reference as the incorporated claim which was indicated as allowable, is claim 22, which is dependent on claim 21. In the Non-Final Office Action mailed on 11/18/2025, page 29 paragraph 2, the Examiner stated 22 was part of the indicated allowable subject matter, however, the Examiner wrote that it would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The applicant seemingly did not include the intervening claim of claim 21, which was the claim that had limitations italicized as primary reason for indication of allowable subject matter.
The applicant further argues (Remarks page 15 paragraph 6 – page 16 paragraph 2) that Chou et al., (U.S. Patent Application Publication 2022/0351032 A1), hereinafter, “Chou”, fails to teach dynamic mapping of an ADC adjusting its internal input range so that the maximum magnitude of Vsig is mapped to the reference voltage. The Examiner respectfully points to the Non-Final Office Action mailed on 11/18/2025, page 8 regarding the Examiner combining Noack et al., (U.S. Patent Application Publication 2023/0041759 A1), hereinafter, “Noack” with Chou to alleviate this limitation not explicitly taught by Chou.
The applicant further continues arguing (Remarks page 16 paragraph 3 – page 17 paragraph 3) that Noack lacks the teaching of deriving a reference voltage from the maximum output current of a memory array, as well as determining a maximum value of an input range based on that specific memory-derived reference. The Examiner respectfully points to the Non-Final Office Action mailed on 11/18/2025, page 8 regarding the Examiner combining Noack with Chou. The Examiner merely uses Noack because the part of the ADC that does these determinations is an internal comparator circuit, Chou has an ADC in series with a comparator, and Noack teaches an internal comparator in an ADC.
The applicant further continues arguing (Remarks page 17 paragraph 4-6) that Eyole does not suggest the configuration of an ADC determining a maximum input range such that the signal’s maximum magnitude is mapped to the reference voltage. Furthermore arguing that Eyole has static response to a threshold not a dynamically calibrated one. The Examiner respectfully points out that in the Non-Final Office Action dated 11/18/2025, the Examiner did not rely on Eyole to have a configuration of an ADC determining a maximum input range such that the signal’s maximum magnitude is mapped to the reference voltage. The Examiner relied on the combination of Eyole with Chou in view of Noack with Eyole teaching a comparator taking in a reference voltage and an input voltage, and adjusting the input voltage to the reference voltage based on the comparison. Furthermore the Examiner respectfully suggests that this is seemingly the same as what the applicant is arguing the claimed invention does, a maximum magnitude is mapped to the reference voltage.
The applicant continues arguing (Remarks page 17 paragraph 7-8 – page 18 paragraph 1) that the referenced prior art does not teach or suggest the claimed invention and thus should be allowable. The Examiner respectfully disagrees. See new reasons for rejection below.
Conclusion
The Examiner acknowledges the applicant’s conclusion statements.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, claim 1 recites the limitation of: “wherein each of the plurality of analog-to-digital converters determines a maximum value of an input range of the analog signal voltage based on the reference voltage”. It is unclear what is meant by the “analog-to-digital converters determines a maximum value of an input range of the analog signal voltage” because the analog voltage isn’t generated by the analog-to-digital converters, they are received by the analog-to-digital converters, so it is unclear how they determine the maximum value of an input range of the analog signal voltage. In the Remarks (page 15 paragraph 6) the applicant points to the applicant’s figure 12D in reference to this limitation. The applicant continued discussing figure 12D in the example that an input analog signal is 11mV, and exceeds the reference voltage of 10mV, the ADC adjusts its internal input range so that the maximum magnitude of Vsig is correctly mapped to the reference voltage of Vref. It is unclear how the ADC determine a max value of an input range if the example shown of the applicant’s figure 12D shows that the analog value is still input into the ADC. In the Figure 12D, and in the applicant’s mentioned remarks, the ADC seemingly is merely comparing Vsig to Vref and adjusting the output accordingly. For purposes of examination, the Examiner interprets this limitation to mean that the ADC has an analog signal voltage as an input and compares it to the reference voltage, and adjusts the voltage according to the comparison.
Claims 2-14 inherit the same deficiency of claim 1 based on dependence.
Regarding claim 7, claim 7 recites the limitation of: “wherein each of the plurality of voltage buffers is configured to receive the reference voltage and determine a maximum value of an output voltage to be equal to a magnitude of the reference voltage.” Claim 7 is dependent on claim 1. Claim 1 recites the limitation of: “wherein each of the plurality of analog-to-digital converters determines a maximum value of an input range of the analog signal voltage based on the reference voltage”. It is unclear if the limitation of claim 7 is meant to replace the action of the analog-to-digital converters of claim 1 or if it is somehow supposed to act in addition to the analog-to-digital converters of claim 1.
Claim 8 inherits the same deficiency as claim 7 based on dependance.
Regarding claim 14, claim 14 recites the limitation of: “a maximum conductance value stored in a second memory cell of the plurality of second memory cells corresponds to the largest one of conductance values stored in a subset of the plurality of first memory cells coupled to a row line to which the second memory cell is coupled”. Claim 14 is dependent upon claim 1. Claim 1 recites the limitation of: “a plurality of second memory cells each storing a maximum conductance value determined among a subset of the plurality of conductance values”, and “the maximum conductance value stored in each of the plurality of second memory cells”. Claim 1 seemingly indicates a singular conductance value as a maximum conductance value for the plurality of second memory cells, whereas claim 14 seemingly indicates potentially a different maximum conductance value per row line. It is unclear how the limitation of claim 14 can coincide with the limitation of claim 1.
Regarding claim 15, claim 15 recites the limitation of: “wherein each of the plurality of analog-to-digital converters determines a maximum value of an input range of the analog signal voltage based on the reference voltage, such that a maximum magnitude of the analog signal voltage is mapped to the reference voltage.” It is unclear what is meant by the “analog-to-digital converters determines a maximum value of an input range of the analog signal voltage” because the analog voltage isn’t generated by the analog-to-digital converters, they are received by the analog-to-digital converters, so it is unclear how they determine the maximum value of an input range of the analog signal voltage. In the Remarks (page 15 paragraph 6) the applicant points to the applicant’s figure 12D in reference to this limitation. The applicant continued discussing figure 12D in the example that an input analog signal is 11mV, and exceeds the reference voltage of 10mV, the ADC adjusts its internal input range so that the maximum magnitude of Vsig is correctly mapped to the reference voltage of Vref. It is unclear how the ADC determine a max value of an input range if the example shown of the applicant’s figure 12D shows that the analog value is still input into the ADC. In the Figure 12D, and in the applicant’s mentioned remarks, the ADC seemingly is merely comparing Vsig to Vref and adjusting the output accordingly. For purposes of examination, the Examiner interprets this limitation to mean that the ADC has an analog signal voltage as an input and compares it to the reference voltage, and adjusts the voltage according to the comparison.
Claims 16-19 inherit the same deficiency of claim 1 based on dependence.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 9, 13-15, 18, 20, 23, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Noack.
With regards to claim 1, the Examiner notes that the preamble of “An electronic device,” is awarded no patentable weight due to it not being referred back to in the body of the claim nor in the dependent claims.
Chou teaches:
comprising: a crossbar array (Fig. 4B item 420 (Compute in memory array));
including: a plurality of first memory cells respectively storing a plurality of conductance values; (Fig. 4B items 420 (Compute in memory array), 326 (memory cells); [0081] regarding the memory cells programed with a plurality of conductance values);
a plurality of second memory cells each storing a maximum conductance value determined among a subset of the plurality of conductance values, the subset corresponding to the respective second memory cell; (Fig. 4B items 420 (Compute in memory array), 426 (reference cells); [0135] regarding reference cells programed to Gmax as a maximum conductance value);
a plurality of row lines coupled to the plurality of first memory cells and the plurality of second memory cells and supplying a plurality of input voltages to the plurality of first memory cells and the plurality of second memory cells; (Fig. 4B items 420 (Compute in memory array), 424/324 (row lines), 326 (memory cells), 426 (reference cells));
a plurality of first column lines coupled to the plurality of first memory cells and configured to respectively output a plurality of output currents generated using the plurality of input voltages and the plurality of conductance values; (Fig. 4B items 420 (Compute in memory array), 326 (memory cells), 322 (column lines), i1, i2, i3, i4);
and a second column line coupled to the plurality of second memory cells and configured to output a maximum output current generated using the plurality of input voltages and the maximum conductance value stored in each of the plurality of second memory cells; (Fig. 4B items 420 (Compute in memory array), 426 (reference cells), 422 (column line), iref; [0135] regarding a maximum current generated on the reference column due to a maximum conductance at the reference cells);
and a plurality of analog-to-digital converters respectively coupled to the plurality of first column lines, (Fig. 4B items 420 (Compute in memory array), 322 (column lines), 340 (Analog to digital converters connected to column lines), 430 (Saturation detection units));
each of the plurality of analog-to-digital converters receiving an analog signal voltage corresponding to each of the plurality of output currents (Fig. 4B items 420 (Compute in memory array), 322 (column lines), 340 (Analog to digital converters connected to column lines), 430 (Saturation detection units));
and configured to generate a digital signal, (Fig. 4B items 340 (Analog to digital converters); [0169] regarding analog to digital converters converting analog signals into output data);
the reference voltage being generated from the maximum output current, wherein each of. (Fig. 4B items 340 (Analog to digital converters); [0135] regarding a maximum current generated on the reference column due to a maximum conductance at the reference cells).
Chou does not explicitly teach:
analog-to-digital converters receiving a reference voltage and an analog signal voltage
configured to generate a digital signal corresponding to the analog signal voltage based on the reference voltage
the plurality of analog-to-digital converters determines a maximum value of an input range of to the analog signal voltage based on the reference voltage such that a maximum magnitude of the analog signal voltage is mapped to the reference voltage.
However, Chou teaches a plurality of Saturation Detection Units (SDUs), connected to each of the first columns which include a comparator, inputting Vref signals and analog voltages from the first columns to compare (Fig. 4; [0127] regarding SDU units comparing column voltages to reference voltages). Chou further teaches analog-to-digital converters coupled to the SDUs which output digital signals from the input voltages (Fig. 4).
Noack teaches:
analog-to-digital converters receiving a reference voltage and an analog signal voltage ([0187] regarding an analog to digital converter including a comparator, comparing an output voltage with a reference voltage)
configured to generate a digital signal corresponding to the analog signal voltage based on the reference voltage ([0187] regarding an analog to digital converter including a comparator, comparing an output voltage with a reference voltage, and outputting a digital result based on the comparison)
the plurality of analog-to-digital converters determines a maximum value of an input range of to the analog signal voltage based on the reference voltage such that a maximum magnitude of the analog signal voltage is mapped to the reference voltage. ([0187] regarding an analog to digital converter including a comparator, comparing an output voltage with a reference voltage, and outputting a digital result based on the comparison)
Therefore, it would have been obvious before the effective filing date of the claimed invention
to one of ordinary skill in the art to which said subject matter pertains to combine the SDUs and analog -
to-digital converters of Chou with the combined analog-to-digital converter and comparator of Noack
because this would be considered a simple substitution of one known element for another to obtain
predictable results, MPEP 2141 (III)(B).
With regards to claim 2, Chou in view of Noack teaches the electronic device according to claim 1, as referenced above.
Chou further teaches:
wherein: the plurality of first column lines are configured to output the plurality of output currents by performing a multiply-accumulate operation on the plurality of input voltages and the plurality of conductance values, (Fig. 4B items 420 (Compute in memory array), 326 (memory cells); [0081] regarding the memory cells programed with a plurality of conductance values; [0079] regarding each column of cells calculates a dot product);
and the second column line is configured to output the maximum output current by performing a multiply-accumulate operation on the plurality of input voltages (Fig. 4B items 420 (Compute in memory array), 426 (reference cells); [0079] regarding each column of cells calculates a dot product);
and the maximum conductance value stored in each of the plurality of second memory cells. ([0135] regarding a maximum current generated on the reference column due to a maximum conductance at the reference cells).
With regards to claim 5, Chou in view of Noack teaches the electronic device according to claim 1, as referenced above.
Chou further teaches:
further comprising: a plurality of first current-to-voltage converters, (Fig. 4B regarding i1, i2, i3, i4, iref, SDU, SRU, Vref; [0079] regarding current produced on columns due to voltage applied to rows containing voltage cells with conductance; [0127] regarding column lines 322 provide voltage level for comparison to the reference voltage in an SDU. As interpreted by the Examiner, Fig. 4B shows current produced in the array, Fig. 4 further shows that the current lines turn to current at some point in the circuit (Vref for example), [0127] discusses the columns of the array (as the first columns) providing to the SDU units a voltage level to compare a reference voltage to. As interpreted by the Examiner, not shown in Fig. 4B, there must be current to voltage converters for each row in order to go from a current in each column to a voltage in each SDU);
each configured to receive an output current from a corresponding one of the plurality of first column lines and convert the output current into an analog signal voltage; (Fig. 4B regarding i1, i2, i3, i4, iref, SDU, SRU, Vref; [0079] regarding current produced on columns due to voltage applied to rows containing voltage cells with conductance; [0127] regarding column lines 322 provide voltage level for comparison to the reference voltage in an SDU. As interpreted by the Examiner, Fig. 4B shows current produced in the array, Fig. 4 further shows that the current lines turn to current at some point in the circuit (Vref for example), [0127] discusses the columns of the array (as the first columns) providing to the SDU units a voltage level to compare a reference voltage to. As interpreted by the Examiner, not shown in Fig. 4B, there must be current to voltage converters for each row in order to go from a current in each column to a voltage in each SDU);
and a second current-to-voltage converter configured to receive the maximum output current from the second column line (Fig. 4B regarding i1, i2, i3, i4, iref, SDU, SRU, Vref; [0079] regarding current produced on columns due to voltage applied to rows containing voltage cells with conductance; [0139] regarding the SRU taking input of a reference current from the reference column and outputting a reference voltage);
and convert the maximum output current into the reference voltage. (Fig. 4B regarding i1, i2, i3, i4, iref, SDU, SRU, Vref; [0079] regarding current produced on columns due to voltage applied to rows containing voltage cells with conductance; [0139] regarding the SRU taking input of a reference current from the reference column and outputting a reference voltage).
With regards to claim 9, Chou in view of Noack teaches the electronic device according to claim 1, as referenced above.
Chou further teaches:
further comprising: a digital signal processor configured to output a digital operation signal based on a digital signal, (Fig. 4B items 405, 340 (ADC outputs); [0132]- [0133] regarding the circuitry of the compute in memory array as signal processing circuitry; [0127] regarding SDU units comparing column voltages to reference voltages);
output from one of the plurality of analog- to-digital converters, and the reference voltage. (Fig. 4B item 405; [0132]- [0133] regarding the circuitry of the compute in memory array as signal processing circuitry; [0127] regarding SDU units comparing column voltages to reference voltages ; As interpreted by the Examiner, Chou describes the compute in memory circuit 405 as signal processing circuitry, the digital output from the circuitry is an output computed by using the reference voltage and outputting from the analog-to-digital converters).
With regards to claim 13, Chou in view of Noack teaches the electronic device according to claim 1, as referenced above.
Chou further teaches:
wherein the maximum conductance value stored in each of the plurality of second memory cells corresponds to the largest one of the plurality of conductance values. (Fig. 4B items 420 (Compute in memory array), 426 (reference cells); [0135] regarding reference cells programed to Gmax as a maximum conductance value).
With regards to claim 14, Chou in view of Noack teaches the electronic device according to claim 1, as referenced above.
Chou further teaches:
wherein a maximum conductance value stored in a second memory cell of the plurality of second memory cells corresponds to the largest one of conductance values stored in a subset of the plurality of first memory cells coupled to a row line to which the second memory cell is coupled. (Fig. 4B items 420 (Compute in memory array), 426 (reference cells); [0087] regarding max as a maximum conductance value from a memory cell 326 (which is in the columns 322 as a first set of columns); [0135] regarding reference cells programed to Gmax as a maximum conductance value).
With regards to claim 15, the Examiner notes that the preamble of “An electronic device,” is awarded no patentable weight due to it not being referred back to in the body of the claim nor in the dependent claims.
Chou teaches:
comprising: a crossbar array (Fig. 4B item 420 (Compute in memory array));
including: a plurality of first memory cells respectively storing a plurality of conductance values; (Fig. 4B items 420 (Compute in memory array), 326 (memory cells); [0081] regarding the memory cells programed with a plurality of conductance values);
a plurality of second memory cells each storing a maximum conductance value determined among a subset of the plurality of conductance values, the subset corresponding to the respective second memory cell; (Fig. 4B items 420 (Compute in memory array), 426 (reference cells); [0135] regarding reference cells programed to Gmax as a maximum conductance value);
a plurality of row lines coupled to the plurality of first memory cells and the plurality of second memory cells and supplying a plurality of input voltages to the plurality of first memory cells and the plurality of second memory cells; (Fig. 4B items 420 (Compute in memory array), 424/324 (row lines), 326 (memory cells), 426 (reference cells));
a plurality of first column lines coupled to the plurality of first memory cells and configured to respectively output a plurality of output currents generated using the plurality of input voltages and the plurality of conductance values; (Fig. 4B items 420 (Compute in memory array), 326 (memory cells), 322 (column lines), i1, i2, i3, i4);
and a second column line coupled to the plurality of second memory cells and configured to output a maximum output current generated using the plurality of input voltages and the maximum conductance value stored in each of the plurality of second memory cells; (Fig. 4B items 420 (Compute in memory array), 426 (reference cells), 422 (column line), iref);
and a plurality of analog-to-digital converters respectively coupled to the plurality of first column lines, (Fig. 4B items 420 (Compute in memory array), 322 (column lines), 340 (Analog to digital converters connected to column lines), 430 (Saturation detection units));
each of the plurality of analog-to-digital converters receiving an analog signal voltage corresponding to each of the plurality of output currents (Fig. 4B items 420 (Compute in memory array), 322 (column lines), 340 (Analog to digital converters connected to column lines), 430 (Saturation detection units));
and configured to convert the analog signal voltage into a digital signal corresponding to the analog signal voltage, (Fig. 4B items 340 (Analog to digital converters); [0169] regarding analog to digital converters converting analog signals into output data);
the reference voltage being generated from the maximum output current (Fig. 4B items 426 (reference cells), 422 (reference column), iref, Vref; [0135] regarding a maximum current generated from reference cells with a maximum conductance)
Chou does not explicitly teach:
analog-to-digital converters receiving a reference voltage and an analog signal voltage
by applying a gain corresponding to the reference voltage to the analog signal voltage
wherein each of the plurality of analog-to-digital converters determines a maximum value of an input range of the analog signal voltage based on the reference voltage, such that a maximum magnitude of the analog signal voltage is mapped to the reference voltage
However, Chou teaches a plurality of Saturation Detection Units (SDUs) connected to each of the first columns which include a comparator, inputting Vref signals and analog voltages from the first columns to compare. Chou further teaches analog-to-digital converters coupled to the SDUs which output digital signals from the input voltages.
Noack teaches:
analog-to-digital converters receiving a reference voltage and an analog signal voltage ([0187] regarding an analog to digital converter including a comparator, comparing an output voltage with a reference voltage)
by applying a gain1 corresponding to the reference voltage to the analog signal voltage ([0187] regarding an analog to digital converter including a comparator, comparing an output voltage with a reference voltage, and outputting a digital result based on the comparison)
wherein each of the plurality of analog-to-digital converters determines a maximum value of an input range of the analog signal voltage based on the reference voltage, such that a maximum magnitude of the analog signal voltage is mapped to the reference voltage ([0187] regarding an analog to digital converter including a comparator, comparing an output voltage with a reference voltage, and outputting a digital result based on the comparison)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the SDUs and analog - to-digital converters of Chou with the combined analog-to-digital converter and comparator of Noack because this would be considered a simple substitution of one known element for another to obtain predictable results, MPEP 2141 (III)(B).
With regards to claim 18, Chou in view of Noack teaches The electronic device according to claim 15, as referenced above.
Chou further teaches:
further comprising: a plurality of first current-to-voltage converters, (Fig. 4B regarding i1, i2, i3, i4, iref, SDU, SRU, Vref; [0079] regarding current produced on columns due to voltage applied to rows containing voltage cells with conductance; [0127] regarding column lines 322 provide voltage level for comparison to the reference voltage in an SDU. As interpreted by the Examiner, Fig. 4B shows current produced in the array, Fig. 4 further shows that the current lines turn to current at some point in the circuit (Vref for example), [0127] discusses the columns of the array (as the first columns) providing to the SDU units a voltage level to compare a reference voltage to. As interpreted by the Examiner, not shown in Fig. 4B, there must be current to voltage converters for each row in order to go from a current in each column to a voltage in each SDU);
each configured to receive an output current from a corresponding one of the plurality of first column lines and convert the output current into the analog signal voltage; (Fig. 4B regarding i1, i2, i3, i4, iref, SDU, SRU, Vref; [0079] regarding current produced on columns due to voltage applied to rows containing voltage cells with conductance; [0127] regarding column lines 322 provide voltage level for
comparison to the reference voltage in an SDU. As interpreted by the Examiner, Fig. 4B shows current produced in the array, Fig. 4 further shows that the current lines turn to current at some point in the circuit (Vref for example), [0127] discusses the columns of the array (as the first columns) providing to the SDU units a voltage level to compare a reference voltage to. As interpreted by the Examiner, not shown in Fig. 4B, there must be current to voltage converters for each row in order to go from a current in each column to a voltage in each SDU);
and a second current-to-voltage converter configured to receive the maximum output current
from the second column line and convert the maximum output current into the reference voltage. (Fig. 4B regarding i1, i2, i3, i4, iref, SDU, SRU, Vref; [0079] regarding current produced on columns due to voltage applied to rows containing voltage cells with conductance; [0139] regarding the SRU taking input of a reference current from the reference column and outputting a reference voltage).
With regards to claim 20, Chou teaches:
A method of operating an electronic device, (Fig. 4B item 420 (Compute in memory array));
the electronic device comprising a crossbar array including a plurality of row lines, (Fig. 4B item 420 (Compute in memory array));
a plurality of first column lines, (Fig. 4B items 420 (Compute in memory array), 326 (memory cells), 322 (column lines), i1, i2, i3, i4);
a second column line, (Fig. 4B items 420 (Compute in memory array), 426 (reference cells), 422 (column line), iref);
and a plurality of first memory cells coupled to the plurality of row lines and the plurality of first column lines, (Fig. 4B items 420 (Compute in memory array), 326 (memory cells); [0081] regarding the memory cells programed with a plurality of conductance values);
and a plurality of second memory cells coupled to the plurality of row lines and the second column line, (Fig. 4B items 420 (Compute in memory array), 426 (reference cells); [0135] regarding reference cells programed to Gmax as a maximum conductance value);
the method comprising: receiving a plurality of input voltages through the plurality of row lines; (Fig. 4B items 420 (Compute in memory array), 424/324 (row lines), 326 (memory cells), 426 (reference cells));
generating a maximum output current based on a maximum conductance value, stored in each of the plurality of second memory cells, and the plurality of input voltages, (Fig. 4B items 420 (Compute in memory array), 426 (reference cells), 422 (column line), iref; [0135] regarding a maximum current generated on the reference column due to a maximum conductance at the reference cells);
the maximum conductance value corresponding to the largest one of a plurality of conductance values stored in a subset of the plurality of first memory cells, the subset corresponding to the respective second memory cell; (Fig. 4B items 420 (Compute in memory array), 426 (reference cells); [0135] regarding reference cells programed to Gmax as a maximum conductance value);
converting the maximum output current into a reference voltage; (Fig. 4B regarding i1, i2, i3, i4, iref, SDU, SRU, Vref; [0079] regarding current produced on columns due to voltage applied to rows containing voltage cells with conductance; [0139] regarding the SRU taking input of a reference current from the reference column and outputting a reference voltage);
and determining, based on the reference voltage, an analog signal voltage, which is input to each of a plurality of analog-to-digital converters respectively coupled to the plurality of first column lines. (Fig. 4B items 340 (Analog to digital converters); [0135] regarding a maximum current generated on the reference column due to a maximum conductance at the reference cells).
Chou does not explicitly teach:
a maximum value of an input range of an analog signal voltage which is input to a analog -to- digital converters
such that a maximum magnitude of the analog signal voltage is mapped to the reference voltage.
However, Chou teaches a plurality of Saturation Detection Units (SDUs) connected to each of the first columns which include a comparator, inputting Vref signals and analog voltages from the first columns to compare. Chou further teaches analog-to-digital converters coupled to the SDUs which output digital signals from the input voltages.
Noack teaches:
a maximum value of an input range of an analog signal voltage which is input to a analog -to- digital converters ([0187] regarding an analog to digital converter including a comparator, comparing an output voltage with a reference voltage, and outputting a digital result based on the comparison)
such that a maximum magnitude of the analog signal voltage is mapped to the reference voltage. ([0187] regarding an analog to digital converter including a comparator, comparing an output voltage with a reference voltage, and outputting a digital result based on the comparison)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the SDUs and analog - to-digital converters of Chou with the combined analog-to-digital converter and comparator of Noack because this would be considered a simple substitution of one known element for another to obtain predictable results, MPEP 2141 (III)(B).
With regards to claim 23, Chou in view of Noack teaches The method according to claim 20, as referenced above.
Chou further teaches:
wherein the determining further comprises: the analog signal voltage. (Fig. 4B items 340 (Analog to digital converters); [0169] regarding analog to digital converters converting analog signals into output data).
Chou does not explicitly teach:
applying a gain1 corresponding to the reference voltage to the analog signal voltage
However, Chou teaches a plurality of Saturation Detection Units (SDUs), connected to each of the first columns which include a comparator, inputting Vref signals and analog voltages from the first columns to compare (Fig. 4; [0127] regarding SDU units comparing column voltages to reference voltages). Chou further teaches analog-to-digital converters coupled to the SDUs which output digital signals from the input voltages (Fig. 4).
Noack teaches:
applying a gain1 corresponding to the reference voltage to the analog signal voltage ([0187] regarding an analog to digital converter including a comparator, comparing an output voltage with a reference voltage, and outputting a digital result based on the comparison)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the SDUs and analog - to-digital converters of Chou with the combined analog-to-digital converter and comparator of Noack because this would be considered a simple substitution of one known element for another to obtain predictable results, MPEP 2141 (III)(B).
With regards to claim 24, Chou in view of Noack teaches the method according to claim 20, as referenced above.
Chou teaches:
further comprising: generating a plurality of output currents based on the plurality of input voltages and the plurality of conductance values; (Fig. 4B items 420 (Compute in memory array), 326 (memory cells), 322 (column lines), i1, i2, i3, i4);
and converting a plurality of analog signal voltages into a plurality of digital signals through the plurality of analog-to-digital converters, (Fig. 4B regarding i1, i2, i3, i4, iref, SDU, SRU, Vref; [0079] regarding current produced on columns due to voltage applied to rows containing voltage cells with conductance; [0127] regarding column lines 322 provide voltage level for comparison to the reference voltage in an SDU. As interpreted by the Examiner, Fig. 4B shows current produced in the array, Fig. 4 further shows that the current lines turn to current at some point in the circuit (Vref for example), [0127] discusses the columns of the array (as the first columns) providing to the SDU units a voltage level to compare a reference voltage to. As interpreted by the Examiner, not shown in Fig. 4B, there must be current to voltage converters for each row in order to go from a current in each column to a voltage in each SDU);
the plurality of analog signal voltages being generated from the plurality of output currents. (Fig. 4B regarding i1, i2, i3, i4, iref, SDU, SRU, Vref; [0079] regarding current produced on columns due to voltage applied to rows containing voltage cells with conductance; [0127] regarding column lines 322 provide voltage level for comparison to the reference voltage in an SDU. As interpreted by the Examiner, Fig. 4B shows current produced in the array, Fig. 4 further shows that the current lines turn to current at some point in the circuit (Vref for example), [0127] discusses the columns of the array (as the first columns) providing to the SDU units a voltage level to compare a reference voltage to. As interpreted by the Examiner, not shown in Fig. 4B, there must be current to voltage converters for each row in order to go from a current in each column to a voltage in each SDU).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Noack, and in further view of Eyole.
With regards to claim 17, Chou in view of Noack teaches the electronic device according to claim 15, as referenced above.
Chou teaches:
the plurality of analog-to-digital converters (Fig. 4B items 340 (Analog-to-digital converters));
analog signal voltage input to a corresponding one of the plurality of analog-to-digital converters (Fig. 4 regarding analog signal input into SDU and ADCs);
Chou does not explicitly teach:
wherein when a magnitude of an analog signal voltage is greater than a magnitude of the reference voltage,
the plurality of analog-to-digital converters are configured to control the gain such that the magnitude of the analog signal voltage to which the gain is applied is less than or equal to the magnitude of the reference voltage.
However, Chou teaches a plurality of Saturation Detection Units (SDUs), connected to each of the first columns which include a comparator, inputting Vref signals and analog voltages from the first columns to compare (Fig. 4; [0127] regarding SDU units comparing column voltages to reference voltages). Chou further teaches analog-to-digital converters coupled to the SDUs which output digital signals from the input voltages (Fig. 4).
Noack teaches:
analog-to-digital converters are configured to control the gain1 ([0187] regarding an analog to digital converter including a comparator, comparing an output voltage with a reference voltage, and outputting a digital result based on the comparison)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the SDUs and analog - to-digital converters of Chou with the combined analog-to-digital converter and comparator of Noack because this would be considered a simple substitution of one known element for another to obtain predictable results, MPEP 2141 (III)(B).
Eyole teaches:
wherein when a magnitude of the analog signal voltage is greater than a magnitude of the reference voltage, (Fig. 4A; [0058] regarding Vref compared to Vin, with an output Vcomp output based on if Vin is greater than Vref; Eyole figure 4A shows Vcomp equal to Vin if Vin is greater than Vref, and figure 4B shows Vcomp equal to Vin if Vin is less than Vref. As interpreted by the Examiner, Eyole shows limiting a voltage in a comparator to output the output voltage as equal to one of the input voltages based on comparison of the two input voltages. As interpreted by the Examiner, with the limited number of possibilities, it would have been obvious to try limiting the output, Vcomp, to Vref instead of Vin.);
the comparators are configured to control the gain1 such that the magnitude of the analog signal voltage to which the gain1 is applied is less than or equal to the magnitude of the reference voltage. (Fig. 4A; [0058] regarding Vref compared to Vin, with an output Vcomp output based on if Vin is greater than Vref; Eyole figure 4A shows Vcomp equal to Vin if Vin is greater than Vref, and figure 4B shows Vcomp equal to Vin if Vin is less than Vref. As interpreted by the Examiner, Eyole shows limiting a voltage in a comparator to output the output voltage as equal to one of the input voltages based on comparison of the two input voltages. As interpreted by the Examiner, with the limited number of possibilities, it would have been obvious to try limiting the output, Vcomp, to Vref instead of Vin.)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Chou in view of Noack with Eyole. Eyole teaches limiting the voltage in a comparator to Vin if Vin is less than Vref, but choosing from a finite number of identified, predictable solutions, such as changing the comparator to output Vref when Vin is less than Vref, with a reasonable expectation of success, it would be “obvious to try”, MPEP 2141 (III)(B).
Allowable Subject Matter
Claim 3, 4, 6-8, 10-12, 16 and 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 21, 22, 25 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter regarding
claims 3-4. Applicant claims an electronic device of a crossbar array comprising a first set of memory cells on first columns of the array, and a second set of memory cells on a second column of the array for processing data through the array, wherein the electronic device as in claim 1 comprises:
An electronic device, comprising: a crossbar array including: a plurality of first memory cells respectively storing a plurality of conductance values; a plurality of second memory cells each storing a maximum conductance value determined among a subset of the plurality of conductance values, the subset corresponding to the respective second memory cell; a plurality of row lines coupled to the plurality of first memory cells and the plurality of second memory cells and supplying a plurality of input voltages to the plurality of first memory cells and the plurality of second memory cells; a plurality of first column lines coupled to the plurality of first memory cells and configured to respectively output a plurality of output currents generated using the plurality of input voltages and the plurality of conductance values; and a second column line coupled to the plurality of second memory cells and configured to output a maximum output current generated using the plurality of input voltages and the maximum conductance value stored in each of the plurality of second memory cells; and a plurality of analog-to-digital converters respectively coupled to the plurality of first column lines, each of the plurality of analog-to-digital converters receiving a reference voltage and an analog signal voltage corresponding to each of the plurality of output currents and configured to generate a digital signal corresponding to the analog signal voltage based on the reference voltage, the reference voltage being generated from the maximum output current, wherein each of the plurality of analog-to-digital converters determines a maximum value of an input range of the analog signal voltage based on the voltage, such that a maximum magnitude of the analog signal voltage is mapped to the reference voltage.
Furthermore, wherein the electronic device of claim 3 comprises:
wherein each of the plurality of analog-to-digital converters is configured to determine a plurality of comparison voltages based on a plurality of values calculated from the reference voltage according to a resolution set in the plurality of analog-to-digital converters and output the digital signal based on a result of comparing the analog signal voltage with the plurality of comparison voltages.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
The following is a statement of reasons for the indication of allowable subject matter regarding
claims 6-8. Applicant claims an electronic device of a crossbar array comprising a first set of memory cells on first columns of the array, and a second set of memory cells on a second column of the array for processing data through the array, wherein the electronic device as in claim 1 comprises:
An electronic device, comprising: a crossbar array including: a plurality of first memory cells respectively storing a plurality of conductance values; a plurality of second memory cells each storing a maximum conductance value determined among a subset of the plurality of conductance values, the subset corresponding to the respective second memory cell; a plurality of row lines coupled to the plurality of first memory cells and the plurality of second memory cells and supplying a plurality of input voltages to the plurality of first memory cells and the plurality of second memory cells; a plurality of first column lines coupled to the plurality of first memory cells and configured to respectively output a plurality of output currents generated using the plurality of input voltages and the plurality of conductance values; and a second column line coupled to the plurality of second memory cells and configured to output a maximum output current generated using the plurality of input voltages and the maximum conductance value stored in each of the plurality of second memory cells; and a plurality of analog-to-digital converters respectively coupled to the plurality of first column lines, each of the plurality of analog-to-digital converters receiving a reference voltage and an analog signal voltage corresponding to each of the plurality of output currents and configured to generate a digital signal corresponding to the analog signal voltage based on the reference voltage, the reference voltage being generated from the maximum output current, wherein each of the plurality of analog-to-digital converters determines a maximum value of an input range of the analog signal voltage based on the voltage, such that a maximum magnitude of the analog signal voltage is mapped to the reference voltage.
Furthermore, wherein the electronic device of claim 5 comprises:
The electronic device according to claim 1, further comprising: a plurality of first current-to-voltage converters, each configured to receive an output current from a corresponding one of the plurality of first column lines and convert the output current into an analog signal voltage; and a second current-to-voltage converter configured to receive the maximum output current from the second column line and convert the maximum output current into the reference voltage.
Furthermore, wherein the electronic device of claim 6 comprises:
The electronic device according to claim 5, wherein the plurality of analog-to-digital converters comprise: a plurality of voltage buffers respectively coupled to the plurality of first current-to-voltage converters, and configured to receive analog signal voltages from the plurality of first current-to-voltage converters, buffer the analog signal voltages to cancel noise contained in the analog signal voltages, and output buffered analog signal voltages.
The following is a statement of reasons for the indication of allowable subject matter regarding claims 10-12.
Applicant claims an electronic device of a crossbar array comprising a first set of memory cells on first columns of the array, and a second set of memory cells on a second column of the array for processing data through the array, wherein the electronic device as in claim 1 comprises:
An electronic device, comprising: a crossbar array including: a plurality of first memory cells respectively storing a plurality of conductance values; a plurality of second memory cells each storing a maximum conductance value determined among a subset of the plurality of conductance values, the subset corresponding to the respective second memory cell; a plurality of row lines coupled to the plurality of first memory cells and the plurality of second memory cells and supplying a plurality of input voltages to the plurality of first memory cells and the plurality of second memory cells; a plurality of first column lines coupled to the plurality of first memory cells and configured to respectively output a plurality of output currents generated using the plurality of input voltages and the plurality of conductance values; and a second column line coupled to the plurality of second memory cells and configured to output a maximum output current generated using the plurality of input voltages and the maximum conductance value stored in each of the plurality of second memory cells; and a plurality of analog-to-digital converters respectively coupled to the plurality of first column lines, each of the plurality of analog-to-digital converters receiving a reference voltage and an analog signal voltage corresponding to each of the plurality of output currents and configured to generate a digital signal corresponding to the analog signal voltage based on the reference voltage, the reference voltage being generated from the maximum output current, wherein each of the plurality of analog-to-digital converters determines a maximum value of an input range of the analog signal voltage based on the voltage, such that a maximum magnitude of the analog signal voltage is mapped to the reference voltage.
Furthermore, wherein the electronic device of claim 9 comprises:
The electronic device according to claim 1, further comprising: a digital signal processor configured to output a digital operation signal based on a digital signal, output from one of the plurality of analog- to-digital converters, and the reference voltage.
Furthermore, wherein the electronic device of claim 10 comprises:
The electronic device according to claim 9, wherein the digital signal processor is configured to output the digital operation signal as a result of a multiply operation on the digital signal and a digital reference signal corresponding to the reference voltage.
Furthermore, wherein the electronic device of claim 11 comprises:
The electronic device according to claim 9, wherein: the digital signal processor is configured to output a plurality of digital operation signals based on a plurality of digital signals and a plurality of reference voltages, the plurality of digital signals being output from the plurality of analog-to-digital converters to which the plurality of reference voltages are applied, respectively, and each of the plurality of reference voltages is generated based on a multiply-accumulate operation performed on a plurality of input voltages and the maximum conductance value stored in each of the plurality of second memory cells, the plurality of input voltages corresponding to each of a plurality of input data that are input at different time points.
The following is a statement of reasons for the indication of allowable subject matter regarding claims 16. Applicant claims an electronic device of a crossbar array comprising a first set of memory cells on first columns of the array, and a second set of memory cells on a second column of the array for processing data through the array, wherein the electronic device as in claim 15 comprises:
An electronic device, comprising: a crossbar array including: a plurality of first memory cells respectively storing a plurality of conductance values; a plurality of second memory cells each storing a maximum conductance value determined among a subset of the plurality of conductance values, the subset corresponding to the respective second memory cell; a plurality of row lines coupled to the plurality of first memory cells and the plurality of second memory cells and supplying a plurality of input voltages to the plurality of first memory cells and the plurality of second memory cells; a plurality of first column lines coupled to the plurality of first memory cells and configured to respectively output a plurality of output currents generated using the plurality of input voltages and the plurality of conductance values; and a second column line coupled to the plurality of second memory cells and configured to output a maximum output current generated using the plurality of input voltages and the maximum conductance value stored in each of the plurality of second memory cells; and a plurality of analog-to-digital converters respectively coupled to the plurality of first column lines, each of the plurality of analog-to-digital converters receiving a reference voltage and an analog signal voltage corresponding to each of the plurality of output currents and configured to convert the analog signal voltage into a digital signal corresponding to the analog signal voltage by applying a gain corresponding to the reference voltage to the analog signal voltage, the reference voltage being generated from the maximum output current, wherein each of the plurality of analog-to-digital converters determines a maximum value of an input range of the analog signal voltage based on the reference voltage, such that a maximum magnitude of the analog signal voltage is mapped to the reference voltage.
Furthermore, wherein the electronic device of claim 16 comprises:
The electronic device according to claim 15, wherein each of the plurality of analog-to-digital converters is configured to determine a plurality of comparison voltages based on a plurality of values calculated from the reference voltage and according to a resolution set in the plurality of analog-to-digital converters and output the digital signal based on a result of comparing the analog signal voltage to which the gain is applied with the plurality of comparison voltages.
The following is a statement of reasons for the indication of allowable subject matter regarding claims 19. Applicant claims an electronic device of a crossbar array comprising a first set of memory cells on first columns of the array, and a second set of memory cells on a second column of the array for processing data through the array, wherein the electronic device as in claim 15 comprises:
An electronic device, comprising: a crossbar array including: a plurality of first memory cells respectively storing a plurality of conductance values; a plurality of second memory cells each storing a maximum conductance value determined among a subset of the plurality of conductance values, the subset corresponding to the respective second memory cell; a plurality of row lines coupled to the plurality of first memory cells and the plurality of second memory cells and supplying a plurality of input voltages to the plurality of first memory cells and the plurality of second memory cells; a plurality of first column lines coupled to the plurality of first memory cells and configured to respectively output a plurality of output currents generated using the plurality of input voltages and the plurality of conductance values; and a second column line coupled to the plurality of second memory cells and configured to output a maximum output current generated using the plurality of input voltages and the maximum conductance value stored in each of the plurality of second memory cells; and a plurality of analog-to-digital converters respectively coupled to the plurality of first column lines, each of the plurality of analog-to-digital converters receiving a reference voltage and an analog signal voltage corresponding to each of the plurality of output currents and configured to convert the analog signal voltage into a digital signal corresponding to the analog signal voltage by applying a gain corresponding to the reference voltage to the analog signal voltage, the reference voltage being generated from the maximum output current, wherein each of the plurality of analog-to-digital converters determines a maximum value of an input range of the analog signal voltage based on the reference voltage, such that a maximum magnitude of the analog signal voltage is mapped to the reference voltage.
Furthermore, wherein the electronic device of claim 19 comprises:
The electronic device according to claim 15, further comprising: a digital signal processor configured to perform a multiply operation on a digital signal, output from one of the plurality of analog-to-digital converters, and a digital reference signal corresponding to the reference voltage.
The following is a statement of reasons for the indication of allowable subject matter regarding claims 21, and 22. Applicant claims a method of operating an electronic device of a crossbar array comprising a first set of memory cells on first columns of the array, and a second set of memory cells on a second column of the array for processing data through the array, wherein the electronic device as in claim 20 comprises:
A method of operating an electronic device, the electronic device comprising a crossbar array including a plurality of row lines, a plurality of first column lines, a second column line, and a plurality of first memory cells coupled to the plurality of row lines and the plurality of first column lines, and a plurality of second memory cells coupled to the plurality of row lines and the second column line, the method comprising: receiving a plurality of input voltages through the plurality of row generating a maximum output current based on a maximum conductance value, stored in each of the plurality of second memory cells, and the plurality of input voltages, the maximum conductance value corresponding to the largest one of a plurality of conductance values stored in a subset of the plurality of first memory cells, the subset corresponding to the respective second memory cell; converting the maximum output current into a reference voltage; and determining, based on the reference voltage, a maximum value of an input range of an analog signal voltage, which is input to each of a plurality of analog-to- digital converters respectively coupled to the plurality of first column lines, such that a maximum magnitude of the analog signal voltage is mapped to the reference voltage.
Furthermore, the method of operating the electronic device of claim 21 comprises:
The method according to claim 20, wherein the determining comprises buffering the analog signal voltage and providing buffered analog signal voltage to each of the plurality of analog-to-digital converters.
The following is a statement of reasons for the indication of allowable subject matter regarding claim 25. Applicant claims a method of operating an electronic device of a crossbar array comprising a first set of memory cells on first columns of the array, and a second set of memory cells on a second column of the array for processing data through the array, wherein the electronic device as in claim 20 comprises:
A method of operating an electronic device, the electronic device comprising a crossbar array including a plurality of row lines, a plurality of first column lines, a second column line, and a plurality of first memory cells coupled to the plurality of row lines and the plurality of first column lines, and a plurality of second memory cells coupled to the plurality of row lines and the second column line, the method comprising: receiving a plurality of input voltages through the plurality of row generating a maximum output current based on a maximum conductance value, stored in each of the plurality of second memory cells, and the plurality of input voltages, the maximum conductance value corresponding to the largest one of a plurality of conductance values stored in a subset of the plurality of first memory cells, the subset corresponding to the respective second memory cell; converting the maximum output current into a reference voltage; and determining, based on the reference voltage, a maximum value of an input range of an analog signal voltage, which is input to each of a plurality of analog-to- digital converters respectively coupled to the plurality of first column lines, such that a maximum magnitude of the analog signal voltage is mapped to the reference voltage.
Furthermore, the method of operating the electronic device of claim 24 comprises:
The method according to claim 20, further comprising: generating a plurality of output currents based on the plurality of input voltages and the plurality of conductance values; and converting a plurality of analog signal voltages into a plurality of digital signals through the plurality of analog-to-digital converters, the plurality of analog signal voltages being generated from the plurality of output currents.
Furthermore, the method of operating the electronic device of claim 25 comprises:
The method according to claim 24, wherein converting the plurality of analog signal voltages into the plurality of digital signals comprises: determining a plurality of comparison voltages based on a plurality of values calculated from the reference voltage and according to a resolution set in the plurality of analog-to-digital converters; and converting the plurality of analog signal voltages into the plurality of digital signals based on results of comparing each of the plurality of analog signal voltages with the plurality of comparison voltages.
The following is a statement of reasons for the indication of allowable subject matter regarding claim 26. Applicant claims a method of operating an electronic device of a crossbar array comprising a first set of memory cells on first columns of the array, and a second set of memory cells on a second column of the array for processing data through the array, wherein the electronic device as in claim 20
comprises:
A method of operating an electronic device, the electronic device comprising a crossbar array including a plurality of row lines, a plurality of first column lines, a second column line, and a plurality of first memory cells coupled to the plurality of row lines and the plurality of first column lines, and a plurality of second memory cells coupled to the plurality of row lines and the second column line, the method comprising: receiving a plurality of input voltages through the plurality of row generating a maximum output current based on a maximum conductance value, stored in each of the plurality of second memory cells, and the plurality of input voltages, the maximum conductance value corresponding to the largest one of a plurality of conductance values stored in a subset of the plurality of first memory cells, the subset corresponding to the respective second memory cell; converting the maximum output current into a reference voltage; and determining, based on the reference voltage, a maximum value of an input range of an analog signal voltage, which is input to each of a plurality of analog-to- digital converters respectively coupled to the plurality of first column lines, such that a maximum magnitude of the analog signal voltage is mapped to the reference voltage.
Furthermore, the method of operating the electronic device of claim 26 comprises:
The method according to claim 20, further comprising: performing a multiply operation on each of the plurality of digital signals and a digital reference signal corresponding to the reference voltage.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
Chou teaches much of the same structure of the claimed invention, a crossbar array of memory cells with a set of first columns and a second column as a reference column, comparing the voltages of the first columns to the reference voltage of the second column, with the conductance of the cells in the reference column being programmed to a maximum conductance value.
Noack teaches an analog-to-digital converter with an internal comparator, which is described in the claimed invention.
Eyole teaches a method of comparing an input to a reference voltage, and limiting the output based on if Vin is greater than or less than the reference voltage.
Chou, Chou in view of Noack, or Chou in view of Noack and in further view of Eyole discloses the claimed invention in accordance with the above claim mappings. Chou, Chou in view of Noack, or Chou in view of Noack and Eyole is silent with respect to the above highlighted limitations in combination with the remaining limitations including intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.A.K./ Examiner, Art Unit 2182 /EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182
1 Operational amplifier, comparator (tutorial). (2018, March).
https://www.mouser.com/pdfDocs/opamp_comparator_tutorial_appli-e-2.pdf
Regarding Comparators and Gain in sections 1.2 and 1.3