DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 8-13, 15-19, and 22-23 objected to as failing to comply with 37 CFR 1.75(a) because of the following informalities:
In claims 8 and 15, lists multiple items using semi-colons, but does not end the list by separating the last two items with an “and”. i.e. claim 8: “… comprising: …first OR gate;… second OR gate;… third OR gate;… decimal output;… adjacent digit.”
Claims 9-13 and 22 inherit the issue of claim 8.
Claims 16-19 and 23 inherit the issue of claim 15.
Appropriate correction is required
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2, 9, and 16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 8, and 15 recites “wherein, for a given digit of the intermediate value, the value of the carry bit and the value of the inverse carry bit determined for an adjacent digit are provided, within a same clock cycle, to a doubler logic…”. Claims 2, 9, and 16 recites “shifting the bits of the input binary integer and doubling the intermediate value are performed a plurality of times within the same clock cycle”. The specification discloses that the shifting and doubling of an intermediate value (comprising of digits) are performed a plurality of times within a same clock cycle as noted in paragraph 18. Paragraphs 26 and 39 and figure 5, merely discloses generating the carry and inverse carry to be used in a doubler that is for a single digit. The specification does not disclose “providing the carry bit and the inverse carry bit” alongside “shifting the bits of the input binary integer and doubling the intermediate value are performed a plurality of times within the same clock cycle”.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-13 and 22-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites “wherein the semiconductor chip generates the intermediate value… the semiconductor chip shifts bits of the input…the semiconductor chip converts the intermediate value…”. This limitation is unclear because it merely states a function without providing any indication about how the function is performed. The recited function does not follow from the structure recited in the claim, i.e. Doubler logics, carrier logics, or inverse carrier logic. It is also unclear whether the function requires some other structure or is simply a result of operating the semiconductor chip in a certain manner.
Claim 22 recites “wherein the semiconductor chip is configured to determine the value of the inverse carry bit by…”. .It is unclear whether the function requires some other structure or is simply a result of operating the semiconductor chip in a certain manner.
Claims 9-13 and 22 effectively inherits the issues of claim 8, and are also rejected for the reasons given above
Claim 23 recites “wherein the semiconductor chip is configured to…”, However, there is insufficient antecedent basis for this limitation in the claim as the parent claim 15, does not recite a semiconductor chip.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-6, 8-13, 15-19, and 21-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under the Alice Framework Step 1, Claims 1-6 and 21 recite a method and, therefore, is a process. Claims 8-13 and 22 recites a chip and, therefore, is a machine. Claims 15-19 and 23 recites an apparatus and, therefore, is a machine.
Under the Alice Framework Step 2A prong 1, claim 8 recites
A semiconductor chip for reduced logic conversion of binary integers to binary coded decimals, comprising:
one or more doubler logics that double an intermediate value comprising all zero digits encoded in an intermediate format,
wherein the semiconductor chip generates the intermediate value is generated from an input binary integer,
wherein the semiconductor chip shifts bits of the input binary integer into the intermediate value until each bit of the input binary integer has been shifted into the intermediate value, and
wherein each doubler logic comprises a first AND gate, a second AND gate, and a first OR gate, and
wherein outputs of the first AND gate and the second AND gate are provided to the first OR gate;
a carrier logic that determines a value of a carry bit when performing a doubling operation is performed,
wherein the carrier logic comprises a third AND gate and a second OR gate, and
wherein an output of the third AND gate is provided to the second OR gate;
an inverse carrier logic that determines a value of an inverse carry bit when a doubling operation is performed,
wherein the inverse carrier logic comprises a fourth AND gate and a third OR gate,
wherein an output of the fourth AND gate is provided to the third OR gate;
wherein the semiconductor chip converts the intermediate value is converted to a binary coded decimal output;
wherein the intermediate format comprises, for each digit of the intermediate value, a plurality of bits corresponding to a plurality of even weights, a first bit corresponding to a one weight, and a second bit corresponding to an inverse of the one weight,
wherein the intermediate format comprises, for each digit of the intermediate value, seven bits,
wherein, for each digit of the intermediate value the inverse of the one weight is a seventh bit
wherein a bit value for the inverse of the one weight is provided directly to one of the first AND gate or the second AND gate,
wherein, for a given digit of the intermediate value, the value of the carry bit and the value of the inverse carry bit determined for an adjacent digit are provided, within a same clock cycle, to a doubler logic of the one or more doubler logics that doubles the given digit, and
wherein the bit value for the inverse of the one weight that is provided directly to the first AND gate or the second AND gate of the doubler logic that doubles the given digit is the value of the inverse carry bit determined for the adjacent digit.
The above underlined limitations are related to converting an input binary integer into a binary encoded decimal output which amount to doing mathematical calculations and relationships that fall under “Mathematical Concepts” of abstract ideas (see paragraphs 25-29, 35-40). In view of Gottschalk v. Benson, 409 U.S. 63, 70, 175 USPQ 673, 676 (1972), the conversion of binary-coded-decimal (BCD) numerals into pure binary numbers is directed to “Mathematical Concepts” of abstract ideas. As such, the inverse process which is converting binary into binary-coded-decimal (BCD) numerals is directed to “Mathematical Concepts” of abstract ideas. Furthermore, the intermediate format is just a consequence of the math for providing the input into a more complex math formula. Additionally, the gate logic implementation is merely applying a basic digital circuit design methodology of sum-of-products. See Harris et al. “Digital Design and Computer Architecture”, chapter 2, at least sections 2.2.2 Sum-of-Products Form and 2.4 From Logic to Gates. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 8 recites the following additional elements: “one or more doubler logics”, “an carrier logic”, “an inverse carrier logic” and various logic gates for each logic, and “…within a same clock cycle…”. However, the additional elements of “one or more doubler logics”, “ an carrier logic”, “an inverse carrier logic” and various logic gates for each logic are recited at a high-level of generality (i.e., as a generic computer component for computing doubling; as a generic computer component for computing generating carries; and as a generic computer components for logic gates in a sum-of-products format) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The use of “within a same clock cycle” is merely generally linking the use of a judicial exception to a particular technological environment or field of use by respectfully limiting to a clock cycle time frame. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 8 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “one or more doubler logics”, “ an carrier logic”, “an inverse carrier logic” and various logic gates for each logic are recited at a high-level of generality (i.e., as a generic computer component for computing doubling; as a generic computer component for computing generating carries; and as a generic computer components for logic gates in a sum-of-products format) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The use of “within a same clock cycle” is merely generally linking the use of a judicial exception to a particular technological environment or field of use by respectfully limiting to a clock cycle time frame. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, claims 9-13 and 21 recite further steps and details to converting an input binary integer into a binary encoded decimal output and falls within the “mathematical Concepts” and/or “mental Processes” grouping of abstract ideas.
Claim 9 is directed to repeating the mathematical operations multiple times. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 10 is directed to the intermediate format that is required as part of the consequence of the mathematical operation to convert the data. In particular claim 10 does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 11 is directed to the doubler logic and providing a pair of bits. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 11 recites the following additional element of “providing… a pair of bit values of the plurality of bits, a value for the first bit, and a value of the second bit”. However, the additional element of “providing… a pair of bit values of the plurality of bits, a value for the first bit, and a value of the second bit” is merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claim 11 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “providing… a pair of bit values of the plurality of bits, a value for the first bit, and a value of the second bit” is merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 12 is directed to taking as inputs the values needed for the doubling logic. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 12 recites the following additional elements of “accepts, as input, a first bit value from the pair of bit values and the value for the first bit” and “accepts, as input, a second bit value from the pair of bit values and the value for the second bit”. However, the additional element of “accepts, as input, a first bit value from the pair of bit values and the value for the first bit” and “accepts, as input, a second bit value from the pair of bit values and the value for the second bit” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claim 12 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “accepts, as input, a first bit value from the pair of bit values and the value for the first bit” and “accepts, as input, a second bit value from the pair of bit values and the value for the second bit” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 13 is directed to calculating the carry and inverse carry bits. In particular claim 13 does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 21 is directed to the intermediate format that is required as part of the consequence of the mathematical operation to convert the data and the generation of the inverse carry bit. In particular claim 21 does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claims 1-6 and 21 is directed to claims 8-13 and 22, respectively. A mere change in statutory class is obvious. As such, the claims are rejected for the reasons given above.
Claims 15-19 and 23 is directed to claims 8-12 and 22, respectively. A mere change in statutory class is obvious. As such, the claims are rejected for the reasons given above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 8-13, 15-19, 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Carlough et al. (US 2006/0179090 A1, given in the IDS filed 03/25/2022), hereinafter Carlough, and in view of Beck et al. (US 3,993,891 A1), hereinafter Beck, and in further view of Harris et al. (NPL: “Digital Design and Computer Architecture”), hereinafter Harris.
Regarding claim 8, Carlough discloses:
A semiconductor chip for reduced logic conversion of binary integers to binary coded decimals, comprising:
one or more doubler logics that double an intermediate value comprising all zero digits encoded in an intermediate format, wherein the semiconductor chip generates the intermediate value from an input binary integer [Figure 1; "At the start of the conversion process, the decimal accumulated sum latch 104 is reset to zero." Par. 19; "FIG. 6 depicts circuitry for an exemplary 5,1 code doubler" Par. 37],
wherein the semiconductor chip shifts bits of the input binary integer into the intermediate value until each bit of the input binary integer has been shifted into the intermediate value ["The binary operand latch 102 shifts left once for each cycle... it feeds the MSB of the binary operand into the 5,1 code doubler 110... so on until all bits in the binary operand latch 102 have been input to the 5,1 code doubler 110." Par. 18], and
wherein each doubler logic comprises an logical expression of a first AND gate, a second AND gate, and a first OR gate, wherein the AND logical expression results are logically OR-ed together ["A digit expressed in 5,1 code is input (i.e., Y) and the output is the digit doubled (i.e., Z)... The circuitry depicted in FIG. 6 may be expressed by the formulas that follow... Z8=Yodd*Y8+!Yodd*Y4..." Par. 37, the expressions show the use of two logically ANDed inputs: i.e. the value for the first bit (Yodd) and a first bit of a pair, and the value for the inverse of the first bit (!Yodd) and a second bit of a pair. The expressions also include an OR operation that takes the two above logically ANDed inputs and OR them together];
a carrier logic that calculates a value of a carry bit when performing a doubling operation is performed, wherein the carrier logic comprises a third AND gate and a second OR gate, and wherein an output of the third AND gate is provided to the second OR gate [Figure 6, wherein "Zodd = Y8+Y6+Yodd*Y4… Zodd is actually the carry out of this digit" Par. 37, shows an AND and OR gate; Figure 3, shows that Zodd is based on the bottom half of the table for Y inputs];
wherein the semiconductor chip converts the intermediate value to a binary coded decimal output ["FIG. 5 depicts circuitry for an exemplary 5,1 code to BCD recoder… The five bits making up a 5,1 code digit… are input and the output result is … the corresponding BCD digit" Par. 36];
wherein the intermediate format comprises, for each digit of the intermediate value, a plurality of bits corresponding to a plurality of even weights, a first bit corresponding to a one weight ["When the BCD is recoded to five bits with weights of 8, 6, 4, 2, 0, respectively, and one additional bit indicates whether the value is odd or even" Par. 33];
wherein the intermediate format comprises, for each digit of the intermediate value, six bits [“1st digit = 000010 5,1 code 2nd digit = 000010 5,1 code” par.34, example given on page 3].
Wherein, for each digit of the intermediate value, the one weight is a sixth bit [Fig.3, 5,1 code; “When BCD is recoded to five bits… and one additional bit indicates whether the value is odd or even” par.33]
Wherein a bit value for the inverse of the one weight is provided directly to one of the logical expressions of the first AND gate or the second AND gate [“the circuitry depicted in FIG. 6 may be expressed by the formulas that follow... Z8=Yodd*Y8+!Yodd*Y4..." Par. 37 shows inverse of the Yodd bit provided directly to one of the AND logical operations],
wherein, for a given digit of the intermediate value, the value of the carry bit determined for an adjacent digit are provided to a doubler logic that doubles the given digit [Fig.2, 110 code doubler; "Zodd = Y8+Y6+Yodd*Y4… Zodd is actually the carry out of this digit" Par. 37; See par.34, 1st 5,1 Code Doubler to 4th 5,1 Code Doubler], and
wherein the bit value for the inverse of the one weight that is provided directly to the first AND gate or the second AND gate for the given digit is the value of the inverse carry bit determined for the adjacent digit [“the circuitry depicted in FIG. 6 may be expressed by the formulas that follow... Z8=Yodd*Y8+!Yodd*Y4..." Par. 37 shows inverse of the Yodd bit provided directly to one of the AND logical operations; “Note that Zodd is actually the carry out of this digit and it is transmitted to the next more significant digit” par.37 shows that Zodd is Yodd in the next/adjacent/intermediate digits],.
However, Carlough does not explicitly disclose:
wherein each doubler logic comprises a first AND gate, a second AND gate, and a first OR gate, wherein outputs of the first AND gate and the second AND gate are provided to the first OR gate;
an inverse carrier logic that calculates a value of an inverse carry bit when a doubling operation is performed, wherein the inverse carrier logic comprises a fourth AND gate and a third OR gate, wherein an output of the fourth AND gate is provided to the third OR gate;
and a second bit corresponding to an inverse of the one weight, and wherein a bit value for the inverse of the one weight is provided directly to one of the first AND gate or the second AND gate.
wherein the intermediate format comprises, for each digit of the intermediate value, seven bits.
wherein, for each digit of the intermediate value, the inverse of the one weight is a seventh bit.
wherein, for a given digit of the intermediate value, the value of the carry bit and the value of the inverse carry bit determined for an adjacent digit are provided, within a same clock cycle, to a doubler logic that doubles the given digit,
In the analogous art of Parallel digital data processing implementations, Beck teaches providing the inverse carry signal alongside the normal carry signal for acceleration ["the carry-not lookahead signals !C0, !C1… are available simultaneously with the carry look-ahead signals C0,C1…” Col.5 Lines 27-30, teaches providing both normal and inverted signals at the same time]
Beck also discloses having two logics for generating carry signals and inverse carry signals [Fig.3]
Carlough further discloses that the intermediate format is used in the logical operations shown on paragraph 37, wherein there is a necessity of both Yodd and the inversion of Yodd for each doubling stage and that the next stage uses both the carry Zodd and the inverse carry !Zodd for the next stage as a result ["Note that Zodd is actually the carry out of this digit and it is transmitted to the next more significant digit" Par. 37, wherein Zodd is the next stage Yodd for the Doubler as shown in the example given in page 3].
It would have been obvious to one of ordinary skill in the art, given Beck's benefit to generating both carry and inverse carry, to implement an inverse carry circuitry that results on the inverse of Carlough carry circuit. Additionally, it would have been obvious to one of ordinary skill in the art to look within Carlough to find the inverse cases of Zodd, wherein Zodd = Y8 +Y6 + Yodd*Y4, looking at figure 3, Zodd is true for the bottom half of the table and false (inverse of true) for the top half of the table, wherein Y2, Y0, and Y4*!Yodd is true.
Additionally, It would have been obvious to one of ordinary skill in the art, seeing the similarities between the carry logic "Zodd=Y8+Y6+Yodd*Y4" and Y2, Y0, and Y4*!Yodd for !Zodd to follow the same circuitry as shown on figure 6 of Carlough.
As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Carlough and Beck before him before the effective filing date of the claimed invention to implement an inverse carry circuit based on figure 6's carry circuit and figure 3's table from Carlough, to include the technique of providing both the carry signal and the inverse carry signal at the same time from Beck, to allow for reducing the time delay from directly inverting a signal that is required for the logic [Beck: Col.5 Lines 30-33]. The combination of Carlough and Beck discloses the limitation of an inverse carrier logic that calculates a value of an inverse carry bit when a doubling operation is performed, wherein the inverse carrier logic comprises a fourth AND gate and a third OR gate, wherein an output of the fourth AND gate is provided to the third OR gate;
Additionally, It would have further been obvious to one of ordinary skill in the art to implement the inverse carry circuitry of the combination of Carlough and Beck, using the sum-of-products PLA implementation taught by Harris, to follow Carlough’s sum-of-products design of the carry circuit to design a sum-of-products design of the inverse carry circuit, allowing for inexpensive simplified design for a two-level combinational logic in a sum-of-product form and shortest equations based on truth tables [Harris: p.54-56, 62-65, and 266-267].
Furthermore, Carlough further discloses that the intermediate format is used in the logical operations shown on paragraph 37, wherein there is a necessity of both Yodd and the inversion of Yodd for each doubling stage, i.e. "...Z8=Yodd*Y8+!Yodd*Y4...". It would have been obvious to one of ordinary skill in the art, seeing that the carry bit (one weight) is appended as the sixth bit [Fig.3] to also append the inverse of the one weight to the 5,1 code as the seventh bit, as there is a necessity of both Yodd and the inversion of Yodd for each doubling stage and that the next stage uses both the carry Zodd and the inverse carry !Zodd ["Note that Zodd is actually the carry out of this digit and it is transmitted to the next more significant digit" Par. 37, wherein Zodd is the next stage Yodd for the Doubler as shown in the example given in page 3]. Seeing that Beck teaches a technique of “the carry-not lookahead signals… are available simultaneously with the carry look-ahead signals… rather than suffering the time delay which would be necessary if the carry-not look-ahead signals were to be derived by inverting the carry look-ahead signals”.
It would have been obvious to one of ordinary skill in the art, that the technique from Beck is generalizable to all signals and not only the carry signals. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Carlough and Beck before him before the effective filing date of the claimed invention to modify the intermediate format’s Yodd signal disclosed by Carlough to include the technique of providing both the signal (the Yodd signal) and the inverse signal (the !Yodd signal) at the same time from Beck, to allow for reducing the time delay from directly inverting a signal that is required for the logic [Beck: Col.5 Lines 30-33]. The combination of Carlough and Beck discloses and a second bit corresponding to an inverse of the one weight, and wherein a bit value for the inverse of the one weight is provided directly to one of the logical expression first AND gate or the second AND gate. wherein the intermediate format comprises, for each digit of the intermediate value, seven bits. wherein, for each digit of the intermediate value, the inverse of the one weight is a seventh bit. wherein, for a given digit of the intermediate value, the value of the carry bit and the value of the inverse carry bit determined for an adjacent digit are provided, within a same clock cycle, to a doubler logic that doubles the given digit.
However, Carlough and Beck does not explicitly disclose:
wherein each doubler logic comprises a first AND gate, a second AND gate, and a first OR gate, wherein outputs of the first AND gate and the second AND gate are provided to the first OR gate; wherein a bit value for the inverse of the one weight is provided directly to one of the first AND gate or the second AND gate.
In the analogous art of Logic Circuit Design and Architecture, Harris teaches sum of product design PLA architecture implementation and logic expression to gates [“This is called the sum-of-products canonical form of a function because it is the sum (OR) of products (ANDs forming minterms)“ p.54-55, sec.2.2.2; “Programmable logic arrays (PLAs) implement two-level combinational logic in sum-of-products (SOP) form” p.266, sec. 5.6.1; “Any Boolean equation in sum-of-products form can be drawn as a schematic in a systematic way similar to Figure 2.23” p.63, sec.2.4]
It would have been obvious to one of ordinary skill in the art, having the teachings of Carlough, Beck, and Harris before him before the effective filing date of the claimed invention to incorporate the sum-of-products PLA implementation as taught by Harris into the logic components of the logical expressions as disclosed by the combination of Carlough and Beck to allow for inexpensive simplified design for a two-level combinational logic in a sum-of-product form and shortest equations based on truth tables [Harris: p.54-56, 62-65, and 266-267]. The combination of Carlough, Beck, and Harris discloses the implementation of doubler logic gates and sum-of-product implementations, as such Carlough, Beck, and Harris discloses wherein each doubler logic comprises a first AND gate, a second AND gate, and a first OR gate, wherein outputs of the first AND gate and the second AND gate are provided to the first OR gate; wherein a bit value for the inverse of the one weight is provided directly to one of the first AND gate or the second AND gate.
Regarding claim 9, Carlough, Beck, and Harris disclose the invention substantially as claimed. See the discussion of claim 8 above.
Carlough further discloses: wherein shifting the bit of the input binary integer and doubling the intermediate value are performed a plurality of times within the same clock cycle ["The binary operand latch 102 shifts left once for each cycle... it feeds the MSB of the binary operand into the 5,1 code doubler 110... so on until all bits in the binary operand latch 102 have been input to the 5,1 code doubler 110." Par. 18; Page 3 shows a 4-parallel bit variant executed per cycle (loop), where they show the double and shifting of bit in the cycle].
Regarding claim 10, Carlough, Beck, and Harris disclose the invention substantially as claimed. See the discussion of claim 8 above.
Carlough further discloses: wherein the plurality of even weights comprises an eight weight, a six weight, a four weight, a two weight, and a zero weight ["When the BCD is recoded to five bits with weights of 8, 6, 4, 2, 0, respectively" Par. 33].
Regarding claim 11, Carlough, Beck, and Harris disclose the invention substantially as claimed. See the discussion of claim 8 above.
Carlough further discloses: wherein each bit of the plurality of bits corresponds to a doubler logic of a plurality of doubler logics, and wherein doubling the intermediate value comprises providing, to each doubler logic of the plurality of doubler logics, a pair of bit values of the plurality of bits, a value for the first bit, and a value of the inverse of the first bit ["A digit expressed in 5,1 code is input (i.e., Y) and the output is the digit doubled (i.e., Z) and expressed in 5,1 code. The circuitry depicted in FIG. 6 may be expressed by the formulas that follow" Par. 37, wherein they show the logic that requires a pair of bit values and a value for the first bit and the inverse of the first bit, i.e. Yodd and NOT Yodd respectively].
However, Carlough does not explicitly disclose providing a value of the second bit.
In the analogous art of Parallel digital data processing implementations, Beck teaches a technique of “the carry-not lookahead signals… are available simultaneously with the carry look-ahead signals… rather than suffering the time delay which would be necessary if the carry-not look-ahead signals were to be derived by inverting the carry look-ahead signals” as noted in claim 8.
It would have been obvious to one of ordinary skill in the art, that the technique from Beck is generalizable to all signals and not only the carry signals. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Carlough and Beck before him before the effective filing date of the claimed invention to modify the provision of the Yodd signal disclosed by Carlough to include the technique of providing both the signal and the inverse signal at the same time from Beck, to allow for reducing the time delay from directly inverting a signal that is required for the logic [Beck: Col.5 Lines 30-33]. The combination of Carlough and Beck teaches the limitation of “wherein each bit of the plurality of bits corresponds to a doubler logic of a plurality of doubler logics, and wherein doubling the intermediate value comprises providing, to each doubler logic of the plurality of doubler logics, a pair of bit values of the plurality of bits, a value for the first bit, and a value of the second bit.”
Regarding claim 12, Carlough, Beck, and Harris disclose the invention substantially as claimed. See the discussion of claim 11 above.
Carlough further discloses: wherein each doubler logic comprises: A logical expression of a first AND accepting, as input, a first bit value from the pair of bit values and the value for the first bit; A logical expression of a second AND accepting, as input, a second bit value from the pair of bit values and the value for the inverse of the first bit; and A logical expression of an OR accepting, as input, an output from the first AND gate and an output from the second AND gate ["Z8=Yodd*Y8+!Yodd*Y4..." Par. 37, the expressions show the use of two logically ANDed inputs: i.e. the value for the first bit (Yodd) and a first bit of a pair, and the value for the inverse of the first bit (!Yodd) and a second bit of a pair. The expressions also include an OR operation that takes the two above logically ANDed inputs and OR them together]
However, Carlough does not explicitly disclose first AND gate, a second AND gate, and an OR gate, and wherein a second AND gate accepting, as input, a second bit value from the pair of bit values and the value for the second bit.
In the analogous art of Parallel digital data processing implementations, Beck teaches a technique of “the carry-not lookahead signals… are available simultaneously with the carry look-ahead signals… rather than suffering the time delay which would be necessary if the carry-not look-ahead signals were to be derived by inverting the carry look-ahead signals” as noted in claim 8.
It would have been obvious to one of ordinary skill in the art, that the technique from Beck is generalizable to all signals and not only the carry signals. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Carlough and Beck before him before the effective filing date of the claimed invention to implement the technique of providing both the signal and the inverse signal at the same time from Beck, to supply the logical second AND input for the inverse of the first bit disclosed by Carlough, in order to have a second bit value of the inverse of the first bit, to allow for reducing the time delay from directly inverting a signal that is required for the logic [Beck: Col.5 Lines 30-33]. The combination of Carlough and Beck teaches the limitation of “a second AND accepting, as input, a second bit value from the pair of bit values and the value for the second bit.”
In the analogous art of Logic Circuit Design and Architecture, Harris teaches sum of product design PLA architecture implementation and logic expression to gates [“This is called the sum-of-products canonical form of a function because it is the sum (OR) of products (ANDs forming minterms)“ p.54-55, sec.2.2.2; “Programmable logic arrays (PLAs) implement two-level combinational logic in sum-of-products (SOP) form” p.266, sec. 5.6.1; “Any Boolean equation in sum-of-products form can be drawn as a
schematic in a systematic way similar to Figure 2.23” p.63, sec.2.4]
It would have been obvious to one of ordinary skill in the art, having the teachings of Carlough, Beck, and Harris before him before the effective filing date of the claimed invention to incorporate the sum-of-products PLA implementation as taught by Harris into the logic components of the logical expressions as disclosed by the combination of Carlough and Beck to allow for inexpensive simplified design for a two-level combinational logic in a sum-of-product form and shortest equations based on truth tables [Harris: p.54-56, 62-65, and 266-267]. The combination of Carlough, Beck, and Harris discloses the additional limitations of claim 12.
Regarding claim 13, Carlough, Beck, and Harris disclose the invention substantially as claimed. See the discussion of claim 8 above.
Carlough further discloses: wherein doubling the intermediate value further comprises calculating, for each digit of the intermediate value, the carry bit ["Note that Zodd is actually the carry out of this digit and it is transmitted to the next more significant digit" Par. 37, wherein Zodd is the next stage Yodd for the Doubler as shown in the example given in page 3].
However, Carlough does not explicitly disclose wherein doubling the intermediate value further comprises calculating, for each digit of the intermediate value, the carry bit and the inverse carry bit.
In the analogous art of Parallel digital data processing implementations, Beck teaches providing both the carry signal and the inverse carry signal ["the carry-not lookahead signals !C0, !C1… are available simultaneously with the carry look-ahead signals C0,C1…" Col.5 Lines 27-30]
It would have been obvious to one of ordinary skill in the art, having the teachings of Carlough and Beck before him before the effective filing date of the claimed invention to modify carry signal disclosed by Carlough to use the technique of providing both the carry signal and the inverse carry signal at the same time from Beck, to allow for reducing the time delay from directly inverting a signal that is required for the logic [Beck: Col.5 Lines 30-33]. The combination of Carlough and Beck teaches the limitation of “wherein doubling the intermediate value further comprises calculating, for each digit of the intermediate value, the carry bit and the inverse carry bit.”
Regarding claim 22, Carlough, Beck, and Harris disclose the invention substantially as claimed. See the discussion of claim 8 above.
Carlough discloses:
wherein the plurality of even weights comprises an eight weight, a six weight, a four weight, a two weight, and a zero weight ["When the BCD is recoded to five bits with weights of 8, 6, 4, 2, 0, respectively" Par. 33].
Determine the value of the carry bit by providing a bit value for the sixth weight and a bit value for the eight weight to the second OR gate, and by providing a bit value for the four weight and the bit value of the one weight to the third AND gate, the output of the third AND gate being provided to the second OR gate [See figures 6 and 3; “Zodd=Y8+Y6+Yodd*Y4… Zodd is actually the carry out of this digit” par.37].
However, Carlough does not explicitly disclose:
Wherein the semiconductor chip is configured to determine the value of the inverse carry bit by providing a bit value for the zero weight and a bit value for the two weight to the third OR gate, and by providing a bit value for the four weight and the bit value for the inverse of the one weight to the forth AND gate, the output of the fourth AND gate being provided to the third OR gate.
In the analogous art of Parallel digital data processing implementations, Beck teaches providing the inverse carry signal alongside the normal carry signal for acceleration ["the carry-not lookahead signals !C0, !C1… are available simultaneously with the carry look-ahead signals C0,C1…” Col.5 Lines 27-30, teaches providing both normal and inverted signals at the same time]
Beck also discloses having two logics for generating carry signals and inverse carry signals [Fig.3]
Carlough further discloses that the intermediate format is used in the logical operations shown on paragraph 37, wherein there is a necessity of both Yodd and the inversion of Yodd for each doubling stage and that the next stage uses both the carry Zodd and the inverse carry !Zodd for the next stage as a result ["Note that Zodd is actually the carry out of this digit and it is transmitted to the next more significant digit" Par. 37, wherein Zodd is the next stage Yodd for the Doubler as shown in the example given in page 3].
It would have been obvious to one of ordinary skill in the art, given Beck's benefit to generating both carry and inverse carry, to implement an inverse carry circuitry that results on the inverse of Carlough carry circuit. Additionally, it would have been obvious to one of ordinary skill in the art to look within Carlough to find the inverse cases of Zodd, wherein Zodd = Y8 +Y6 + Yodd*Y4, looking at figure 3, Zodd is true for the bottom half of the table and false (inverse of true) for the top half of the table, wherein Y2, Y0, and Y4*!Yodd is true.
Additionally, It would have been obvious to one of ordinary skill in the art, seeing the similarities between the carry logic "Zodd=Y8+Y6+Yodd*Y4" and Y2, Y0, and Y4*!Yodd for !Zodd to follow the same circuitry as shown on figure 6 of Carlough.
As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Carlough and Beck before him before the effective filing date of the claimed invention to implement an inverse carry circuit based on figure 6's carry circuit and figure 3's table from Carlough, to include the technique of providing both the carry signal and the inverse carry signal at the same time from Beck, to allow for reducing the time delay from directly inverting a signal that is required for the logic [Beck: Col.5 Lines 30-33]. The combination of Carlough and Beck discloses Wherein the semiconductor chip is configured to determine the value of the inverse carry bit by providing a bit value for the zero weight and a bit value for the two weight to the third OR gate, and by providing a bit value for the four weight and the bit value for the inverse of the one weight to the forth AND gate, the output of the fourth AND gate being provided to the third OR gate.
Additionally, It would have further been obvious to one of ordinary skill in the art to implement the inverse carry circuitry of the combination of Carlough and Beck, using the sum-of-products PLA implementation taught by Harris, to follow Carlough’s sum-of-products design of the carry circuit to design a sum-of-products design of the inverse carry circuit, allowing for inexpensive simplified design for a two-level combinational logic in a sum-of-product form and shortest equations based on truth tables [Harris: p.54-56, 62-65, and 266-267].
Claims 1-6 and 21 are directed to claims 8-13 and 22, respectively. A mere change in statutory class is obvious. As such, the claims are rejected for the reasons given above.
Claims 15-19 and 23 are directed to claims 8-12 and 23, respectively. A mere change in statutory class is obvious. As such, the claims are rejected for the reasons given above.
Response to Amendment
The amendment to the claims does not comply with 37 CFR 1.121(c)(2). Claims 2, 9, and 16 changed the limitation of “a same clock cycle” to “the same clock cycle” without showing the required underlining for added matter and strike-through or double brackets for deleted matter. Additionally, claims 2 and 16 have the incorrect status identifiers of “(Original)” and should be “(Currently Amended)” because of the previous issue. This issue is waved, see attached “Corrected Claims Listing (For Non-Compliant Amendment Filed 06/17/2026)”, but applicant is warned that should another non-compliant response be filed, it may result in a notice of non-compliance.
Response to Arguments
Applicant’s arguments, see page 12, filed 06/17/2026, with respect to Objections to the Claims have been fully considered and are persuasive. The Objections to the Claims of the Office Action mailed 03/17/2026 (hereinafter Prior Office Action) has been withdrawn.
Applicant's arguments, see pages 12-20, filed 06/17/2026, with respect to Rejections under 35 U.S.C. 101 have been fully considered but they are not persuasive.
On p.13, applicant argues that claim 8 does not recite a general mathematical formula for conversion, however this is inconsistent with the rejection made, as the rejection was made based on mathematical calculations and relationships. See Prior Office Action page 4 and MPEP 2106.04(a)(2)(I).
On p.13, applicant argues that claim 8 does not recite a mathematical concept such as mathematical formula, equation, or calculation, but instead recites physical logic elements and states that the operations performed by these logic elements may be described in mathematical terms does not mean the claim recites a mathematical concept. However, MPEP 2106.04(a)(2)(I) (A) and (C) states the following: “A mathematical relationship may be expressed in words” and “A mathematical calculation is a mathematical operation (such as multiplication) or an act of calculating using mathematical methods to determine a variable or number… a claim does not have to recite the word "calculating" in order to be considered a mathematical calculation. For example, a step of "determining" a variable or number using mathematical methods or "performing" a mathematical operation may also be considered mathematical calculations when the broadest reasonable interpretation of the claim in light of the specification encompasses a mathematical calculation”. In view of claim 8, the claim recites various operations such as but not limited to “double an intermediate value…“, “determines a value of a carry bit when performing a doubling operation is performed…”, and “determines a value of an inverse carry bit…” . See rejection under 35 USC 101.
On pp.13-14, applicant argues that claim 8 is directed to a specific semiconductor chip and not carried out on a general-purpose computer. However, this is inconsistent with the application’s specification wherein the specification states: “the flow of Fig.1 may be implemented, for example, in a chip or other semiconductor devices. Such a chip or semiconductor device may be included in a device or apparatus such as a server, personal computer, mobile device, set-top box, and the like” on paragraph 16 and “method of FIG.8 may be performed, for example, in a chip 800 or another semiconductor device as can be appreciated. The method of FIG. 8 may also be performed in a device or apparatus such as a computing device including a chip 800 or semiconductor device as described herein” on paragraph 34. Additionally, the claim is open-ended, wherein a microprocessor that includes this circuitry to do the conversion would be the semi-conductor chip that carries out the conversion as a general-purpose computer. This is like Gottschalk v. Benson, 409 U.S. 63 (1972), wherein the case was using a general-purpose computer for the conversion.
On pages 15-16, applicant argues claim 8 is a particular machine and is a specific improvement to computer technology. However, the additional elements of claim 8 are merely a consequence of implementing the math to perform the conversion. The doubler performs doubling, and the carrier logics determines carry values, wherein the operations comprises of performing logical operations such as AND and OR to perform the doubling and determine the carry values. The doubling operation requires the carry and its inverse to perform the mathematical operation. Furthermore, applicant argues the improvement to computer technology comes from not having an inverter, however merely performing less steps to perform the doubling still falls under the abstract ideas. See MPEP 2106.05(a) “the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements.”
On pages 16-17, applicant argues the independent claims now recite a same clock cycle feature that reflects an improvement. However, this is merely an arbitrary unit of time that is performed in a period and is rejected above as generally linking the math to a clock cycle time frame. See rejection under 35 USC 101 above.
On page 17, applicant argues the improvement recited in claim 8 is not the result of the conversion itself, but the specific arrangement of logic elements that performs the conversion using fewer logic gates and within fewer clock cycles. However, as discussed above under paragraph D, merely performing less steps to perform the doubling still falls under the abstract ideas and is an improvement from the abstract idea.
On page 18, applicant also argues the mere instructions using a generic computer component. However, claim 8 does recite generic computer components where the improvement comes from the abstract idea, see arguments above under paragraphs C and D.
On pages 19-20, applicant argues for claim 8 that the arrangement of doubler logic, carrier logic, and inverse carrier logic is not conventional. However, the argument is not directed to the rejection that was made, wherein it relied upon MPEP 2106.05(f). See rejection under 35 USC 101.
The examiner respectfully disagrees with the applicant’s assertion to the contrary for at least the reasons given above for 35 U.S.C. 101.
Applicant's arguments, see pages 20-26, filed 06/17/2026, with respect to Rejections under 35 U.S.C. 103 have been fully considered but they are not persuasive.
On page 22-23, applicant argues that the Office Action has not articulated a rationale with the rational underpinning required for the combination, with respect to the technique of Beck of generating the carry and inverse carry is generalizable to all signals. Beck discloses “so that the carry-not look-ahead signals… are available simultaneously with the carry look-ahead signals…, rather than suffering the time delay which would be necessary if the carry-not look-ahead signals were to be derived by inverting the carry look-ahead signals” on col.5, ll.27-32, which discloses the benefit of reduced time delay if instead of inverting the signals after, provide both the signals and the inverse signals simultaneously. A person of ordinary skill in the art would recognize that if you are going to need the inverted signal later you would provide both the signals and the inverse signals simultaneously, a person of ordinary skill in the art would recognize the provision of the carry and inverse carry applies to signals and inverted signals. Carlough provides the one additional bit signal (Yodd in figure 3-6) that requires the inversion of the bit signal as shown on paragraph 37 of Carlough. As such a person of ordinary skill in the art would recognize the bit signal and apply the design principle disclosed in beck and generalize it to apply to the bit signal. Furthermore, the applicant’s argument ignores the technical field of processor design, the level of skill in the art is very high, and a person of ordinary skill in the art would understand the design principle disclosed in beck and would apply it to other signals.
In response to applicant's argument, on page 23, that the combination is a substantial redesign rather than a use of a known technique in a known way, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
In response to applicant's argument, on page 23, that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
In response to applicant's argument, on pages 23-24, that the combination does not disclose the limitation as recited in claim 5 and 12, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The applicant only argues Harris but does not address the combination of Carlough, Beck, and Harris. See above for claim 5 and 12
In response to applicant's arguments on pages 23-24, that the combination does not disclose the limitation of “wherein each bit of the plurality of bits corresponds to a doubler logic of a plurality of doubler logics, and wherein doubling the intermediate value comprises providing, to each doubler logic of the plurality of doubler logics, a pair of bit values of the plurality of bits, a value for the first bit, and a value of the second bit, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The applicant only argues Carlough but does not address the combination of Carlough and Beck. See above for claim 11 and 18.
In response to applicant's argument, on pages 25-26, that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). Furthermore, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Additionally, see arguments above with respect to Beck.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenny K. Bui whose telephone number is (571)270-0604. The examiner can normally be reached 8:00 am to 3:00 pm on Monday, 8:00 am to 4:00 pm on Tuesday to Friday ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571)272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNY K. BUI/Patent Examiner, Art Unit 2182 (571)270-0604
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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