DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/09/2026 has been entered.
Examiner Notes the following: claims 1, 8, and 15 have been amended. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 15 objected to because of 37 CFR 1.75(a) for the following informalities: Claim 15, line 1, “to to” should read as “to”. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under the Alice Framework Step 1, Claims 1-7 recite a method and, therefore, is a process. Claims 8-14 recites a chip and, therefore, is a machine. Claims 15-20 recites an apparatus and, therefore, is a machine.
Under the Alice Framework Step 2A prong 1, claim 8 recites
A chip for reduced logic conversion of binary integers to binary coded decimals, comprising:
one or more doubler logics that double an intermediate value comprising all zero digits encoded in an intermediate format,
wherein the intermediate value is generated from an input binary integer,
wherein, until each bit of the input binary integer has been shifted into the intermediate value, a bit of the input binary integer is shifted into the intermediate value, and
wherein each doubler logic comprises a first AND gate, a second AND gate, and a first OR gate, and
wherein outputs of the first AND gate and the second AND gate are provided to the first OR gate;
a carrier logic that determines a value of a carry bit when performing a doubling operation is performed,
wherein the carrier logic comprises a third AND gate and a second OR gate, and
wherein an output of the third AND gate is provided to the second OR gate;
an inverse carrier logic that determines a value of an inverse carry bit when a doubling operation is performed,
wherein the inverse carrier logic comprises a fourth AND gate and a third OR gate,
wherein an output of the fourth AND gate is provided to the third OR gate;
wherein the intermediate value is converted to a binary encoded decimal output; and
wherein the intermediate format comprises, for each digit of the intermediate value, a plurality of bits corresponding to a plurality of even weights, a first bit corresponding to a one weight, and a second bit corresponding to an inverse of the one weight,
wherein the intermediate format comprises, for each digit of the intermediate value, seven bits,
wherein, for each digit of the intermediate value the inverse of the one weight is a least significant bit and
wherein a bit value for the inverse of the one weight is provided directly to one of the first AND gate or the second AND gate.
The above underlined limitations are related to converting an input binary integer into a binary encoded decimal output which amount to doing mathematical calculations and relationships that fall under “Mathematical Concepts” of abstract ideas (see paragraphs 25-29, 35-40). In view of Gottschalk v. Benson, 409 U.S. 63, 70, 175 USPQ 673, 676 (1972), the conversion of binary-coded-decimal (BCD) numerals into pure binary numbers is directed to “Mathematical Concepts” of abstract ideas. As such, the inverse process which is converting binary into binary-coded-decimal (BCD) numerals is directed to “Mathematical Concepts” of abstract ideas. Furthermore, the intermediate format is just a consequence of the math for providing the input into a more complex math formula. Additionally, the gate logic implementation is merely applying a basic digital circuit design methodology of sum-of-products. See Harris et al. “Digital Design and Computer Architecture”, chapter 2, at least sections 2.2.2 Sum-of-Products Form and 2.4 From Logic to Gates. Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 8 recites the following additional elements: “one or more doubler logics”, “ an carrier logic”, “an inverse carrier logic” and various logic gates for each logic. However, the additional elements of “one or more doubler logics”, “ an carrier logic”, “an inverse carrier logic” and various logic gates for each logic are recited at a high-level of generality (i.e., as a generic computer component for computing doubling; as a generic computer component for computing generating carries; and as a generic computer components for logic gates in a sum-of-products format) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 8 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “one or more doubler logics”, “ an carrier logic”, “an inverse carrier logic” and various logic gates for each logic are recited at a high-level of generality (i.e., as a generic computer component for computing doubling; as a generic computer component for computing generating carries; and as a generic computer components for logic gates in a sum-of-products format) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, claims 9-14 recite further steps and details to converting an input binary integer into a binary encoded decimal output and falls within the “mathematical Concepts” and/or “mental Processes” grouping of abstract ideas.
For claim 9, is directed to repeating the mathematical operations multiple times. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 9 recites the following additional element of “within a same clock cycle”. However, the additional element of “within a same clock cycle” is recited at a high-level of generality (i.e., as a generic computer component for processing the data within a cycle) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claim 9 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “within a same clock cycle” is recited at a high-level of generality (i.e., as a generic computer component for processing the data within a cycle) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
For claim 10, is directed to the intermediate format that is required as part of the consequence of the mathematical operation to convert the data. In particular claim 10 does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
For claim 11, is directed to the doubler logic and providing a pair of bits. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 11 recites the following additional element of “providing… a pair of bit values of the plurality of bits, a value for the first bit, and a value of the second bit”. However, the additional element of “providing… a pair of bit values of the plurality of bits, a value for the first bit, and a value of the second bit” is merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claim 11 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “providing… a pair of bit values of the plurality of bits, a value for the first bit, and a value of the second bit” is merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
For claim 12, is directed to taking as inputs the values needed for the doubling logic. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 12 recites the following additional elements of “accepts, as input, a first bit value from the pair of bit values and the value for the first bit” and “accepts, as input, a second bit value from the pair of bit values and the value for the second bit”. However, the additional element of “accepts, as input, a first bit value from the pair of bit values and the value for the first bit” and “accepts, as input, a second bit value from the pair of bit values and the value for the second bit” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claim 12 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “accepts, as input, a first bit value from the pair of bit values and the value for the first bit” and “accepts, as input, a second bit value from the pair of bit values and the value for the second bit” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
For claim 13, is directed to calculating the carry and inverse carry bits. In particular claim 13 does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
For claim 14, is directed to a mathematical relationship between the adjacent digit and the carry bits. In particular claim 14 does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claims 1-7 is directed to claims 8-14, respectively. A mere change in statutory class is obvious. As such, claims 1-7 is rejected for the reasons given for claims 8-14.
Claims 15-20 is directed to claims 8-13, respectively. A mere change in statutory class is obvious. As such, claims 15-20 is rejected for the reasons given for claims 8-13.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Carlough et al. (US 2006/0179090 A1, given in the IDS filed 03/25/2022), hereinafter Carlough, and in view of Beck et al. (US 3,993,891 A1), hereinafter Beck, and in further view of Harris et al. (NPL: “Digital Design and Computer Architecture”), hereinafter Harris.
Regarding claim 8, Carlough discloses:
a chip for reduced logic conversion of binary integers to binary coded decimals, comprising:
one or more doubler logics that double an intermediate value comprising all zero digits encoded in an intermediate format, wherein the intermediate value is generated from an input binary integer [Figure 1; "At the start of the conversion process, the decimal accumulated sum latch 104 is reset to zero." Par. 19; "FIG. 6 depicts circuitry for an exemplary 5,1 code doubler" Par. 37],
wherein, until each bit of the input binary integer has been shifted into the intermediate value, shifting a bit of the input binary integer is shifted into the intermediate value ["The binary operand latch 102 shifts left once for each cycle... it feeds the MSB of the binary operand into the 5,1 code doubler 110... so on until all bits in the binary operand latch 102 have been input to the 5,1 code doubler 110." Par. 18], and
wherein each doubler logic comprises an logical expression of a first AND gate, a second AND gate, and a first OR gate ["A digit expressed in 5,1 code is input (i.e., Y) and the output is the digit doubled (i.e., Z)... The circuitry depicted in FIG. 6 may be expressed by the formulas that follow... Z8=Yodd*Y8+!Yodd*Y4..." Par. 37, the expressions show the use of two logically ANDed inputs: i.e. the value for the first bit (Yodd) and a first bit of a pair, and the value for the inverse of the first bit (!Yodd) and a second bit of a pair. The expressions also include an OR operation that takes the two above logically ANDed inputs and OR them together];
a carrier logic that calculates a value of a carry bit when performing a doubling operation is performed, wherein the carrier logic comprises a third AND gate and a second OR gate, and wherein an output of the third AND gate is provided to the second OR gate [Figure 6, wherein "Zodd = Y8+Y6+Yodd*Y4… Zodd is actually the carry out of this digit" Par. 37, shows an AND and OR gate; Figure 3, shows that Zodd is based on the bottom half of the table for Y inputs];
wherein the intermediate value is converted to a binary encoded decimal output ["FIG. 5 depicts circuitry for an exemplary 5,1 code to BCD recoder… The five bits making up a 5,1 code digit… are input and the output result is … the corresponding BCD digit" Par. 36]; and
wherein the intermediate format comprises, for each digit of the intermediate value, a plurality of bits corresponding to a plurality of even weights, a first bit corresponding to a one weight ["When the BCD is recoded to five bits with weights of 8, 6, 4, 2, 0, respectively, and one additional bit indicates whether the value is odd or even" Par. 33];
wherein the intermediate format comprises, for each digit of the intermediate value, six bits [“1st digit = 000010 5,1 code 2nd digit = 000010 5,1 code” par.34, example given on page 3].
Wherein, for each digit of the intermediate value, the one weight is a least significant bit (a sixth bit) [Fig.3, 5,1 code; “When BCD is recoded to five bits… and one additional bit indicates whether the value is odd or even” par.33]
However, Carlough does not explicitly disclose:
wherein each doubler logic comprises a first AND gate, a second AND gate, and a first OR gate, wherein outputs of the first AND gate and the second AND gate are provided to the first OR gate;
an inverse carrier logic that calculates a value of an inverse carry bit when a doubling operation is performed, wherein the inverse carrier logic comprises a fourth AND gate and a third OR gate, wherein an output of the fourth AND gate is provided to the third OR gate;
and a second bit corresponding to an inverse of the one weight, and wherein a bit value for the inverse of the one weight is provided directly to one of the first AND gate or the second AND gate.
wherein the intermediate format comprises, for each digit of the intermediate value, seven bits.
wherein, for each digit of the intermediate value, the inverse of the one weight is a least significant bit (a seventh bit).
In the analogous art of Parallel digital data processing implementations, Beck teaches providing the inverse carry signal alongside the normal carry signal for acceleration ["the carry-not lookahead signals !C0, !C1… are available simultaneously with the carry look-ahead signals C0,C1…” Col.5 Lines 27-30, teaches providing both normal and inverted signals at the same time]
Carlough further discloses that the intermediate format is used in the logical operations shown on paragraph 37, wherein there is a necessity of both Yodd and the inversion of Yodd for each doubling stage and that the next stage uses both the carry Zodd and the inverse carry !Zodd for the next stage as a result ["Note that Zodd is actually the carry out of this digit and it is transmitted to the next more significant digit" Par. 37, wherein Zodd is the next stage Yodd for the Doubler as shown in the example given in page 3].
It would have been obvious to one of ordinary skill in the art, given Beck's benefit to generating both carry and inverse carry, to implement an inverse carry circuit based on Carlough carry circuit. Additionally, it would have been obvious to look within Carlough to find the other cases for !Zodd to be true, looking at figure 3, Zodd is true for the bottom half of the table and the opposite i.e. !Zodd would be true for the top half of the table, wherein Y2, Y0, and Y4*!Yodd would be true.
Additionally, It would have been obvious to one of ordinary skill in the art, seeing the similarities between the carry logic "Zodd=Y8+Y6+Yodd*Y4" and Y2, Y0, and Y4*!Yodd for !Zodd to follow the same circuitry as shown on figure 6 of Carlough.
As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Carlough and Beck before him before the effective filing date of the claimed invention to implement an inverse carry circuit based on figure 6's carry circuit and figure 3's table from Carlough, to include the technique of providing both the carry signal and the inverse carry signal at the same time from Beck, to allow for reducing the time delay from inverting a signal that is required for further stages [Beck: Col.5 Lines 30-33]. The combination of Carlough and Beck discloses the limitation of an inverse carrier logic that calculates a value of an inverse carry bit when a doubling operation is performed, wherein the inverse carrier logic comprises a fourth AND gate and a third OR gate, wherein an output of the fourth AND gate is provided to the third OR gate;
Carlough further discloses that the intermediate format is used in the logical operations shown on paragraph 37, wherein there is a necessity of both Yodd and the inversion of Yodd for each doubling stage, i.e. "...Z8=Yodd*Y8+!Yodd*Y4...".
Additionally, It would have been obvious to one of ordinary skill in the art, seeing that the carry bit (one weight) is appended as the sixth bit [Fig.3] to also append the inverse of the one weight to the 5,1 code as another end bit (i.e. the seventh bit), as there is a necessity of both Yodd and the inversion of Yodd for each doubling stage and that the next stage uses both the carry Zodd and the inverse carry !Zodd for the next stage as a result ["Note that Zodd is actually the carry out of this digit and it is transmitted to the next more significant digit" Par. 37, wherein Zodd is the next stage Yodd for the Doubler as shown in the example given in page 3].
Beck further teaches a technique of “the carry-not lookahead signals… are available simultaneously with the carry look-ahead signals… rather than suffering the time delay which would be necessary if the carry-not look-ahead signals were to be derived by inverting the carry look-ahead signals”.
It would have been obvious to one of ordinary skill in the art, that the technique from Beck is generalizable to all signals and not only the carry signals. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Carlough and Beck before him before the effective filing date of the claimed invention to modify the intermediate format’s Yodd signal disclosed by Carlough to include the technique of providing both the signal and the inverse signal at the same time from Beck, to allow for reducing the time delay from inverting a signal that is required for further stages [Beck: Col.5 Lines 30-33]. The combination of Carlough and Beck discloses and a second bit corresponding to an inverse of the one weight, and wherein a bit value for the inverse of the one weight is provided directly to one of the logical expression first AND gate or the second AND gate. wherein the intermediate format comprises, for each digit of the intermediate value, seven bits. wherein, for each digit of the intermediate value, the inverse of the one weight is a least significant bit (a seventh bit).
However, Carlough and Beck does not explicitly disclose:
wherein each doubler logic comprises a first AND gate, a second AND gate, and a first OR gate, wherein outputs of the first AND gate and the second AND gate are provided to the first OR gate; wherein a bit value for the inverse of the one weight is provided directly to one of the first AND gate or the second AND gate.
In the analogous art of Logic Circuit Design and Architecture, Harris teaches sum of product design PLA architecture implementation and logic expression to gates [“This is called the sum-of-products canonical form of a function because it is the sum (OR) of products (ANDs forming minterms)“ p.54-55, sec.2.2.2; “Programmable logic arrays (PLAs) implement two-level combinational logic in sum-of-products (SOP) form” p.266, sec. 5.6.1; “Any Boolean equation in sum-of-products form can be drawn as a
schematic in a systematic way similar to Figure 2.23” p.63, sec.2.4]
It would have been obvious to one of ordinary skill in the art, having the teachings of Carlough, Beck, and Harris before him before the effective filing date of the claimed invention to incorporate the sum-of-products PLA implementation as taught by Harris into the logic components as disclosed by the combination of Carlough and Beck to allow for inexpensive simplified design for a two-level combinational logic in a sum-of-product form and shortest equations based on truth tables [Harris: p.54-56, 62-65, and 266-267]. The combination of Carlough, Beck, and Harris discloses the implementation of doubler logic gates and sum-of-product implementations, as such Carlough, Beck, and Harris discloses wherein each doubler logic comprises a first AND gate, a second AND gate, and a first OR gate, wherein outputs of the first AND gate and the second AND gate are provided to the first OR gate; wherein a bit value for the inverse of the one weight is provided directly to one of the first AND gate or the second AND gate.
Regarding claim 9, Carlough, Beck, and Harris disclose the invention substantially as claimed. See the discussion of claim 8 above.
Carlough further discloses: wherein shifting the bit of the input binary integer and doubling the intermediate value are performed a plurality of times within a same clock cycle ["The binary operand latch 102 shifts left once for each cycle... it feeds the MSB of the binary operand into the 5,1 code doubler 110... so on until all bits in the binary operand latch 102 have been input to the 5,1 code doubler 110." Par. 18; Page 3 shows a 4-parallel bit variant executed per cycle (loop), where they show the double and shifting of bit in the cycle].
Regarding claim 10, Carlough, Beck, and Harris disclose the invention substantially as claimed. See the discussion of claim 8 above.
Carlough further discloses: wherein the plurality of even weights comprises an eight weight, a six weight, a four weight, a two weight, and a zero weight ["When the BCD is recoded to five bits with weights of 8, 6, 4, 2, 0, respectively" Par. 33].
Regarding claim 11, Carlough, Beck, and Harris disclose the invention substantially as claimed. See the discussion of claim 8 above.
Carlough further discloses: wherein each bit of the plurality of bits corresponds to a doubler logic of a plurality of doubler logics, and wherein doubling the intermediate value comprises providing, to each doubler logic of the plurality of doubler logics, a pair of bit values of the plurality of bits, a value for the first bit, and a value of the inverse of the first bit ["A digit expressed in 5,1 code is input (i.e., Y) and the output is the digit doubled (i.e., Z) and expressed in 5,1 code. The circuitry depicted in FIG. 6 may be expressed by the formulas that follow" Par. 37, wherein they show the logic that requires a pair of bit values and a value for the first bit and the inverse of the first bit, i.e. Yodd and NOT Yodd respectively].
However, Carlough does not explicitly disclose providing a value of the second bit.
In the analogous art of Parallel digital data processing implementations, Beck teaches a technique of “the carry-not lookahead signals… are available simultaneously with the carry look-ahead signals… rather than suffering the time delay which would be necessary if the carry-not look-ahead signals were to be derived by inverting the carry look-ahead signals” as noted in claim 8.
It would have been obvious to one of ordinary skill in the art, that the technique from Beck is generalizable to all signals and not only the carry signals. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Carlough and Beck before him before the effective filing date of the claimed invention to modify the provision of the Yodd signal disclosed by Carlough to include the technique of providing both the signal and the inverse signal at the same time from Beck, to allow for reducing the time delay from inverting a signal that is required for the logic [Beck: Col.5 Lines 30-33]. The combination of Carlough and Beck teaches the limitation of “wherein each bit of the plurality of bits corresponds to a doubler logic of a plurality of doubler logics, and wherein doubling the intermediate value comprises providing, to each doubler logic of the plurality of doubler logics, a pair of bit values of the plurality of bits, a value for the first bit, and a value of the second bit.”
Regarding claim 12, Carlough, Beck, and Harris disclose the invention substantially as claimed. See the discussion of claim 11 above.
Carlough further discloses: wherein each doubler logic comprises: A logical expression of a first AND accepting, as input, a first bit value from the pair of bit values and the value for the first bit; A logical expression of a second AND accepting, as input, a second bit value from the pair of bit values and the value for the inverse of the first bit; and A logical expression of an OR accepting, as input, an output from the first AND gate and an output from the second AND gate ["Z8=Yodd*Y8+!Yodd*Y4..." Par. 37, the expressions show the use of two logically ANDed inputs: i.e. the value for the first bit (Yodd) and a first bit of a pair, and the value for the inverse of the first bit (!Yodd) and a second bit of a pair. The expressions also include an OR operation that takes the two above logically ANDed inputs and OR them together]
However, Carlough does not explicitly disclose first AND gate, a second AND gate, and an OR gate, and wherein a second AND gate accepting, as input, a second bit value from the pair of bit values and the value for the second bit.
In the analogous art of Parallel digital data processing implementations, Beck teaches a technique of “the carry-not lookahead signals… are available simultaneously with the carry look-ahead signals… rather than suffering the time delay which would be necessary if the carry-not look-ahead signals were to be derived by inverting the carry look-ahead signals” as noted in claim 8.
It would have been obvious to one of ordinary skill in the art, that the technique from Beck is generalizable to all signals and not only the carry signals. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Carlough and Beck before him before the effective filing date of the claimed invention to modify the second AND input for the inverse of the first bit disclosed by Carlough to use the technique of providing both the signal and the inverse signal at the same time from Beck, in order to have a second bit value of the inverse of the first bit, to allow for reducing the time delay from inverting a signal that is required for the logic [Beck: Col.5 Lines 30-33]. The combination of Carlough and Beck teaches the limitation of “a second AND accepting, as input, a second bit value from the pair of bit values and the value for the second bit.”
In the analogous art of Logic Circuit Design and Architecture, Harris teaches sum of product design PLA architecture implementation and logic expression to gates [“This is called the sum-of-products canonical form of a function because it is the sum (OR) of products (ANDs forming minterms)“ p.54-55, sec.2.2.2; “Programmable logic arrays (PLAs) implement two-level combinational logic in sum-of-products (SOP) form” p.266, sec. 5.6.1; “Any Boolean equation in sum-of-products form can be drawn as a
schematic in a systematic way similar to Figure 2.23” p.63, sec.2.4]
It would have been obvious to one of ordinary skill in the art, having the teachings of Carlough, Beck, and Harris before him before the effective filing date of the claimed invention to incorporate the sum-of-products PLA implementation as taught by Harris into the logic components as disclosed by the combination of Carlough and Beck to allow for inexpensive simplified design for a two-level combinational logic in a sum-of-product form and shortest equations based on truth tables [Harris: p.54-56, 62-65, and 266-267]. The combination of Carlough, Beck, and Harris discloses the additional limitations of claim 12.
Regarding claim 13, Carlough, Beck, and Harris disclose the invention substantially as claimed. See the discussion of claim 8 above.
Carlough further discloses: wherein doubling the intermediate value further comprises calculating, for each digit of the intermediate value, the carry bit ["Note that Zodd is actually the carry out of this digit and it is transmitted to the next more significant digit" Par. 37, wherein Zodd is the next stage Yodd for the Doubler as shown in the example given in page 3].
However, Carlough does not explicitly disclose wherein doubling the intermediate value further comprises calculating, for each digit of the intermediate value, the carry bit and the inverse carry bit.
In the analogous art of Parallel digital data processing implementations, Beck teaches providing both the carry signal and the inverse carry signal ["the carry-not lookahead signals !C0, !C1… are available simultaneously with the carry look-ahead signals C0,C1…" Col.5 Lines 27-30]
It would have been obvious to one of ordinary skill in the art, that the technique from Beck is generalizable to all signals and not only the carry signals. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Carlough and Beck before him before the effective filing date of the claimed invention to modify carry signal disclosed by Carlough to use the technique of providing both the carry signal and the inverse carry signal at the same time from Beck, to allow for reducing the time delay from inverting a signal that is required for further stages [Beck: Col.5 Lines 30-33]. The combination of Carlough and Beck teaches the limitation of “wherein doubling the intermediate value further comprises calculating, for each digit of the intermediate value, the carry bit and the inverse carry bit.”
Regarding claim 14, Carlough, Beck, and Harris disclose the invention substantially as claimed. See the discussion of claim 13 above.
Carlough further discloses: wherein the value of the first bit for a given digit correspond to the carry bit for an adjacent digit ["Note that Zodd is actually the carry out of this digit and it is transmitted to the next more significant digit" Par. 37, discloses that the first bit (Zodd) is the same first bit in the next digit].
However, Carlough does not explicitly disclose wherein the value of the first bit and the value of the second bit for a given digit correspond to the carry bit and the inverse carry bit for an adjacent digit.
In the analogous art of Parallel digital data processing implementations, Beck teaches providing both the carry signal and the inverse carry signal ["the carry-not lookahead signals !C0, !C1… are available simultaneously with the carry look-ahead signals C0,C1…" Col.5 Lines 27-30]
It would have been obvious to one of ordinary skill in the art, that the technique from Beck is generalizable to all signals and not only the carry signals. As such, it would have been obvious to one of ordinary skill in the art, having the teachings of Carlough and Beck before him before the effective filing date of the claimed invention to modify the corresponding carry bit for the next digit disclosed by Carlough to include the both the carry signal and the inverse carry signal from Beck, to allow for reducing the time delay from inverting a signal that is required for further stages [Beck: Col.5 Lines 30-33]. The combination of Carlough and Beck teaches the limitation of “wherein the value of the first bit and the value of the second bit for a given digit correspond to the carry bit and the inverse carry bit for an adjacent digit.”
Claims 1-7 is directed to claims 8-14, respectively. A mere change in statutory class is obvious. As such, claims 1-7 is rejected for the reasons given for claims 8-14.
Claims 15-20 is directed to claims 8-13, respectively. A mere change in statutory class is obvious. As such, claims 15-20 is rejected for the reasons given for claims 8-13.
Response to Amendment
Applicant’s amendment to claim 15 is non-compliant with 37 CFR 1.121(c)(2), wherein at least the text of any added subject matter must be shown by underlining the added text. For example: from the prior claims listing (09/03/2025) “(Currently Amended) An apparatus for reduced logic conversion of binary integers to one or more doubler logics that double an…” should be shown as “(Currently Amended) an apparatus for reduced logic conversion of binary integers to to binary coded decimals, comprising: one or more doubler logics that double an…” for the current claims listing. This non-compliance has been waived, however Examiner notes that future responses must comply with 37 CFT 1.121, in the case that a future response does not comply, the Office will mail a Notice of Non-compliance.
Response to Arguments
Applicant's arguments filed, see page 9-12, filed 09/03/2025, with respect to Rejections under 35 U.S.C. 101 have been fully considered but they are not persuasive.
Regarding applicant’s arguments to Prong One of Step 2A in view of claim 8:
On pages 9-10, the applicant argues that the claim does not recite a general mathematical formula for conversion but is a technical tool. However, the applicant’s argument is not directed to the proper test of Prong One of Step 2A. Under Prong One, “examiners evaluate whether the claim recites a judicial exception, i.e. whether a law of nature, natural phenomenon, or abstract idea is set forth or described in the claim.” See MPEP 2106.04. The claim recites abstract ideas as shown above under 35 U.S.C. 101. The use of determine instead of calculates still performs the corresponding doubling operation, and the definition of determine also includes: to find out or come to a decision about by calculation. See Merriam-Webster (NPL: “Definition of Determine”). In view of Gottschalk v. Benson, 409 U.S. 63, 70, 175 USPQ 673, 676 (1972), hereinafter Benson, the conversion of binary-coded-decimal (BCD) numerals into pure binary numbers is directed to “Mathematical Concepts” of abstract ideas. As such, the inverse process which is converting binary into binary-coded-decimal (BCD) numerals is directed to “Mathematical Concepts” of abstract ideas. In Benson the Supreme Court have found types of operations falls under “Mathematical Concepts” of abstract ideas, i.e. shifting.
Regarding applicant’s arguments to Prong Two of Step 2A in view of claim 8:
On page 11, the applicant argues the preamble intended use for the chip makes the chip not a general purpose machine or computer. However, the preamble is not given patentable weight. See MPEP 2111.02.
On page 11-12, the applicant argues the doubler logic configuration improves the performance of the chip. However, the layout of the configuration is merely an ordering of mathematical operations that is a consequence of the abstract idea. The abstract idea can not provide the improvement. See 2106.05(a).
On page 12, the applicant argues multiple doubling stages can be performed within the same clock cycle. However, the features upon which applicant relies (i.e., same clock cycle) are not recited in the claim. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Furthermore, if considering the executing of the multiple doubling stages in a clock cycle as an additional element would fall under as mere instructions using a generic computer component to process the data within a cycle to implement the abstract idea. The examiner respectfully disagrees with the applicant’s assertion to the contrary for at least the reasons given above.
Applicant's arguments filed, see page 13-14, filed 09/03/2025, with respect to Rejections under 35 U.S.C. 103 have been fully considered but they are not persuasive. Applicant’s arguments are directed to the newly added features and asserts that the cited portions does not disclose the features as amended. However, the arguments are directed against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The examiner respectfully disagrees with the applicant’s assertion to the contrary for at least the reasons given above and in the rejection towards the new limitations under 35 U.S.C. 103.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenny K. Bui whose telephone number is (571)270-0604. The examiner can normally be reached 8:00 am to 3:00 pm on Monday, 8:00 am to 4:00 pm on Tuesday to Friday ET.
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/KENNY K. BUI/Patent Examiner, Art Unit 2182 (571)270-0604
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182