Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in
37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible
for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has
been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37
CFR 1.114. Applicant's submission filed on May 30, 2025 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 6/3/2023 are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 23, 24, 28, and 29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 23, lines 1 and 2, it is not clear if it is intended that a common mode voltage is maintained depends on power state of the “PCIe interface device” or “solid state drive” since the solid state drive includes the PCIe interface device.
In claim 24, lines 1 and 2, it is not clear if it is intended that activation of upstream port or downstream port depends on power state of the “PCIe interface device” or “solid state drive” since the solid state drive includes the PCIe interface device.
In claim 28, line 3, it is not clear whether a second idle state is longer, shorter, or the same idle duration as the first idle state.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 5, 21, and 23-28 are rejected under 35 U.S.C. 103 as being unpatentable over Sela et al. (U.S. Publication No. 2011/0173352 A1), hereafter referred to as Sela’352 in view of Trivedi et al. (U.S. Publication No. 2014/0019654 A1), hereafter referred to as Trivedi’654.
Referring to claim 1, Sela’352, as claimed, a peripheral component interconnect express (PCIe) interface device (PCIe, see para. [0022]) comprising: a lane group comprising a default lane and at least one or more lanes forming a link for communication between a host (host 34 and a direct memory access (DMA) device (link 26 comprising sub-links 28 and 30; each sub-link comprising multiple lanes 32, see Fig. 1 and paras. [0023]); a command queue configured to store commands for the DMA device generated based on a request of the host (queues for data traffic in response to work request, see para. [0024] and Fig. 1); and a link manager configured to detect whether the link is in a first idle state, and change power of the link from a first state to a second power state when the link is detected in the first idle state (full-bandwidth state, low-bandwidth state, etc., see paras. [0028], [0032]-[0036]), wherein power consumption of the second power state is lower than power consumption of the first power state (discovering that the queues are empty and have remained so for a threshold period, deactivate one or more lanes, see para. [0025]; the controller changes any number of lanes to be active or inactive based on traffic level, see para. [0028]; deactivated lanes are powered down or switch to reduced levels in order to reduce power consumption, see para. [0031]).
However, Sela’352 does not explicitly teach the PCIe interface device is embodied within a solid state drive comprising a buffer memory configured to store data received from a host; a non-volatile memory configured to retain the stored data when a power supply configured to provide power to the non-volatile memory is cut off; and a command queue storing commands for DMA device.
Trivedi’654 discloses the PCIe interface device is embodied within a solid state drive (solid state drives (SSDs), storage drives, see paras. [0044] and [0051]) comprising a buffer memory configured to store data received from a host; a non-volatile memory (SSDs have nonvolatile memory, see para. [0051]; also note: stored in non-volatile data storage, see para. [0051]) configured to retain the stored data when a power supply configured to provide power to the non-volatile memory is cut off; a command queue storing commands for DMA device (command and data queues, see para. [0019]; monitoring the command/data queues; counts the queue depth using for example a leaky bucket algorithm in the ingress and egress ports, see paras. [0019]-[0021]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify Sela’352’s invention to comprise the PCIe interface device is embodied within a solid state drive comprising a buffer memory configured to store data received from a host; a non-volatile memory configured to retain the stored data when a power supply configured to provide power to the non-volatile memory is cut off and a command queue storing commands for DMA device, as taught by Trivedi’654, in order to provide power savings without impacting performance (see Trivedi’654, para. [0042]).
As to claim 2, Sela’352 also discloses the link manager detects the link as the first idle state when a time period during which packets are not transmitted and received with the host through the link elapses a reference time (discovering that the queues are empty and have remained so for a threshold period, deactivate one or more lanes, see para. [0025]).
As to claim 4, Sela’352 also discloses the link manager changes the power of the link to the normal state when the link is released from the first idle state (the controller activates any number of lanes depending of traffic level, see paras. [0028]; also note increasing number of active lanes or full bandwidth, see paras. [0028] and [0034]).
As to claim 5, Sela’352 also discloses the link manager changes the power of the link from the normal state to the low power state when the link is detected as the first idle state even if there is a command stored in the command queue time (discovering that the queues are low and have remained so for a threshold period, deactivate one or more lanes, see para. [0025]).
As to claim 21, Sela’352 also discloses the first power state includes a L0 state in which data is transmitted and received and the second power state indicates a L1 state in which additional power is saved more than the L0 state (full-bandwidth state, low-bandwidth state, etc., see paras. [0028], [0032]-[0036]).
As to claim 23, Sela’352 also discloses a common mode voltage is to be maintained or not is dependent on a power state of the PCIe interface device (deactivated lanes powered down, i.e. supply voltage and clock circuits for the lanes in question are switched off or switched to reduced levels in order to reduce power consumption, see paras. [0018], [0031], and [0033]).
As to claim 24, Sela’352 also discloses an activation of upstream port or downstream port is dependent on a power state of the PCIe interface device device (deactivated lanes powered down, i.e. supply voltage and clock circuits for the lanes in question are switched off or switched to reduced levels in order to reduce power consumption, see paras. [0018], [0031], and [0033]).
As to claim 25, Sela’352 also discloses the first power state is changed to the second power state when the command queue is empty during more than a first reference time (discovering that the queues are empty and have remained so for a threshold period, deactivate one or more lanes, see paras. [0025] and [0027]).
As to claim 26, Sela’352 also discloses the second power state is changed to a third power state when the command queue is empty during more than a second reference time (discovering that the queues are empty and have remained so for a threshold period, deactivate one or more lanes, see paras. [0025] and [0027]).
As to claim 27, Sela’352 also discloses the first power state is changed to the second power state when the command queue is empty during more than a first reference time (discovering that the queues are empty and have remained so for a threshold period, deactivate one or more lanes, see paras. [0025] and [0027]), wherein the second power state is changed to a third power state when the command queue is empty during more than a second reference time, and wherein the second reference time is greater is greater than the first reference time (discovering that the queues are empty and have remained so for a threshold period, deactivate one or more lanes, see paras. [0025] and [0027]).
As to claim 28, Sela’352 also discloses the link manager is configured to change (full-bandwidth state, low-bandwidth state, etc., see paras. [0028], [0032]-[0036]) power of the link from a second power state to a third power state in response to detecting a second idle state of the link after the power of the link enters the second power state (discovering that the queues are empty and have remained so for a threshold period, deactivate one or more lanes, see para. [0025]; the controller changes any number of lanes to be active or inactive based on traffic level, see para. [0028]; deactivated lanes are powered down or switch to reduced levels in order to reduce power consumption, see para. [0031]).
Claim(s) 3, 22, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Sela’352 in view of Trivedi’654 and further in view of Leucht-Roth et al. (U.S. Publication No. 2019/0064915 A1), hereafter referred to as Leucht-Roth’915.
As to claim 3, Sela’352 and Trivedi’654 does not explicitly teach the link manager changes the power of the link from the low power state to the ultra-low power state when a preset time elapses after the link enters the first idle state.
Leucht-Roth’915 discloses the link manager changes the power of the link from the low power state to an ultra-low power state when a preset time elapses after the link enters the idle state (the link transition to a PCIe D0/L1.2 idle state 724 in response to sleep notification when the communication module reaches an idle loop due to inactivity, see para. [0058]; the attributes of the present idle condition justify transition into a lower power idle state, or “suspend” state. The suspend state corresponds to a D3 idle state (and corresponding link state (e.g. L2)), while sleep state corresponds to D0 idle state (e.g. L1.2), see paras. [0062]; entry into the D3 state is beneficial only for longer idle times such as after a greater than 10 second idle interval, see para. [0075] and Figs. 12A-B).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify Sela’352 and Trivedi’654’s invention to comprise the link manager changes the power of the link from the low power state to an ultra-low power state when a preset time elapses after the link enters the idle state, as taught by Leucht-Roth’915, in order to promote more frequent use of D3 idle states to further reduce power consumption (see Leucht-Roth’915, paras. [0054]-[0056]).
As to claim 22, Sela’352 and Trivedi’654 does not explicitly teach the third power state indicates a L1.2 state in which an upstream port and a downstream port are inactivated.
Leucht-Roth’915 discloses the third power state indicates a L1.2 state in which an upstream port and a downstream port are inactivated (the link transition to a PCIe D0/L1.2 idle state 724 in response to sleep notification when the communication module reaches an idle loop due to inactivity, see para. [0058]; the attributes of the present idle condition justify transition into a lower power idle state, or “suspend” state. The suspend state corresponds to a D3 idle state (and corresponding link state (e.g. L2)), while sleep state corresponds to D0 idle state (e.g. L1.2), see paras. [0062]; entry into the D3 state is beneficial only for longer idle times such as after a greater than 10 second idle interval, see para. [0075] and Figs. 12A-B).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify Sela’352 and Trivedi’654’s invention to comprise the link manager changes the power of the link from the low power state to an ultra-low power state when a preset time elapses after the link enters the idle state, as taught by Leucht-Roth’915, in order to promote more frequent use of D3 idle states to further reduce power consumption (see Leucht-Roth’915, paras. [0054]-[0056]).
As to claim 29, Sela’352 and Trivedi’654 does not explicitly teach power consumption of the solid state drive decreases in an order of the first power state, the second power state, and the third power state.
Leucht-Roth’915 discloses power consumption of the solid state drive decreases in an order of the first power state, the second power state, and the third power state (the link transition to a PCIe D0/L1.2 idle state 724 in response to sleep notification when the communication module reaches an idle loop due to inactivity, see para. [0058]; the attributes of the present idle condition justify transition into a lower power idle state, or “suspend” state. The suspend state corresponds to a D3 idle state (and corresponding link state (e.g. L2)), while sleep state corresponds to D0 idle state (e.g. L1.2), see paras. [0062]; entry into the D3 state is beneficial only for longer idle times such as after a greater than 10 second idle interval, see para. [0075] and Figs. 12A-B).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify Sela’352 and Trivedi’654’s invention to comprise power consumption of the solid state drive decreases in an order of the first power state, the second power state, and the third power state, as taught by Leucht-Roth’915, in order to promote more frequent use of D3 idle states to further reduce power consumption (see Leucht-Roth’915, paras. [0054]-[0056]).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Sela’352 in view of Trivedi’654 and further in view of Song et al. (U.S. Patent No. 9,467,120 B1), hereafter referred to as Song’120.
As to claim 6, Sela’352 discloses the link manager deactivates the at least one or more lanes (deactivated lanes are powered down or switch to reduced levels in order to reduce power consumption, see para. [0031]).
However, Sela’352 and Trivedi’654 do not appear to teach providing a second operation clock lower than the first operation clock to the DMA device when the power of the link is changed from the first power state to the second power state.
Song’120 discloses providing a second operation clock lower than the first operation clock to the DMA device when the power of the link is changed from the first power state to the second power state (disabling clocking of logic components during periods of non-activity such that the clocking may be enabled or re-enabled based on incoming wake data and/or signals to that logic component, see Col. 4, lines 47-67; also note: PCIe link entering into a low power state, see Col. 4, line 60 to Col. 5, line 31).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify Sela’352 and Trivedi’654’s invention to comprise providing a second operation clock lower than the first operation clock to the DMA device when the power of the link is changed from the first power state to the second power state, as taught by Song’120, in order to manage power of a device thus providing power optimization and power consumption reduction (see Col. 1, lines 40-51).
As to claim 7, Sela’352 and Trivedi’654 do not appear to teach the second operation clock is obtained by multiplying the first operation clock by a ratio of a number of activated lanes to a total number of lanes included in the lane group.
Song’120 discloses the second operation clock is obtained by multiplying the first operation clock by a ratio of a number of activated lanes to a total number of lanes included in the lane group (disabling clocking of logic components during periods of non-activity such that the clocking may be enabled or re-enabled based on incoming wake data and/or signals to that logic component, see Col. 4, lines 47-67; also note: PCIe link entering into a low power state, see Col. 4, line 60 to Col. 5, line 31).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify Sela’352 and Trivedi’654’s invention to comprise the second operation clock is obtained by multiplying the first operation clock by a ratio of a number of activated lanes to a total number of lanes included in the lane group, as taught by Song’120, in order to manage power of a device thus providing power optimization and power consumption reduction (see Col. 1, lines 40-51).
In addition, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to multiplying the first operation clock by a ratio of a number of activated lanes to a total number of lanes included in the lane group (i.e. reducing operation clock when there are less activated lanes or increasing operation clock when there are more activated lanes) since it has been held to be within the general skill in the art on the basis of its suitability for the intended use as a matter of obvious design choice and to reduce power consumption. In re Leshin, 125 USPQ 416.
Response to Arguments
Applicant's arguments filed 5/30/2025 have been fully considered but they are moot due to new grounds of rejection.
In the latest filed response, claim limitations from independent claim 1 were removed (i.e. lowest relative power state and change in power of link when a second idle state is detected) that broadened the scope of the claims, such as to claims 1, 3, 26, 27, and 28. As such, the “third power state” in claims 3, 26, 27, and 28 is now interpreted as any power state/level (i.e. increased/decreased power consumption with respect to “first” or “second” power states, or “equal”). Therefore, the art rejection was updated accordingly.
Applicant is suggested to clarify the third power state.
In summary, Sela’352, Trivedi’654, Leucht-Roth’915, and Song’120 teach the claimed limitations as set forth.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Guddeti et al. (U.S. Publication No. 2014/0115223 A1) discloses dual casting PCIe inbound writes to memory and peer devices.
AVEZ et al. (U.S. Publication No. 2014/0281099 A1) discloses a method for controlling flow of PCIe transport layer packets.
Puranik (U.S. Patent No. 8,122,177 B1) discloses direct memory access technique for use with PCIe endpoints.
Liu (U.S. Publication No. 2014/0281040 A1) discloses namespace access control in NVM Express PCIe NVM with SR-IOV.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Contact Information
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/TITUS WONG/Primary Examiner, Art Unit 2181
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