DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114.
Applicant's submission filed on 04/30/2026 has been entered.
Claims 1-20 have been examined.
Response to Amendment
In the instant amendment, claims 1, 3, 8, 10, 15 and 17 have been amended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4, 8-9, 11-12, 15-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0187964 to Wyse et al. (hereafter “Wyse”) and further in view of US 2011/0296428 to Rawson, III et al. (hereafter “Rawson”)
As per claim 1, Wyse discloses a method, comprising:
allocating (FIGs. 3-4; paragraphs 0037-0038: “For example, the compilation tool can first seek to identify immediately adjacent instructions (instructions with a distance of one) with operands mapping to the same physical bank of the register file.”), at a compiler (FIGs. 3-4; paragraphs 0032 and 0037-0038: “In one embodiment, source language processing unit 306 represents one application (or tool) and analysis and conversion units 310 and 312, respectively, together form a second application (or tool) 330. Alternatively, all units can be included as part of a single tool or application.” [Wingdings font/0xE0] a combination of 306, 310 and 312 –> a compilation tool), physical registers of a physical register file (FIGs. 3-4; paragraphs 0037-0039: : For example, the compilation tool can first seek to identify immediately adjacent instructions (instructions with a distance of one) with operands mapping to the same physical bank of the register file. Having completed this analysis, the compilation tool could analyze instructions with a distance of two for operands that map to the same physical bank, then a distance of three, and so on.) of a parallel processor (FIGs. 1-2 and 4; paragraphs 0016-0017, 0024, 0026-0027, 0035-0037 and 0039: “the registers V1 and V9 were located in different physical banks, an access to both registers could be performed simultaneously and the execution latency of the instruction could be reduced.” [Wingdings font/0xE0] CPU 165 including multiple Processing Unit 175A-N and GPU 135 including compute Unit 145A-N allocated among plurality of banks of physical registers in a currently/simultaneously (parallelly) processing manner) to a wavefront (FIGs. 3-4; paragraphs 0037-0040: executable codes including instructions which is compiled by the compiling tool) for mapping to virtual registers (FIGs. 3-4; paragraphs 0037-00340: “Various embodiments are contemplated for assigning virtual registers such that they map to different physical banks. In one embodiment, virtual registers can be mapped to locations in the register file using a base offset into the register file (e.g., an offset that corresponds to a given row of the register file shown in FIG. 2) and an index that identifies a particular bank.”),
wherein the bank access conflict comprises instructions of the wavefront requiring access to unique registers from the same bank of the physical register file in the same cycle (paragraphs 0003 and 0024: “instructions attempt to access registers that reside in the same physical banks in the same cycle, resulting in a bank access conflict. For example, assuming the register file organization depicted in FIG. 2, the following instruction V0=V1+V9 includes two operands in the same physical bank. In this case, both of the register V1 and V9 reside in bank B 220B. Consequently, accesses to the registers V1 and V9 must be serialized. This serialization of accesses increases the execution latency of the instruction.”).
Wyse discloses execution of the wavefront at the parallel processor (FIGs. 1-2 and 4; paragraphs 0016-0017, 0024, 0026-0027, 0035-0037 and 0039: “the registers V1 and V9 were located in different physical banks, an access to both registers could be performed simultaneously and the execution latency of the instruction could be reduced.” [Wingdings font/0xE0] CPU 165 including multiple Processing Unit 175A-N and GPU 135 including compute Unit 145A-N allocated among plurality of banks of physical registers in a currently/simultaneously (parallelly) processing manner), and physical registers at different banks of the physical register file (FIGs. 3-4; paragraphs 0037-0040) however Wyse does not explicitly disclose remapping, at a remapping circuit, the virtual registers to physical registers at different banks of the physical register file during execution of the wavefront at the parallel processor in response to a bank access conflict, the remapping being based on a subset of physical registers of the physical register file that are available for remapping and a remapping policy.
Rawson further discloses remapping, at a remapping circuit, the virtual registers to physical registers at different banks (FIG. 5; blocks 512-518) during execution of the wavefront (FIGs. 3-8; paragraphs 0069-0071: “An embodiment may transfer, trade, re-allocate, or otherwise make available physical registers 516 from thread 502 to thread 504 if such availability is deemed advantageous to thread 504 without adversely affecting thread 502. Thread 502's performance remains unaffected from such re-allocation because thread 502 was not utilizing physical registers 516 prior to the re-allocation. The performance of thread 504, on the other hand, may improve due to the re-allocation according to the embodiment because thread 504 can now utilize physical registers subsets 518 as well as 516.” [Wingdings font/0xE0] during the execution of application 402 including threads [Wingdings font/0xE0] detecting thread 504 needs more physical registers while thread 502 does not use all of its physical registers [Wingdings font/0xE0] reallocating/remapping a portion of logical registers of thread 504 to available block physical registers 512 (FIG. 5)) at the parallel processor (paragraphs 0007 and 0026) in response to a bank access conflict (FIGs. 5-11; paragraphs 0069-0071: detecting one thread needs more physical during the execution), the remapping being based on a subset of physical registers that are available for remapping (FIGs. 3-8; paragraphs 0069-0071: block physical registers 512 which is available) and a remapping policy (FIGs. 3-5; paragraphs 0058, 0070-0071 and 0082: “An embodiment may transfer, trade, re-allocate, or otherwise make available physical registers 516 from thread 502 to thread 504 if such availability is deemed advantageous to thread 504 without adversely affecting thread 502. Thread 502's performance remains unaffected from such re-allocation because thread 502 was not utilizing physical registers 516 prior to the re-allocation. The performance of thread 504, on the other hand, may improve due to the re-allocation according to the embodiment because thread 504 can now utilize physical registers subsets 518 as well as 516.” [Wingdings font/0xE0] the remap policy that follows “transfer, trade, re-allocate, or otherwise make available physical registers 516 from thread 502 to thread 504 if such availability is deemed advantageous to thread 504 without adversely affecting thread 502”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Rawson into Wyse’s teaching because it would provide for the purpose of improving register allocation among threads in a simultaneous multithreaded processor (Rawson, paragraph 0008).
As per claim 2, Wyse discloses storing a set of virtual register to physical register mappings at a mapping table (FIG. 2, paragraph 0040) comprising a plurality of entries, each entry comprising a valid bit and a physical register index indicating a first physical location in the physical register file where a virtual register resides (FIG. 2; paragraph 0040: “In one embodiment, virtual registers can be mapped to locations in the register file using a base offset into the register file (e.g., an offset that corresponds to a given row of the register file shown in FIG. 2) and an index that identifies a particular bank. For example, in an embodiment in which the register file has N=4 banks, and 256 rows, an offset can identify a particular row and the index can map to one of the banks”).
As per claim 4, Wyse discloses a first physical location in the physical register file and second physical location in the physical register file (FIGs. 4; paragraphs 0024-0026, 0030, 0036-0038: “If such an intra-instruction bank conflict is detected, the compilation tool will remap the operands of the instruction so that the source and/or destination operands map to different physical banks of the register file (block 414).” [Wingdings font/0xE0] visible register is virtual register as teaches by paragraph 0025 is selectively remapped to different bank instead of the same bank).
Rawson further discloses wherein the remapping policy is to selectively remap the virtual register from a first physical location to a second physical location (FIGs. 3-5; paragraphs 0058, 0070-0071 and 0082: “An embodiment may transfer, trade, re-allocate, or otherwise make available physical registers 516 from thread 502 to thread 504 if such availability is deemed advantageous to thread 504 without adversely affecting thread 502. Thread 502's performance remains unaffected from such re-allocation because thread 502 was not utilizing physical registers 516 prior to the re-allocation. The performance of thread 504, on the other hand, may improve due to the re-allocation according to the embodiment because thread 504 can now utilize physical registers subsets 518 as well as 516.”) in response to execution of the wavefront causing a write to the first physical location (FIGs. 3-8; paragraphs 0069-0071: “An embodiment may transfer, trade, re-allocate, or otherwise make available physical registers 516 from thread 502 to thread 504 if such availability is deemed advantageous to thread 504 without adversely affecting thread 502. Thread 502's performance remains unaffected from such re-allocation because thread 502 was not utilizing physical registers 516 prior to the re-allocation. The performance of thread 504, on the other hand, may improve due to the re-allocation according to the embodiment because thread 504 can now utilize physical registers subsets 518 as well as 516.” [Wingdings font/0xE0] during the execution [Wingdings font/0xE0] detecting thread 504 needs more physical registers while thread 502 does not use all of its physical registers [Wingdings font/0xE0] reallocating/remapping a portion of logical registers of thread 504 to available block physical registers 512 (FIG. 5)).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Rawson into Wyse’s teaching because it would provide for the purpose of improving register allocation among threads in a simultaneous multithreaded processor (Rawson, paragraph 0008).
As per claim 8, Wyse discloses a set of virtual register to physical register (FIGs. 3-4; paragraphs 0037-00340: “Various embodiments are contemplated for assigning virtual registers such that they map to different physical banks. In one embodiment, virtual registers can be mapped to locations in the register file using a base offset into the register file (e.g., an offset that corresponds to a given row of the register file shown in FIG. 2) and an index that identifies a particular bank.”) mappings (FIGs. 3-4; paragraphs 0037-0038: “For example, the compilation tool can first seek to identify immediately adjacent instructions (instructions with a distance of one) with operands mapping to the same physical bank of the register file.”) allocated by a compiler (FIGs. 3-4; paragraphs 0032 and 0037-0038: “In one embodiment, source language processing unit 306 represents one application (or tool) and analysis and conversion units 310 and 312, respectively, together form a second application (or tool) 330. Alternatively, all units can be included as part of a single tool or application.” [Wingdings font/0xE0] a combination of 306, 310 and 312 –> a compilation tool) for physical registers of a physical register file (FIGs. 3-4; paragraphs 0037-0039: : For example, the compilation tool can first seek to identify immediately adjacent instructions (instructions with a distance of one) with operands mapping to the same physical bank of the register file. Having completed this analysis, the compilation tool could analyze instructions with a distance of two for operands that map to the same physical bank, then a distance of three, and so on.) of a parallel processor (FIGs. 3-4; paragraphs 0032 and 0037-0038: “In one embodiment, source language processing unit 306 represents one application (or tool) and analysis and conversion units 310 and 312, respectively, together form a second application (or tool) 330. Alternatively, all units can be included as part of a single tool or application.” [Wingdings font/0xE0] a combination of 306, 310 and 312 –> a compilation tool);
maintaining a list indicating a subset of physical registers of the physical register file that are available for remapping (FIG. 2-4; paragraphs 0023, 0030 and 0037-0039),
wherein the bank access conflict comprises instructions of the wavefront requiring access to unique registers from the same bank of the physical register file in the same cycle (paragraphs 0003 and 0024: “instructions attempt to access registers that reside in the same physical banks in the same cycle, resulting in a bank access conflict. For example, assuming the register file organization depicted in FIG. 2, the following instruction V0=V1+V9 includes two operands in the same physical bank. In this case, both of the register V1 and V9 reside in bank B 220B. Consequently, accesses to the registers V1 and V9 must be serialized. This serialization of accesses increases the execution latency of the instruction.”).
Wyse discloses execution of the wavefront at the parallel processor (FIGs. 1-2 and 4; paragraphs 0016-0017, 0024, 0026-0027, 0035-0037 and 0039: “the registers V1 and V9 were located in different physical banks, an access to both registers could be performed simultaneously and the execution latency of the instruction could be reduced.” [Wingdings font/0xE0] CPU 165 including multiple Processing Unit 175A-N and GPU 135 including compute Unit 145A-N allocated among plurality of banks of physical registers in a currently/simultaneously (parallelly) processing manner), and physical registers at different banks of the physical register file (FIGs. 3-4; paragraphs 0037-0040) however Wyse does not explicitly disclose in response to a bank access conflict, dynamically remapping virtual registers to physical registers at different banks of the physical register file during execution of the wavefront based on the list and a register mapping policy at a remapping circuit.
Rawson further discloses in response to a bank access conflict (FIGs. 5-11; paragraphs 0069-0071: detecting one thread needs more physical during the execution), dynamically remapping virtual registers to physical registers at different banks (FIG. 5; blocks 512-518) during execution of the wavefront (FIGs. 3-8; paragraphs 0069-0071: “An embodiment may transfer, trade, re-allocate, or otherwise make available physical registers 516 from thread 502 to thread 504 if such availability is deemed advantageous to thread 504 without adversely affecting thread 502. Thread 502's performance remains unaffected from such re-allocation because thread 502 was not utilizing physical registers 516 prior to the re-allocation. The performance of thread 504, on the other hand, may improve due to the re-allocation according to the embodiment because thread 504 can now utilize physical registers subsets 518 as well as 516.” [Wingdings font/0xE0] during the execution of application 402 including threads [Wingdings font/0xE0] detecting thread 504 needs more physical registers while thread 502 does not use all of its physical registers [Wingdings font/0xE0] reallocating/remapping a portion of logical registers of thread 504 to available block physical registers 512 (FIG. 5)) based on the list (FIGs. 3-8; paragraphs 0069-0071: block physical registers 512 which is available) and a register mapping policy at a remapping circuit (FIGs. 3-5; paragraphs 0058, 0070-0071 and 0082: “An embodiment may transfer, trade, re-allocate, or otherwise make available physical registers 516 from thread 502 to thread 504 if such availability is deemed advantageous to thread 504 without adversely affecting thread 502. Thread 502's performance remains unaffected from such re-allocation because thread 502 was not utilizing physical registers 516 prior to the re-allocation. The performance of thread 504, on the other hand, may improve due to the re-allocation according to the embodiment because thread 504 can now utilize physical registers subsets 518 as well as 516.” [Wingdings font/0xE0] the remap policy that follows “transfer, trade, re-allocate, or otherwise make available physical registers 516 from thread 502 to thread 504 if such availability is deemed advantageous to thread 504 without adversely affecting thread 502”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Rawson into Wyse’s teaching because it would provide for the purpose of improving register allocation among threads in a simultaneous multithreaded processor (Rawson, paragraph 0008).
As per claim 9, it is a method claim, which recite(s) the same limitations as those of claim 2. Accordingly, claim 9 is rejected for the same reasons as set forth in the rejection of claim 2.
As per claim 11, it is a method claim, which recite(s) the same limitations as those of claim 4. Accordingly, claim 11 is rejected for the same reasons as set forth in the rejection of claim 4.
As per claim 12, Wyse discloses wherein the physical registers of the physical register file are allocated among a plurality of banks (FIGs. 1-2 and 4);
the register mapping policy is to remap the virtual register to a second physical location of a physical register based on an activity level of a bank to which the physical register is allocated (FIG. 4; paragraphs 0036-0040: order intra-instruction bank conflicted [Wingdings font/0xE0] inter-instruction bank conflicted [Wingdings font/0xE0] multi-word operand detected).
As per claim 15, Wyse discloses a parallel processor, comprising:
a physical register file comprising a plurality of banks of physical registers (FIGs. 1-2 and 4), wherein a number of physical registers is allocated (FIGs. 3-4; paragraphs 0037-0038: “For example, the compilation tool can first seek to identify immediately adjacent instructions (instructions with a distance of one) with operands mapping to the same physical bank of the register file.”) to a wavefront (FIGs. 3-4; paragraphs 0037-0040: executable codes including instructions which is compiled by the compiling tool) by a compiler (FIGs. 3-4; paragraphs 0032 and 0037-0038: “In one embodiment, source language processing unit 306 represents one application (or tool) and analysis and conversion units 310 and 312, respectively, together form a second application (or tool) 330. Alternatively, all units can be included as part of a single tool or application.” [Wingdings font/0xE0] a combination of 306, 310 and 312 –> a compilation tool),
wherein the bank access conflict comprises instructions of the wavefront requiring access to unique registers from the same bank of the physical register file in the same cycle (paragraphs 0003 and 0024: “instructions attempt to access registers that reside in the same physical banks in the same cycle, resulting in a bank access conflict. For example, assuming the register file organization depicted in FIG. 2, the following instruction V0=V1+V9 includes two operands in the same physical bank. In this case, both of the register V1 and V9 reside in bank B 220B. Consequently, accesses to the registers V1 and V9 must be serialized. This serialization of accesses increases the execution latency of the instruction.”).
Wyse discloses execution of the wavefront at the parallel processor (FIGs. 1-2 and 4; paragraphs 0016-0017, 0024, 0026-0027, 0035-0037 and 0039: “the registers V1 and V9 were located in different physical banks, an access to both registers could be performed simultaneously and the execution latency of the instruction could be reduced.” [Wingdings font/0xE0] CPU 165 including multiple Processing Unit 175A-N and GPU 135 including compute Unit 145A-N allocated among plurality of banks of physical registers in a currently/simultaneously (parallelly) processing manner), and physical registers at different banks of the physical register file (FIGs. 3-4; paragraphs 0037-0040) however Wyse does not explicitly disclose a remapping circuit configured to remap virtual registers to physical registers at different banks during execution of a wavefront at the parallel processor in response to a bank conflict based on a subset of physical registers that are available for remapping and a remapping policy.
Rawson further discloses a remapping circuit configured to remap virtual registers to physical registers at different banks (FIG. 5; blocks 512-518) during execution of a wavefront (FIGs. 3-8; paragraphs 0069-0071: “An embodiment may transfer, trade, re-allocate, or otherwise make available physical registers 516 from thread 502 to thread 504 if such availability is deemed advantageous to thread 504 without adversely affecting thread 502. Thread 502's performance remains unaffected from such re-allocation because thread 502 was not utilizing physical registers 516 prior to the re-allocation. The performance of thread 504, on the other hand, may improve due to the re-allocation according to the embodiment because thread 504 can now utilize physical registers subsets 518 as well as 516.” [Wingdings font/0xE0] during the execution of application 402 including threads [Wingdings font/0xE0] detecting thread 504 needs more physical registers while thread 502 does not use all of its physical registers [Wingdings font/0xE0] reallocating/remapping a portion of logical registers of thread 504 to available block physical registers 512 (FIG. 5)) at the parallel processor (paragraphs 0007 and 0026) in response to a bank conflict (FIGs. 5-11; paragraphs 0069-0071: detecting one thread needs more physical during the execution) based on a subset of physical registers that are available for remapping (FIGs. 3-8; paragraphs 0069-0071: block physical registers 512 which is available) and a remapping policy (FIGs. 3-5; paragraphs 0058, 0070-0071 and 0082: “An embodiment may transfer, trade, re-allocate, or otherwise make available physical registers 516 from thread 502 to thread 504 if such availability is deemed advantageous to thread 504 without adversely affecting thread 502. Thread 502's performance remains unaffected from such re-allocation because thread 502 was not utilizing physical registers 516 prior to the re-allocation. The performance of thread 504, on the other hand, may improve due to the re-allocation according to the embodiment because thread 504 can now utilize physical registers subsets 518 as well as 516.” [Wingdings font/0xE0] the remap policy that follows “transfer, trade, re-allocate, or otherwise make available physical registers 516 from thread 502 to thread 504 if such availability is deemed advantageous to thread 504 without adversely affecting thread 502”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Rawson into Wyse’s teaching because it would provide for the purpose of improving register allocation among threads in a simultaneous multithreaded processor (Rawson, paragraph 0008).
As per claim 16 it is a processor claim, which recite(s) the same limitations as those of claim 2. Accordingly, claim 16 is rejected for the same reasons as set forth in the rejection of claim 2.
As per claim 18, Wyse discloses wherein the remapping policy is to remap a virtual register to from a first physical location of a first physical register a second physical location of a second physical register based on an activity level of a bank to which each physical register is allocated (FIG. 4; paragraphs 0036-0040: order intra-instruction bank conflicted [Wingdings font/0xE0] inter-instruction bank conflicted [Wingdings font/0xE0] multi-word operand detected)
Claims 3, 5, 7, 10, 14, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wyse, and Rawson, as applied to claims 1, 9 and 15, and further in view of US 2014/0189324 to Combs et al. (hereafter “Comb”)
As per claim 3, Wyse discloses storing a set of virtual register to physical register mappings at a mapping table comprising each entry comprising a register bank index indicating a bank in the physical register file where a virtual register resides (FIG. 2; paragraph 0040).
Combs further discloses a number of entries fewer than the number of physical registers in the physical register file (abstract).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Combs into Wyse’s teaching, and Rawson’s teaching because it would provide for the purpose of for each logical register specified by a renamed instruction, an unused physical register from FL is allocated and RAT is updated with this new mapping (Combs, paragraph 0016).
As per claim 5, Wyse discloses wherein the remapping policy is to remap the virtual register to a second physical location of a physical register based on an activity level of a bank to which the physical register is allocated (FIG. 4; paragraphs 0036-0040: order intra-instruction bank conflicted [Wingdings font/0xE0] inter-instruction bank conflicted [Wingdings font/0xE0] multi-word operand detected).
As per claim 7, Wyse does not explicitly disclose updating the subset of physical registers of the physical register file that are available for remapping based on a hint received compiler indicating that a physical register will not be used again by the wavefront.
Combs further discloses updating the subset of physical registers of the physical register file that are available for remapping based on a hint received compiler indicating that a physical register will not be used again by the wavefront (FIG. 4: block 466, 470, 472 and 474; paragraphs 0045, 0053, 0055 and 0062: “When a counter reaches a pre-determined value (e.g., zero), that entry is evicted (e.g., cleared or marked invalid) and that entry location becomes available. If that entry is the only entry for that physical register, then that physical register becomes free, and it is removed from the active list and added to the free list.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Combs into Wyse’s teaching and Rawson’s teaching because it would provide for the purpose of for each logical register specified by a renamed instruction, an unused physical register from FL is allocated and RAT is updated with this new mapping (Combs, paragraph 0016).
As per claim 10, it is a method claim, which recite(s) the same limitations as those of claim 3. Accordingly, claim 10 is rejected for the same reasons as set forth in the rejection of claim 3.
As per claim 14, it is a method claim, which recite(s) the same limitations as those of claim 7. Accordingly, claim 14 is rejected for the same reasons as set forth in the rejection of claim 7.
As per claim 17 it is a processor claim, which recite(s) the same limitations as those of claim 3. Accordingly, claim 17 is rejected for the same reasons as set forth in the rejection of claim 3.
As per claim 20, it is a processor claim, which recite(s) the same limitations as those of claim 7. Accordingly, claim 20 is rejected for the same reasons as set forth in the rejection of claim 7.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Wyse, Rawson, and Combs, as applied to claim 5, and further in view of US 2016/0350114 to Airaud et al. (hereafter “Airaud”)
As per claim 6, Wyse discloses wherein the remapping policy selects successive physical registers to be reserved by virtual registers to rotate among a plurality of banks (FIGs. 4; paragraphs 0024-0026, 0030, 0036 and 0038).
Airaud further discloses to rotate among the plurality of banks in a round-robin order (paragraph 0091).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Airaud into Wyse’s teaching, Rawson’s teaching and Comb’s teaching because it would provide for the purpose of by using register renaming to map the same architectural register to different physical registers for the two instructions, this can allow the two instructions to be executed in parallel or out of order, which can help to improve performance (Airaud, paragraph 0038).
Claims 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wyse, and Rawson, as applied to claim 12, and further in view of Airaud.
As per claim 13, Wyse discloses wherein the register mapping policy selects successive physical registers to be reserved by virtual registers to rotate among the plurality of banks (FIGs. 4; paragraphs 0024-0026, 0030, 0036 and 0038).
Airaud further discloses to rotate among the plurality of banks in a round-robin order (paragraph 0091).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Airaud into Wyse’s teaching, and Rawson’s teaching because it would provide for the purpose of by using register renaming to map the same architectural register to different physical registers for the two instructions, this can allow the two instructions to be executed in parallel or out of order, which can help to improve performance (Airaud, paragraph 0038).
As per claim 19, Wyse discloses wherein the remapping policy selects successive physical registers to be reserved by virtual registers to rotate among the plurality of banks (FIGs. 4; paragraphs 0024-0026, 0030, 0036 and 0038).
Airaud further discloses to rotate among the plurality of banks in a round-robin order (paragraph 0091).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Airaud into Wyse’s teaching, and Rawson’s teaching because it would provide for the purpose of by using register renaming to map the same architectural register to different physical registers for the two instructions, this can allow the two instructions to be executed in parallel or out of order, which can help to improve performance (Airaud, paragraph 0038).
Response to Arguments
Applicants’ arguments have been considered but are moot in view of the new ground(s) of rejection. Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tuan Dao whose telephone number is (571) 270 3387. The examiner can normally be reached on Monday to Friday from 09am to 05pm. The examiner can also be reached on alternate Fridays.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital, can be reached at telephone number (571) 272 4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUAN C DAO/Primary Examiner, Art Unit 2198
Prosecution Insights