Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Applicant’s Amendments / Arguments Regarding 35 U.S.C. § 102/103
The applicant’s remarks, on pages 6-9 of the response / amendment, the applicant argues the features which allegedly distinguish over the previously cited references cited in the 35 U.S.C. § 102/103 rejections.
Applicant’s arguments have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over by US 9767318 to Dropps (hereinafter Dropps), in view of US 20170286298 to Geetha et al. (hereinafter Geetha).
Regarding claim 1, Dropps teaches,
An apparatus comprising: (figs. 1-4.)
at least one core to execute operations on data; (figs. 1-4 teach circuitry which passes data and executes processes.) (The applicant’s printed publication at [0015] states “used herein, the term “core” refers generally to any type of processing circuitry that is configured to execute instructions, tasks and/or workloads, namely to process data.”)
a cryptographic circuit to perform cryptographic operations; (fig. 2, cryptographic processing 230A-C, initially described in Col. 14, lines 2-22.)
(Dropps, Col. 10, lines 54-65, teaches using one or more types of memory, such as FRAM and SRAM, and teaches hybrid storage related to drives. Col. 11, lines 15-17 teaches all storage and cryptographic processing is performed on the same memory device or the die used for the memory device. Dropps fails to teach hybrid memory coupled to at least one core.)
a static random access memory (SRAM) (fig. 3, Col. 19, line 66 to Col. 20, line 5, teaches a key storage 310A-N may be constructed from SRAM.) coupled to the at least one core; and (fig. 2 shows cryptographical processing modules 230A-C, and Col. 20, lines 61-67 and fig. 4 teach a cryptographic processing circuit 402 used by the cryptographic processing modules 230A-230D, that includes key storage.)
a ferroelectric memory, (Col. 10, lines 54-60 teaches host memory of ferroelectric random access memory (FRAM). Col. 14, lines 2-22 and fig. 2 teach that the memory 210 is connected to management units 220 via signals.)
wherein in response to a single read request the (Col. 14, lines 50-53 teaches read and data load requests.) (The applicant’s printed publication at [0041] describes the “read request” shown in fig. 5, see also [0039-41] for full description of fig. 5’s SRAM and ferroelectric memories in use.) to provide an encryption key to the cryptographic circuit from the SRAM … (fig. 3, Col. 19, line 66 to Col. 20, line 5, teaches a key storage 310A-N may be constructed from SRAM. Col. 18, lines 14-24 teaches the cryptographic processing module 230C uses the key.)
… and provide encrypted data to the cryptographic circuit from the ferroelectric memory, (fig. 2, Col. 14, lines 2-22, teaches memory 210 stores the cryptographically protected program data, which is used by the cryptographically protected CPU 240 (protected by cryptographical process 230 of fig. 2), where memory 210 may be constructed from FRAM (described above.) the encryption key associated with the encrypted data. (fig. 4 and Col. 21, lines 25-35, teaches select the cryptographic key from key storage through address translation and the information to be cryptographically protected.)
Dropps fails to explicitly teach a hybrid memory couped to a core and a single read request to a hybrid memory,
However, Geetha teaches,
hybrid memory coupled to at least one core comprising: ([0014-15] teaches tiered memory, where the different memories have different access times, and [0016] teaches that the memory may be ferro-electric RAM (FRAM).)
wherein in response to a single read request the hybrid memory … ([0059-61] & fig. 5 teach memory encryption engine (MEE) that encrypts and decrypts data in response to a request, where the tiered memory is the near and far memory of MC 505 in fig. 5.)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Dropps, which teaches a cryptographic circuit that performs encryption / decryption where the data being encrypted / decrypted is stored in an SRAM and the key used in cryptography is stored in ferroelectric memory (Abstract & Col. 10, lines 54-60), with Geetha, which also teaches encryption and decryption (fig. 5 & [0059-61]) being performed using ferroelectric memory ([0014]), and additionally teaches the use of tiered memory / “hybrid memory” where the different memories have different access times ([0014]). One of ordinary skill in the art would have been motivated to perform such an addition to provide Droops with the added ability to explicitly utilize a tiered memory, with different access times, to perform encryption and other data processing, as taught by Geetha, for the purpose of increasing computational efficiency by using the appropriately memory, according to access times, while maintaining security by performing encryption / decryption.
Claims 2-3, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Dropps, in view of Geetha, in view of US 20190200207 to Lauster (hereinafter Lauster).
Regarding claim 2, Dropps and Geetha teach,
The apparatus of claim 1,
Dropps fails to teach retrieving a key before retrieving data that is to be decrypted,
However, Lauster teaches,
wherein the cryptographic circuit is to receive the encryption key in advance of receiving the encrypted data. ([0101] teaches decrypting subscriber data, where retrieving a secure key is performed before retrieving the subscriber data.) (Dropps teaches a specific cryptographic circuit, as opposed to software.)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Dropps, which teaches a cryptographic circuit that performs encryption / decryption where the data being encrypted / decrypted is stored in an SRAM and the key used in cryptography is stored in ferroelectric memory (Abstract & Col. 10, lines 54-60), with Geetha, which also teaches encryption and decryption (fig. 5 & [0059-61]) being performed using ferroelectric memory ([0014]), and additionally teaches the use of tiered memory / “hybrid memory” where the different memories have different access times ([0014]), with Lauster, which also teaches cryptographic encryption / decryption of data using a key stored separate from the data, and additionally teaches retrieving the key before retrieving the data ([0101]). One of ordinary skill in the art would have been motivated to perform such an addition to provide Dropps with the added ability to retrieve a key before retrieving data, as taught by Lauster, for the purpose of increasing computational efficiency by preventing the retrieval of encrypted data until the key for decryption is retrieved which also increases security by preventing the movement of the data.
Regarding claim 3, Dropps, Geetha, and Lauster teach,
The apparatus of claim 2, wherein the cryptographic circuit is to configure a decryption engine of the cryptographic circuit based at least in part on the encryption key. (This feature is inherent in any cryptographic circuit or software that actually performs encryption / decryption once the key is received.) (The applicant’s printed publication at [0032] describes the above feature as: cryptographic/compression circuitry can configure itself to be ready when the encrypted/compressed information is thereafter received from ferroelectric memory 324.)
Regarding claim 10, Dropps, Geetha, and Lauster teach,
A method comprising:
receiving, in a hybrid memory comprising a static random access memory (SRAM) and a ferroelectric memory, a single read request;
in response to the single read request, obtaining an encryption key from the SRAM and obtaining encrypted data from the ferroelectric memory, the encryption key associated with the encrypted data; and
sending the encryption key to a cryptographic circuit
Claim 10 features recited above are rejected using the same basis of arguments used to reject claim 1 above.
sending the encryption key to a cryptographic circuit prior to sending the encrypted data to the cryptographic circuit, to enable configuration of the cryptographic circuit for decryption of the encrypted data in advance of receipt of the encrypted data.
Claim 10 features recited above are rejected using the same basis of arguments used to reject claim 2 above.
Regarding claim 12, Dropps, Geetha, and Lauster teach,
The method of claim 10, further comprising:
Dropps and Geetha teach the following,
receiving the encryption key and the encrypted data in the hybrid memory;
storing the encryption key in the SRAM; and
storing the encrypted data in the ferroelectric memory.
The features of claim 12 recited above are rejected using the same basis of arguments used to reject claim 1 above.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Dropps, in view of Geetha, in view of US 20230336338 to Sagae et al. (hereinafter Sagae).
Regarding claim 4, Dropps and Geetha teach,
The apparatus of claim 1,
Dropps and Geetha fail to explicitly teach that the key storage / retrieval has a lower latency that the data storage / retrieval,
However, Sagae teaches,
wherein the cryptographic circuit is to receive the encryption key with a first latency and receive the encrypted data with a second latency, the second latency greater than the first latency. (fig. 1 teaches cryptographic key storage and cryptography. [0015] teaches receiving a key from a low latency core while the data is received from a non-low latency core.)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Dropps, which teaches a cryptographic circuit that performs encryption / decryption where the data being encrypted / decrypted is stored in an SRAM and the key used in cryptography is stored in ferroelectric memory (Abstract & Col. 10, lines 54-60), with Geetha, which also teaches encryption and decryption (fig. 5 & [0059-61]) being performed using ferroelectric memory ([0014]), and additionally teaches the use of tiered memory / “hybrid memory” where the different memories have different access times ([0014]), with Sagae, which also teaches cryptographic key storage and encryption / decryption and key storage, and additionally teaches receiving a key from a low latency core while the data is received from a non-low latency core ([0015]). One of ordinary skill in the art would have been motivated to perform such an addition to provide Dropps with the explicitly taught ability to receive a key faster than the data being decrypted / encrypted, as taught by Sagae, for the purpose of increasing computational efficiency by preparing the system for encryption / decryption before the data is received by first receiving the key that is needed to perform cryptography.
Claims 5-6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Dropps, in view of Geetha, in view of US 20210066317 to Wu et al. (hereinafter Wu).
Regarding claim 5, Dropps and Geetha teaches,
The apparatus of claim 1, wherein the apparatus comprises a multi-die package comprising:
a first die having the at least one core; and (Dropps, fig. 2, shows different cores, such as processor and cryptographic processing 230 that are separate.) (Wu, further discussed below, includes a first and second semiconductor in [0148-149])
a second die comprising the hybrid memory having the SRAM (Dropps, Col. 11, lines 15-17 teaches all storage and cryptographic processing is performed on the same memory device or the die used for the memory device.) (Geetha, [0014] teaches the tiered / “hybrid” memory)
Dropps fails to teach including SRAM and ferroelectric memory on a single chip / die, However, Wu teaches,
a second die comprising a hybrid memory having the SRAM and the ferroelectric memory.
([0149] teaches a single semi-conductor die that includes logic devices, and memory devices that include SRAM and FeRAM with is ferroelectric memory. See also [0164].)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Dropps, which teaches a cryptographic circuit that performs encryption / decryption where the data being encrypted / decrypted is stored in an SRAM and the key used in cryptography is stored in ferroelectric memory (Abstract & Col. 10, lines 54-60), with Geetha, which also teaches encryption and decryption (fig. 5 & [0059-61]) being performed using ferroelectric memory ([0014]), and additionally teaches the use of tiered memory / “hybrid memory” where the different memories have different access times ([0014]), with Wu, which also teaches logic circuits connected to SRAM and FRAM, and additionally teaches including on a single die / chip / IC a combination of logic circuits, SRAM, and FRAM ([0164]). One of ordinary skill in the art would have been motivated to perform such an addition to provide Dropps with the added ability to include all of the logic and memory circuits required by a logic circuit (e.g., cryptographic) logic circuit on a single chip, as taught by Wu, for the purpose of increasing security by limiting the potential for signals to be intercepted by incorporating all functionality and storage on a single die / chip while also increasing manufacturing efficiency by including computational features on a single chip and utilizing different forms of memory to decrease costs.
Regarding claim 6, Dropps, Geetha, and Wu teach,
The apparatus of claim 5,
wherein the (Col. 11, lines 15-17 teaches all storage and cryptographic processing is performed on the same memory device or the die used for the memory device, where one type of memory and cryptographic processor are located on a single die / chip.)
Wu teaches,
wherein the second die further comprises the ([0149] teaches a single semi-conductor die that includes logic devices, and memory devices that include SRAM and FeRAM with is ferroelectric memory, see also [0164].) (as discussed above and also in the rejection of claim 5, Dropps explicitly teaches cryptographic processing and at least a single type of memory being on the same die (i.e., chip) but does not explicitly teach including two types of memory (SRAM and ferroelectric) and a logic processor on the same chip.)
Regarding claim 18, Wu teaches the following,
A package comprising:
a first die having one or more cores; and
a second die comprising a hybrid memory, the hybrid memory comprising:
The above features of claim 18 are rejected using the same basis of arguments used to reject claim 5 above.
Dropps and Geetha teach the following,
a static random access memory (SRAM); and
a ferroelectric memory,
wherein in response to a single read request the hybrid memory is to provide an encryption key to a cryptographic circuit from SRAM and provide encrypted data to the cryptographic circuit from the ferroelectric memory, the encryption key associated with the encrypted data.
The above features of claim 18 are rejected using the same basis of arguments used to reject claim 1 above.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Dropps, in view of Geetha, in view of Wu, in view of US 20200328192 to Zaman et al. (hereinafter Zaman).
Regarding claim 7, Dropps, Geetha, and Wu teach,
The apparatus of claim 5, wherein the second die further comprises:
Dropps, Geetha, and Wu fail to teach including on a single die / chip: memory, compression logic, and encryption/decryption logic,
However, Zaman teaches,
a compression circuit to compress data into compressed data; and (fig. 5 and [0039] teach die 304 that includes memory 500, encryption / decryption circuit 502, and compression decompression circuit 504. See also fig. 7 and [0047])
a decompression circuit to decompress the compressed data. (See above, figs. 5 and 7, [0039] and [0047])
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Dropps, which teaches a cryptographic circuit that performs encryption / decryption where the data being encrypted / decrypted is stored in an SRAM and the key used in cryptography is stored in ferroelectric memory (Abstract & Col. 10, lines 54-60), with Geetha, which also teaches encryption and decryption (fig. 5 & [0059-61]) being performed using ferroelectric memory ([0014]), and additionally teaches the use of tiered memory / “hybrid memory” where the different memories have different access times ([0014]), with Zaman, which also teaches cryptographic circuits and memories, and additionally teaches a single die / chip that includes memory, cryptographic processing, and data compression processing (fig. 5 & [0039]). One of ordinary skill in the art would have been motivated to perform such an addition to provide Dropps with the added ability to include a compression circuit with the encryption circuit, as taught by Zaman, for the purpose of increasing efficiency in manufacturing of components by placing them on a single chip and/or to increasing security and computational efficiency by keeping connections internal and therefore more difficult to intercept by putting components on a single chip.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Dropps, in view of Geetha, in view of Wu, in view of US 20200350320 to Cheng et al. (hereinafter Cheng), in view of US 20190138893 to Sharma et al. (hereinafter Sharma), in view of US 11087843 (hereinafter Chi).
Regarding claim 8, Dropps, Geetha, and Wu teach,
The apparatus of claim 5, wherein the second die comprises:
Wu teaches,
a substrate; (fig. 18 and [0129] teach substrate 708.)
one or more complementary metal oxide semiconductor (CMOS) layers adapted on the substrate, the one or more CMOS layers comprising the cryptographic circuit; (fig. 18 and [0129] teach the semiconductor devices 710 made of CMOS devices are formed on the substrate 708. [0130] teaches semiconductor devices are logic devices. [0149] teaches SRAM, FRAM, and logic devices.) (Wu teaches logic devices, while Dropps, as discussed above in the rejection of claim 1 teaches a “cryptographic circuit.”)
the ferroelectric memory formed (Wu [0045] teaches that “three-dimensional memory array” is where multiple levels of memory are stacked above one another without substrates between the levels. [0149] teaches SRAM and ferroelectric memory (FeRAM) are in a three dimensional memory array (i.e., stacked on top of one another).)
Dropps, Geetha, and Wu teach fail to teach the different layered configuration of the ferroelectric memory is above the SRAM, which is above the CMOS layer.
However, Cheng teaches,
the SRAM formed above the one or more CMOS layers, wherein the SRAM has a first access latency; and ([0059] teaches the SRAM cells may be formed above the processor. [0048] teaches the processor is made of CMOS. Latency is inherent in memories.)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Dropps, which teaches a cryptographic circuit that performs encryption / decryption where the data being encrypted / decrypted is stored in an SRAM and the key used in cryptography is stored in ferroelectric memory (Abstract & Col. 10, lines 54-60), with Geetha, which also teaches encryption and decryption (fig. 5 & [0059-61]) being performed using ferroelectric memory ([0014]), and additionally teaches the use of tiered memory / “hybrid memory” where the different memories have different access times ([0014]), with Cheng, which also teaches SRAM and logic circuits placed together, and additionally teaches placing SRAM above a processor made of CMOS ([0048-59]). One of ordinary skill in the art would have been motivated to perform such an addition to provide Dropps with the added ability to place SRAM above a processor, as taught by Cheng, for the purpose of increasing efficiency in manufacturing of components by placing them on a single chip and stacking them, and stacking memories above each other to increasing security and computational efficiency by keeping connections internal and therefore more difficult to intercept by putting components on a single chip.
Dropps, Geetha, Wu, and Cheng fail to teach ferroelectric memory formed above the SRAM,
However, Sharma et al. teaches,
the ferroelectric memory formed above the SRAM, (Abstract and [0011] teach a ferroelectric BEOL capacitor that is a memory. Claim 11 teaches the ferroelectric BEOL capacitor, which is memory, located above the SRAM.)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Dropps, which teaches a cryptographic circuit that performs encryption / decryption where the data being encrypted / decrypted is stored in an SRAM and the key used in cryptography is stored in ferroelectric memory (Abstract & Col. 10, lines 54-60), with Geetha, which also teaches encryption and decryption (fig. 5 & [0059-61]) being performed using ferroelectric memory ([0014]), and additionally teaches the use of tiered memory / “hybrid memory” where the different memories have different access times ([0014]), with Sharma, which also teaches SRAM and FRAM memory, and additionally teaches placing the FRAM above the SRAM (Abstract). One of ordinary skill in the art would have been motivated to perform such an addition to provide Dropps with the added ability to place FRAM above an SRAM, as taught by Sharma, for the purpose of increasing efficiency in manufacturing of components by placing them on a single chip and stacking them, and stacking memories above each other to increasing security and computational efficiency by keeping connections internal and therefore more difficult to intercept by putting components on a single chip.
Dropps, Geetha, Wu, Cheng, and Chia fail to teach latency properties of SRAM vs ferroelectric (FRAM),
However, Chia teaches,
… , wherein the ferroelectric memory has a second access latency greater than the first access latency. (Col 11, lines 15-25 teaches that FRAM has a higher latency than SRAM.)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Dropps, which teaches a cryptographic circuit that performs encryption / decryption where the data being encrypted / decrypted is stored in an SRAM and the key used in cryptography is stored in ferroelectric memory (Abstract & Col. 10, lines 54-60), with Geetha, which also teaches encryption and decryption (fig. 5 & [0059-61]) being performed using ferroelectric memory ([0014]), and additionally teaches the use of tiered memory / “hybrid memory” where the different memories have different access times ([0014]), with Chia, which also teaches FRAM and SRAM memories, and additionally teaches that FRAM has a higher latency than SRAM (Col. 11). One of ordinary skill in the art would have been motivated to perform such an addition to provide Dropps with the added ability to understand that different memories have different properties such as latency, as taught by Chia, for the purpose of increasing efficiency in manufacturing of components by placing them on a single chip and selecting the appropriate components due to their properties in an effort to balance trade-offs while increasing security and computational efficiency by keeping connections internal and therefore more difficult to intercept by putting components on a single chip.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Dropps, in view of Geetha, in view of US 20230100106 to Dewan et al. (hereinafter Dewan).
Regarding claim 9, Dropps and Geetha teaches,
The apparatus of claim 1,
Dropps and Geetha fail to explicitly teach a memory sending control information to a cryptographic circuit,
However, Dewan teaches the following,
wherein the SRAM is further to send control information to the cryptographic circuit to indicate that the cryptographic circuit is to be enabled for decryption of the encrypted data. ([0171] teaches access control data being sent from a memory to a cryptographic circuit, where the access control data in memory.)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Dropps, which teaches a cryptographic circuit that performs encryption / decryption where the data being encrypted / decrypted is stored in an SRAM and the key used in cryptography is stored in ferroelectric memory (Abstract & Col. 10, lines 54-60), with Geetha, which also teaches encryption and decryption (fig. 5 & [0059-61]) being performed using ferroelectric memory ([0014]), and additionally teaches the use of tiered memory / “hybrid memory” where the different memories have different access times ([0014]), with Dewan, which also teaches a cryptographic circuit that processes information, and additionally teaches that access control data is utilized to determine if encryption / decryption should occur ([0171]). One of ordinary skill in the art would have been motivated to perform such an addition to provide Dropps with the added ability to use access control data in providing the ability to provide cryptographic processes, as taught by Dewan, for the purpose of increasing security by controlling access to cryptography.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Dropps, in view of Geetha, in view of Lauster, in view of Sagae.
Regarding claim 11, Dropps, Geetha, and Lauster teach,
The method of claim 10, further comprising
Sagae teaches the following,
sending the encryption key to the cryptographic circuit with a first latency and sending the encrypted data to the cryptographic circuit with a second latency, the second latency greater than the first latency.
The features of claim 11 recited above are rejected using the same basis of arguments used to reject claim 4 above.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Dropps, in view of Geetha, in view of Lauster, in view of US 20150261975 to Brumley et al. (hereinafter Brumley).
Regarding claim 13, Dropps, Geetha, and Lauster teach,
The method of claim 12,
Dropps and Geetha0 teach,
further comprising storing (The rejection of claim 1 details the teachings of Dropps and Geetha regarding the SRAM and the ferroelectric memory. See figs. 2-4 of Dropps.)
Dropps, Geetha, and Lauster fail to teach storing an index in an SRAM,
However, Brumley teaches,
further comprising storing a mapping to associate the encryption key stored in the SRAM with the encrypted data stored in the ferroelectric memory. ([0036] teaches storing a key and index in same SRAM on-chip for enhanced security.)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Dropps, which teaches a cryptographic circuit that performs encryption / decryption where the data being encrypted / decrypted is stored in an SRAM and the key used in cryptography is stored in ferroelectric memory (Abstract & Col. 10, lines 54-60), with Geetha, which also teaches encryption and decryption (fig. 5 & [0059-61]) being performed using ferroelectric memory ([0014]), and additionally teaches the use of tiered memory / “hybrid memory” where the different memories have different access times ([0014]), with Brumley, which also teaches key storage and cryptography, and additionally teaches storing the key and index together in an SRAM for increased on chip security ([0036]). One of ordinary skill in the art would have been motivated to perform such an addition to provide Dropps with the added ability to store the key and index on the same chip in an SRAM, as taught by Brumley, for the purpose of increasing security by storing the index on the secure chip.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Dropps, in view of Geetha, in view of Lauster, in view of US 20040049630 to Stark (hereinafter Stark).
Regarding claim 14, Dropps and Lauster teach,
The method of claim 10,
Dropps, Geetha, and Lauster fail to teach,
However, Stark teaches,
further comprising storing the encryption key in a first column of the SRAM, the first column storing a plurality of encryption keys each associated with different encrypted data stored in the ferroelectric memory. ([0060] teaches storing a key in a first column.) (Dropps teaches storing the key in an SRAM.)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Dropps, which teaches a cryptographic circuit that performs encryption / decryption where the data being encrypted / decrypted is stored in an SRAM and the key used in cryptography is stored in ferroelectric memory (Abstract & Col. 10, lines 54-60), with Geetha, which also teaches encryption and decryption (fig. 5 & [0059-61]) being performed using ferroelectric memory ([0014]), and additionally teaches the use of tiered memory / “hybrid memory” where the different memories have different access times ([0014]), with Stark, which also teaches key storage and cryptography, and additionally teaches storing a key in a first column of a memory ([0060]). One of ordinary skill in the art would have been motivated to perform such an addition to provide Dropps with the added ability to store a key in a first column, as taught by Stark, for the purpose of increasing by including the key in a location that is secure and easily found.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Dropps, in view of Geetha, in view of Lauster, in view of Dewan.
Regarding claim 15, Dropps, Geetha, and Lauster teach,
The method of claim 10,
Dewan teaches,
wherein sending the encryption key to the cryptographic circuit further comprises sending control information with the encryption key to indicate that the cryptographic circuit is to be enabled for the decryption of the encrypted data.
The above features of claim 15 are rejected using the same basis of arguments used to reject claim 9 above.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Dropps, in view of Geetha, in view of Lauster, in view of Dewan, in view of US 20210064450 to Nugent et al. (hereinafter Nugent).
Regarding claim 16, Dropps, Geetha, and Lauster teach,
The method of claim 10, further comprising:
Dewan teaches,
receiving, in the hybrid memory, a second read request;
in response to the second read request, obtaining second control information from the SRAM, the second control information
sending the second control information to the cryptographic circuit
The above features of claim 16 are rejected using the same basis of arguments used to reject claim 9 above.
Dropps, Geetha, Lauster, and Dewan fail to teach,
However, Nugent teaches,
in response to the second read request, obtaining second control information ([0025] teaches determining that content is neither encoded nor encrypted and, therefore, post processing, decoding/decryption, is unnecessary.)
sending the second control information to the cryptographic circuit to indicate that the second data is unencrypted. ([0025] teaches determining that content is neither encoded nor encrypted and, therefore, post processing, decoding/decryption, is unnecessary.)
Before the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Dropps, which teaches a cryptographic circuit that performs encryption / decryption where the data being encrypted / decrypted is stored in an SRAM and the key used in cryptography is stored in ferroelectric memory (Abstract & Col. 10, lines 54-60), with Geetha, which also teaches encryption and decryption (fig. 5 & [0059-61]) being performed using ferroelectric memory ([0014]), and additionally teaches the use of tiered memory / “hybrid memory” where the different memories have different access times ([0014]), with Nugent, which also teaches encryption and decryption, and additionally teaches that during a read request, the system determines that the data has already been decrypted ([0025]). One of ordinary skill in the art would have been motivated to perform such an addition to provide Dropps with the added ability to determine that data does not need to be decrypted, as taught by Nugent, for the purpose of increasing computational efficiency while maintaining security.
Regarding claim 17, Dropps, Geetha, Lauster, Dewan, and Nugent teach,
The method of claim 16, further comprising, based at least in part on the second control information, performing at least one of:
powering down the cryptographic circuit; and
sending the second data directly from the ferroelectric memory to a requester without sending the second data to the cryptographic circuit. (The examiner takes official notice that it is well known in the art to turn off components / circuitry when the component is not needed / required. Nugent teaches that the data is not processed for decryption, but does not interrupt the process otherwise. )
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Dropps, in view of Geetha, in view of Wu, in view of Sagae.
Regarding claim 19, Dropps, Geetha, and Wu teach,
The package of claim 18,
Sagae teaches the following,
further comprising the cryptographic circuit, wherein the cryptographic circuit is to receive the encryption key with a first latency and receive the encrypted data with a second latency, the second latency greater than the first latency.
The above features of claim 19 are rejected using the same basis of arguments used to reject claim 4 above.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Dropps, in view of Geetha in view of Wu, in view of Zaman.
Regarding claim 20, Dropps, Geetha, and Wu teach,
The package of claim 18,
Zaman teaches,
further comprising a compression circuit, wherein the SRAM is further to provide compression control information to the compression circuit, the compression circuit to configure a decompression circuit of the compression circuit based at least in part on the compression control information, the compression control information associated with the encrypted data, wherein the encrypted data is compressed.
The above features of claim 20 are rejected using the same basis of arguments used to reject claim 7 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN WILLIAM AVERY whose telephone number is (571)272-3942. The examiner can normally be reached on 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Farid Homayounmehr can be reached on (571)272-3739.
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/B.W.A./
/FARID HOMAYOUNMEHR/Supervisory Patent Examiner, Art Unit 2495