DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 11 and 17.
Pending: 1-20.
Withdrawn: 10 and 13.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE INCLUDING BARRIER STRUCTURE AND CEILING LAYER OVER AN AVTIVE DEVICE.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 17, 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Herrault et al., US patent 9508652 B1.
Re: Independent Claim 17, Herrault discloses an active device (20, fig. 1), a passive device (44, fig. 1), and a pad structure (62, 64, 82 and 84, fig. 7A) formed over a substrate (12, fig. 1);
a barrier structure (100, fig. 7B) surrounding the active device (20, fig. 1) in top view, wherein the barrier structure (100, fig. 7B) has a thickness greater than a height of the passive device (44, fig. 1) such that it fills a region surrounding the passive device (44, fig. 1);
a ceiling layer (60, fig. 7B) formed directly above the active device (20, fig. 1) and over the barrier structure (100, fig. 7B);
a via structure (16 and 17, fig. 1) comprising a metal stack (14, 16 and 17, fig. 1) formed in the substrate (12, fig. 1),
wherein the metal stack (14, 16 and 17, fig. 1) is conformally formed under the substrate (12, fig. 1).
Re: Claim 18, Herrault disclose(s) all the limitations of claim 17 on which this claim depends. Herrault further discloses: wherein the barrier structure (100, fig. 7B) covers the passive device (44, fig. 1), and the ceiling layer (60, fig. 7B) has an opening (see annotated fig. 7B below) exposing the barrier structure (100, fig. 7B) on the passive device (44, fig. 1) in top view.
Re: Claim 20, Herrault disclose(s) all the limitations of claim 17 on which this claim depends. Herrault further discloses: wherein the pad structure (62, 64, 82 and 84, fig. 7A) is partially covered by the barrier structure (100, fig. 7B).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8, 9, 11, 12, 14-16 and 19 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Herrault et al., US patent 9508652 B1; in view of Kapusta et al., US Patent 8276268 B2.
Re: Independent Claim 1, Herrault discloses an active device (20, fig. 1) formed over a substrate (12, fig. 1);
a passive device (44, fig. 1) formed over the substrate (12, fig. 1);
a barrier structure (100, fig. 7B) surrounding the active device (20, fig. 1) in top view, wherein a thickness of the barrier structure (100, fig. 7B) is greater than a height of the passive device (44, fig. 1) to fill a space around the passive device (44, fig. 1); and
a ceiling layer (60, fig. 7B) suspended on the barrier structure (100, fig. 7B) over the active device (20, fig. 1),
wherein the ceiling layer (60, fig. 7B) has an opening (see annotated fig. 7B below) exposing the barrier structure (100, fig. 7B) in top view.
Herrault is silent regarding: a passivation layer covering the active device (20, fig. 1) and the passive device (44, fig. 1).
Kapusta teaches as shown in figure 4 a layer of passivation 26 covering an active device and the passive device 16.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a passivation layer to cover the active and passive device since this can protect any external damage during processing.
Re: Claim 2, Herrault and Kapusta discloses all the limitations of claim 1 on which this claim depends. Herrault further discloses: wherein the barrier structure (100, fig. 7B) covers the passive device (44, fig. 1), and the barrier structure (100, fig. 7B) over the passive device (44, fig. 1) 1s exposed in the opening (see annotated fig. 7B below) of the ceiling layer (60, fig. 7B).
Re: Claim 3, Herrault and Kapusta discloses all the limitations of claim 1 on which this claim depends. Herrault further discloses: a pad structure (62, 64, 82 and 84, fig. 7A) formed over the substrate (12, fig. 1),
wherein the pad structure (62, 64, 82 and 84, fig. 7A) is exposed from the barrier structure (100, fig. 7B) and the ceiling layer (60, fig. 7B).
Re: Claim 4, Herrault and Kapusta discloses all the limitations of claim 1 on which this claim depends. Herrault further discloses: wherein the passive device (44, fig. 1) comprises a capacitor.
Re: Claim 5, Herrault and Kapusta discloses all the limitations of claim 1 on which this claim depends. Herrault is silent regarding: wherein a pattern of the passivation layer is defined by a pattern of the barrier structure (100, fig. 7B) and a pattern of the ceiling layer (60, fig. 7B).
Kapusta teaches as shown in figure 4 a layer of passivation 26 covering an active device and the passive device 16.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a passivation layer to cover the active and passive device since this can protect any external damage during processing.
Re: Claim 6, Herrault and Kapusta discloses all the limitations of claim 1 on which this claim depends. Herrault further discloses: a metal layer (14 and 90, fig. 5-6) stack formed under the substrate (12, fig. 1) protruding in the substrate (12, fig. 1).
Re: Claim 8, Herrault and Kapusta discloses all the limitations of claim 6 on which this claim depends. Herrault is silent regarding: wherein a ratio of a thickness of the metal layer (14 and 90, fig. 5-6) stack to a thickness of the barrier structure (100, fig. 7B) is in a range of about 2 to about 20.
However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the thickness metal and barrier layer to have a range of about 2:20 ratio such modification would have only involved a mere change in working range which involves only routine skill in the art one would have been motivated to make such modification to make those layer to have a thinner metal stack layer thickness to achieve the predictable result of miniaturization the display device thereby improve the high-density integration.
Re: Claim 9, Herrault and Kapusta discloses all the limitations of claim 1 on which this claim depends. Herrault is silent regarding: wherein a ratio of an area of the ceiling layer (60, fig. 7B) to an area of the semiconductor chip is in a range of about 2 to about 50.
However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the thickness ceiling layer to area of the chip in a range of about 2:50 ratio such modification would have only involved a mere change in working range which involves only routine skill in the art one would have been motivated to make such modification to make those layer to have a thinner ceiling layer thickness to achieve the predictable result of miniaturization the display device thereby improve the high-density integration.
Re: Independent Claim 11, Herrault discloses an active device (20, fig. 1) formed over a substrate (12, fig. 1);
a passive device (44, fig. 1) formed over the substrate (12, fig. 1) beside the active device (20, fig. 1);
a barrier structure (100, fig. 7B) surrounding the active device (20, fig. 1) and covering the passive device (44, fig. 1) in top view, wherein a thickness of the barrier structure (100, fig. 7B) exceeds a height of the passive device (44, fig. 1), thereby occupying a space adjacent to the passive device (44, fig. 1); and
a ceiling layer (60, fig. 7B) formed over the active device (20, fig. 1) and the barrier structure (100, fig. 7B).
Herrault is silent regarding: a passivation layer formed over the active device (20, fig. 1) and the passive device (44, fig. 1) and wherein a ratio of an area of the ceiling layer (60, fig. 7B) to an area of the semiconductor chip is in a range of about 2 to about 50.
However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the thickness ceiling layer to area of the chip in a range of about 2:50 ratio such modification would have only involved a mere change in working range which involves only routine skill in the art one would have been motivated to make such modification to make those layer to have a thinner ceiling layer thickness to achieve the predictable result of miniaturization the display device thereby improve the high-density integration.
Kapusta teaches as shown in figure 4 a layer of passivation 26 covering an active device and the passive device 16.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a passivation layer to cover the active and passive device since this can protect any external damage during processing.
Re: Claim 12, Herrault and Kapusta discloses all the limitations of claim 11 on which this claim depends. Herrault is silent regarding: wherein the projection of the passivation layer on the substrate (12, fig. 1) overlaps the projection of the barrier structure (100, fig. 7B) and the ceiling layer (60, fig. 7B) on the substrate (12, fig. 1) from a top view.
Kapusta teaches as shown in figure 4 a layer of passivation 26 covering an active device and the passive device 16.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a passivation layer to cover the active and passive device since this can protect any external damage during processing.
Re: Claim 14, Herrault and Kapusta discloses all the limitations of claim 11 on which this claim depends. Herrault is silent regarding: wherein a ratio of an area of the ceiling layer (60, fig. 7B) to an area of the barrier structure (100, fig. 7B) is in a range of about 2 to about 20.
However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the thickness ceiling layer to area of the chip in a range of about 2:20 ratio such modification would have only involved a mere change in working range which involves only routine skill in the art one would have been motivated to make such modification to make those layer to have a thinner ceiling layer thickness to achieve the predictable result of miniaturization the display device thereby improve the high-density integration.
Re: Claim 15, Herrault and Kapusta discloses all the limitations of claim 11 on which this claim depends. Herrault further discloses: a metal layer (14 and 90, fig. 5-6) stack formed under the substrate (12, fig. 1),
wherein the metal layer (14 and 90, fig. 5-6) stack is in direct contact with the active device (20, fig. 1).
Re: Claim 16, Herrault and Kapusta discloses all the limitations of claim 11 on which this claim depends. Herrault further discloses: wherein a top surface of the barrier structure (100, fig. 7B) covering the passive device (44, fig. 1) is partially exposed from the ceiling layer (60, fig. 7B).
Re: Claim 19, Herrault and Kapusta discloses all the limitations of claim 11 on which this claim depends. Herrault is silent regarding: a passivation layer covered by the barrier structure (100, fig. 7B) and the ceiling layer (60, fig. 7B),
wherein the passivation layer is separated from the ceiling layer (60, fig. 7B).
Kapusta teaches as shown in figure 4 a layer of passivation 26 covering an active device and the passive device 16.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modified Kapusta’s passivation layer into Herrault device thereby cover the active and passive device since this can protect any damage during processing wherein Kapusta’s passivation layer would be covered by layers 100 and 60 as shown in figure 7B of Herrault.
Claim(s) 7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Herrault et al., US patent 9508652 B1; in view of Kapusta et al., US Patent 8276268 B2; further in view of Shih US PG pub. 20170018537 A1.
Re: Claim 7, Herrault and Kapusta discloses all the limitations of claim 6 on which this claim depends. Herrault is silent regarding: wherein the metal layer (14 and 90, fig. 5-6) stack comprises a TiW layer sandwiched between metal layers (14 and 90, fig. 5-6).
Shih disclose metal stack layer can made of material such as TiW that is sandwiched between metal layers sandwiched between metal layers (¶0047).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include TiW material stacking onto electrode since Titanium tungsten can exhibit excellent compressive strength prevent damage to a electrode or circuitry.
Annotated figure 7B of Herrault et al., US patent 9508652 B1.
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Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Chen et al., US PG pub. 20210202329 A1”) Discloses a semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.
* (“Ramachandran et al., US PG pub. 20150250058 A1”) discloses an integrated interposer between a first component and a second component includes a substrate. The substrate may have thermal and/or mechanical properties with values lying between the thermal and/or mechanical properties of the first component and the second component. Active devices are disposed on a first surface of the substrate. A contact layer is coupled to the active devices and configured to couple at least the first component and a third component to the integrated interposer. At least one through via(s) is coupled to the contact layer and extends through the substrate to a second surface of the substrate. An interconnect layer is disposed on the second surface of the substrate and coupled to the at least one through via(s). The interconnect layer is configured to couple the second component to the integrated interposer.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-9,11-12,14-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898