DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 08, 2025 has been entered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11935700 in view of Hamada et al. [U.S. Patent No. 11227715] and Okumura et al. [JP 2009038187 A].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito et al. [U.S. Patent No. 11935700] in view of Hamada et al. [U.S. Patent No. 11227715 B2] and Okumura et al. [JP 2009038187 A] (provided in IDS, translation provided by the Examiner).
Regarding claim 1, Saito discloses a laminated electronic component (e.g., 1, Fig. 1, column 3, lines 32-36) comprising:
an element body (e.g., 2, Fig. 1) formed by laminating an insulating layer (e.g., 4, column 3, lines 37-38, column 4, lines 12-15, Fig. 1-2) and having a bottom surface (e.g., 2B of body 2 of component 1, Fig. 1) used as a mounting surface, and side surfaces (e.g., side surfaces 2C, 2D, 2E and 2F, Fig. 1) configured to extend to intersect the bottom surface 2B; and
a bottom surface electrode (e.g., 3, column 4, lines 1-5, Fig. 2) formed on the bottom surface 2B of the element body 2,
wherein the bottom surface electrode 3 includes a first electrode layer (e.g., 11, column 4, lines 43-59, see Fig. 2) and a second electrode layer (e.g., 12, see Fig. 2) such that the first electrode layer 11 is formed on an exterior surface (e.g., 2B, see Fig. 2 ) of the element body 2,
the first electrode layer 11 is laminated to cover the second electrode layer 12 entirely,
the element body 2 comprises an overcoat layer (e.g., 5, column 4, lines 26-28, Fig. 2) as an outermost layer that defines the bottom surface 2B,
an edge portion (e.g., 22, column 4, lines 66-67) of the second electrode layer 12 is covered with the overcoat layer 5,
the overcoat layer 5 is interposed between the edge portion 22 of the second electrode layer 12 and the first electrode layer 11, and
the first electrode layer 11 is connected to a portion of the second electrode layer 12 that is exposed at the bottom surface 2B.
Saito discloses the instant claimed invention discussed above except for the first electrode layer is a resin electrode that has a stretched portion configured to extend to the side surface.
Hamada discloses first electrode layer is a resin electrode (e.g., surface electrode 21 is a resin-base conductor, column 4, lines 65-67), and has a stretched portion configured to extend to the side surface (e.g., plating P of outer electrode 20 which comprises surface electrode 21 stretches on side surface of body 10, see Fig. 17).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first electrode layer is a resin electrode that has a stretched portion configured to extend to the side surface of the body as taught by Hamada to the body of Saito to provide the electronic component with side electrode for soldering to ensure a reliable mechanical and electrical contact to the circuit board.
Saito discloses the instant claimed invention discussed above except for a width dimension of the stretched portion is smaller than a width dimension of the first electrode layer on the bottom surface.
Okumura discloses electrode layer (e.g.,41, 42, 43, 44, of component 10, page 5 of translation provided by Examiner, Fig. 1) has a width dimension of the stretched portion (e.g., width w2 of stretch portion 43b of outer electrode 43, on side surface 32 of component 10 as shown in Figure 1) smaller than a width dimension of electrode layer on the bottom surface (e.g., width w1 of portion 43a or 43c, on mounting surface 21, 22 of component 10 as shown in Figure 1, see page 5 of translation).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the width dimension of the stretched portion of the outer electrode smaller than a width dimension of the outer electrode layer on the bottom surface as taught by Okumura to the outer electrodes of Saito to provide the component with electrode structures that can prevent the “rising phenomenon” in solder reflow process and keep the mounting alignment proper.
Regarding claim 2, Okumura discloses the stretched portion (e.g., stretch portion 43b of outer electrode 43, on side surface 32 of component 10 as shown in Figure 1) is disposed on the side surface (e.g., side surface 32, page 5, Fig. 1) at a position separated from an upper surface (e.g., upper surface 22 of component 10, page 5 of translation, Fig. 1) facing the bottom surface (e.g., bottom surface 21, Fig. 1).
Response to Argument
Applicant's arguments with respect to claims 1-2 have been considered but are moot in view of the new ground(s) of rejection.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11935700 to Saito in view of Hamada et al. [U.S. Patent No. 11227715] and Okumura et al. [JP 2009038187 A].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please refer to form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSELITO SASIS BAISA whose telephone number is (571)272-7132. The examiner can normally be reached M-F, 8AM to 4PM.
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/J.S.B/ Examiner, Art Unit 2837
/SHAWKI S ISMAIL/ Supervisory Patent Examiner, Art Unit 2837