CTFR 17/708,849 CTFR 89881 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This action is in response to the amendment filed on 03/10/2026. Claim Objections 07-29-01 AIA Claim s 5, and 17 are objected to because of the following informalities: Regarding claim 5 , in line 11, “the controller output” appears that it should read as “the control output”. Regarding claim 17 , in line 2, “are part on a single integrated circuit” appears that it should read “are part of a single integrated circuit” . Appropriate correction is required. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 2, 3, 7, 10, 11, 12, 14, 15, 16, and 18-22 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Chen (US Patent Application Publication US 2010/0244788 A1). Regarding claim 1 , Chen discloses (see Fig. 5A and Fig. 5B) an apparatus, comprising: a switch (high-side switch M3) coupled between a capacitor terminal (a terminal of energy storage capacitor CBUS) and a power terminal (output terminal VOUT), the switch having a switch control terminal (gate of M3); and a controller (PWM 504 together with detector 402) having a first control input (the sensing input of detector 402), a second control input (the VBUS sensing input at comparator 528), and a control output (the output of Logic & Driver 508), the first control input coupled to the power terminal (see [0052] " the output voltage VOUT can be sensed directly via detector 402 "), the second control input coupled to the capacitor terminal (VBUS of CBUS is sensed at comparator 528), the control output coupled to the switch control terminal (Logic & Driver 508 drives the gate of M3); the controller configurable to, based on a state of the first control input indicative of whether a transient event occurs at the power terminal (the DISCH signal goes high when VOUT is about 2% below its regulation point, indicating a heavy/transient load condition, see [0052]) and a state of the second control input indicating a condition at the capacitor terminal (VBUS relative to threshold VBUS,MAX, see [0052]–[0053]), control the switch to selectively transfer charge from the capacitor terminal to the power terminal (discharging CBUS to VOUT under heavy load) or from the power terminal to the capacitor terminal (charging CBUS when spare input power is available, see [0052]) . Regarding claim 2 , Chen discloses (see Fig. 5A and Fig. 5B) wherein the controller is configurable to: receive a load signal at the first control input (the output-voltage condition sensed by detector 402), the load signal indicating a load condition; select a charge mode responsive to the load signal indicating a steady-state load condition to transfer charge from the power terminal to the capacitor terminal (when VOUT is at its regulation point, CBUS is charged from the output side, see [0050] " charge up the CBUS when the load current is light "); select a transient response mode responsive to the load signal indicating a transient load condition to transfer charge from the capacitor terminal to the power terminal (CBUS is discharged to the output when regulator 302 cannot supply the heavy load, see [0050]); and provide a control signal at the control output responsive to the selected mode (providing control signals to M3 and M4 responsive to signal “RUN”). Regarding claim 3 , Chen discloses (see Fig. 5A and Fig. 5B) wherein the controller is configurable to: receive a sense signal at the second control input, the sense signal indicating an amount of charge stored in a capacitor coupled to the capacitor terminal (the bus voltage VBUS of CBUS is sensed at comparator 528, VBUS being indicative of the charge stored on CBUS); select the charge mode responsive to the load signal indicating the steady-state load condition and the sense signal being less than a threshold (charging proceeds while VBUS is below VBUS,MAX, see [0052]); select an idle mode to disconnect the capacitor from the power terminal responsive to the load signal indicating the steady-state load condition and the sense signal being equal to or greater than the threshold (the charging operation stops and M3, M4 are turned off when VBUS reaches the preset maximum level, see [0053] and Fig. 8 step 814 " Stop charging "); and select the transient response mode responsive to the load signal indicating the transient load condition (see step 808). Regarding claim 7 , Chen discloses (see Fig. 5A and Fig. 5B) wherein the switch is a first switch (M3), the switch control terminal is a first switch control terminal (gate of M3), the control output is a first control output, the controller has a second control output, and the apparatus further comprises an inductor terminal (the switching node between M3, M4 and inductor L2) and a second switch (low-side switch M4) having a second switch control terminal (gate of M4) coupled to the second control output (Logic & Driver 508), the inductor terminal being coupled to the power terminal and the first switch (L2 couples the switching node to VOUT, and M3 couples the switching node to CBUS), and the second switch coupled between the inductor terminal and a ground (M4 is coupled between the switching node and ground), see Fig. 5A. Regarding claim 10 , Chen discloses (see Fig. 5A and Fig. 5B) wherein the controller is configurable to operate the first switch (M3) and the second switch (M4) to perform ripple attenuation at the power terminal (M3 and M4 are operated to deliver charge to, and absorb charge from, CBUS at the output node VOUT so as to maintain regulation and attenuate the variation/ripple of the output voltage, see [0050], [0052]). Regarding claim 11 , Chen discloses (see Fig. 5A and Fig. 5B) a system, comprising: a power stage (regulator 302 comprising switches M1, M2 and inductor L1) having a power stage input (VIN), a power stage output (VOUT) and switches (M1, M2); a power stage controller (PWM 404) coupled to control terminals of the switches; and an auxiliary converter (regulator 502) having a power terminal (VOUT) coupled to the power stage output, the auxiliary converter including a switch (M3) coupled between a capacitor terminal (a terminal of CBUS) and the power terminal, the switch having a switch control terminal (gate of M3); and an auxiliary converter controller (PWM 504 with detector 402) having a first control input (detector 402), a second control input (VBUS sensing), and a control output (Logic & Driver 508), the first control input coupled to the power terminal (detector 402 senses VOUT), the second control input coupled to the capacitor terminal (VBUS sensing of CBUS), the control output coupled to the switch control terminal, and the auxiliary converter controller configurable to, based on a state of the first control input indicative of whether a transient event occurs at the power terminal (DISCH high when VOUT drops, see [0052]) and a state of the second control input indicating a condition at the capacitor terminal (VBUS versus VBUS,MAX), control the switch to selectively transfer charge between the capacitor terminal and the power terminal or disconnect the power terminal from the capacitor terminal (charging or discharging CBUS, or stopping/idle with M3, M4 off, see [0050], [0052]–[0053] and Fig. 8). Regarding claim 12 , Chen discloses (see Fig. 5A and Fig. 5B) wherein the switch is a first switch (M3), the switch control terminal is a first switch control terminal, the control output is a first control output, the auxiliary converter controller has a second control output, and the auxiliary converter includes a second switch (M4) having a second switch control terminal coupled to the second control output (gate of M4), and an inductor terminal (the switching node of M3/M4/L2) coupled to the power terminal and the first switch, the second switch coupled between the inductor terminal and ground (M4 is coupled between the switching node of M3 /M4/L2 and ground). Regarding claim 14 , Chen discloses (see Fig. 5A and Fig. 5B) wherein the auxiliary converter controller is configurable to retain charge on a capacitor coupled to the capacitor terminal responsive to detecting, based on the state of the second control input, that the charge on the capacitor reaches a threshold (when VBUS reaches the preset maximum VBUS,MAX, charging stops and the charge on CBUS is retained, see [0053] and Fig. 8 step 814). Regarding claim 15 , Chen discloses (see Fig. 5A and Fig. 5B) wherein the auxiliary converter controller is configurable to alternate between a charge mode and an idle mode during a steady-state load condition responsive to a sense signal at the second control input that indicates a voltage on a capacitor coupled to the capacitor terminal or an amount of charge stored in the capacitor (during light/steady-state load, CBUS is charged while VBUS is below VBUS,MAX and charging stops (idle) when VBUS reaches VBUS,MAX, the controller thereby alternating between charging and stopping based on sensed VBUS, see [0052]–[0053] and Fig. 8 steps 810–814). Regarding claim 16 , Chen discloses (see Fig. 5A and Fig. 5B) wherein the auxiliary converter controller is configurable to operate the first switch and the second switch to perform voltage ripple attenuation at the power stage output (M3 and M4 are operated to deliver/absorb charge at VOUT so as to maintain regulation and attenuate the variation/ripple of the output voltage, see [0050], [0052]). Regarding claim 18 , Chen discloses (see Fig. 5A and Fig. 5B) a method comprising: receiving, at a first input (detector 402 coupled to VOUT of regulator 302) coupled to a power stage output (output of VOUT) of a first converter (first converter comprising M1, M2, L1, Cout), a first signal indicating a load condition at the power stage output of the first converter (the sensed VOUT/DISCH condition, see [0052]); receiving, at a second input (the VBUS sensing input of regulator 502 coupled to CBUS) coupled to a capacitor (CBUS) of a second converter (second converter comprising M3, M4, L2), a second signal indicating an amount of charge stored in the capacitor of the second converter (VBUS); responsive to the first signal indicating a steady-state load condition, and the second signal indicating that the amount of charge in the capacitor is below a threshold, transferring charge from the power stage output to the capacitor (charging CBUS when VOUT is regulated and VBUS is below VBUS,MAX, see [0052] and Fig. 8 step 812); and responsive to the first signal indicating a transient load condition, transferring charge from the capacitor to the power stage output (discharging CBUS to VOUT under heavy load, see [0050], [0052] and Fig. 8 step 808). Regarding claim 19 , Chen discloses (see Fig. 5A and Fig. 5B) further comprising controlling charging and discharging of the capacitor based on control signals of the first converter (the charging and discharging of CBUS occurs based on FB, CLK, and SLP which are control signals of first converter comprising M1, M2, L1, Cout and 404). Regarding claim 20 , Chen discloses (see Fig. 5A and Fig. 5B) further comprising performing active buffering at the power stage output to attenuate voltage ripple at the power stage output (the auxiliary regulator 502 actively buffers energy by charging and discharging CBUS at VOUT to maintain regulation and attenuate the variation/ripple of the output voltage, see [0050], [0052]). Regarding claim 21 , Chen discloses (see Fig. 5A and Fig. 5B) further comprising a power converter (the first regulator 302 comprising M1, M2 and L1) coupled between the power terminal (VOUT) and a power input (VIN, see Fig. 5A and [0050]). Regarding claim 22 , Chen discloses further comprising, responsive to the first signal indicating the steady-state load condition and the second signal indicating that the amount of charge in the capacitor is at or above the threshold, disconnecting the capacitor from the power stage output (when VOUT is regulated (steady-state) and VBUS is at or above VBUS,MAX, charging is stopped and CBUS is disconnected with M3 and M4 off, see [0053] and Fig. 8 step 814 " Stop charging ") . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Shioya (US Patent US 6,023,178). Regarding claim 17 , Chen does not disclose wherein the auxiliary converter controller and the power stage controller are part of a single integrated circuit. However, Shioya teaches a pulse width control IC circuit in which a main converter control section, an output MOSFET, and an auxiliary converter control section are provided together (see Abstract and Fig. 1 of Shioya " on a single chip "; see also claim 1 of Shioya). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Chen wherein the auxiliary converter controller and the power stage controller are part of a single integrated circuit, as taught by Shioya, because it can reduce cost, increase packaging density, and improve reliability of the power supply unit . Allowable Subject Matter Claims 4, 5, 6, 8, 9, and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 4 , none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “ the threshold is a first threshold, and the controller is configurable to transition from the idle mode to the charge mode responsive to the load signal indicating the steady-state load condition and the sense signal being less than a second threshold. ” Regarding claim 5 , none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “ the sense signal representing a time interval of charging of a capacitor coupled to the capacitor terminal; select the charge mode responsive to the load signal indicating the steady-state load condition and a duration of the time interval being less than a threshold;… ” Regarding claim 6 , the claim is objected to due to its dependency on claim 5. Regarding claim 8 , none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “ to charge the capacitor responsive to the load signal indicating the steady-state load condition and until the sense signal indicates a first target voltage level at the capacitor is reached, the first target voltage level being equal to a second target voltage at the power terminal plus a surplus voltage. ” Regarding claim 9 , the claim is objected to due to its dependency on claim 8. Regarding claim 13 , none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “ to charge a capacitor coupled to the capacitor terminal during a steady-state load condition up to a first target voltage, the first target voltage being equal to a second target voltage plus a surplus voltage. ” Response to Arguments Applicant’s arguments with respect to claims 1, 11, and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838 /JYE-JUNE LEE/Examiner, Art Unit 2838 Application/Control Number: 17/708,849 Page 2 Art Unit: 2838 Application/Control Number: 17/708,849 Page 4 Art Unit: 2838 Application/Control Number: 17/708,849 Page 5 Art Unit: 2838 Application/Control Number: 17/708,849 Page 6 Art Unit: 2838 Application/Control Number: 17/708,849 Page 7 Art Unit: 2838 Application/Control Number: 17/708,849 Page 8 Art Unit: 2838 Application/Control Number: 17/708,849 Page 9 Art Unit: 2838 Application/Control Number: 17/708,849 Page 10 Art Unit: 2838 Application/Control Number: 17/708,849 Page 11 Art Unit: 2838 Application/Control Number: 17/708,849 Page 12 Art Unit: 2838
Prosecution Insights