DETAILED ACTION
This office action addresses Applicant’s response filed on 10 June 2026. Claims 1, 3, 4, 6, 7, 9, and 10 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4, 6, 7, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gangadharan (“Constraining Designs for Synthesis and Timing Analysis”) in view of Shah (US 10,685,730), Kanamaru (US 2008/0059938), and Chakrabarty (US 2014/0122951).
Regarding claim 1, Gangadharan discloses a path verification method in a logic circuit for chip test (pp. 167-168, § 14.2), the method comprising: determining a plurality of first paths that are to be tested in a design for test (DFT) mode, wherein a design for test (DFT) includes an additional logic added to a design of integrated circuit (IC) for simplifying a manufacturing test of an IC chip (p. 168, Fig. 14.1 and related text, all paths to and between scan elements); determining a plurality of second paths that are to be tested in a function mode (p. 168, Fig. 14.1 and related text, e.g., path F1-F3); determining a third path from the plurality of first paths that needs to be tested in the DFT mode and not in the function mode, the third path being one of the plurality of first paths (p. 168, Fig. 14.1 and related text, e.g., path F1-F2/SI);
configuring a time sequence constraint for the third path in the function mode to have a number AA clock cycles for the additional logic of the DFT to have target performance, AA being a floor of a ratio of a clock frequency in the function mode to a clock frequency in the DFT mode, AA being a positive integer greater than 1, and the floor of the ratio being the largest integer that is less than or equal to the ratio; and performing a hold analysis in (AA-1)-th clock cycle and performing a setup analysis in the AA-th clock cycle for the third path to minimize a quantity of clock cycles waiting for the third path in the function mode, thereby improving work efficiency (pp. 168 and 188-189; test mode path to F/SI is treated as a multicycle path with AA cycles, AA being based on the ratio of the test clock to functional clock, setup using AA and hold using AA-1);
and removing the time sequence constraint configured for the third path in the DFT mode (p. 169, ¶1, test mode analyzes F1-F2 using TestClock; p. 188, § 15.4.4, the multicycle path constraint is only for testing under the functional C1 clock).
If Gangadharan is found to be unclear regarding determining a plurality of first paths that are to be tested in a design for test (DFT) mode, wherein a DFT includes an additional logic added to a design of integrated circuit (IC) for simplifying a manufacturing test of an IC chip, Shah discloses the same (col. 2, lines 40-53; col. 3, lines 43-44; col. 6, lines 34-38, 48-50, and 58-60). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Gangadharan and Shah, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of facilitating circuit testing. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Gangadharan discloses a circuit including a scan chain, which persons having ordinary skill in the art would recognize as being testing elements inserted into circuit designs that facilitate testing of the circuit, as taught by Shah. The teachings of Shah are directly applicable to Gangadharan in the same way, so that Gangadharan would similarly insert scan test elements into a design to facilitate circuit testing.
If Gangadharan is found to be unclear regarding AA being a floor, Kanamaru teaches configuring a time sequence constraint for the third path in the function mode to have a number AA clock cycles for the additional logic of the DFT to have target performance, AA being a floor of a ratio of a clock frequency, and AA being a positive integer greater than 1 (¶7). Specifically, Gangadharan discloses that the test path is treated as a multi-cycle path and the timing constraint is relaxed by the ratio of the test vs functional clock, so the test path is considered a four-cycle path, and Kanamaru teaches that relaxing constraints for multi-cycle paths sets the number of clock cycles to have target performance from the usual 1 clock cycle to n (AA) clock cycles, where n is an integer not less than 2.
That n is the floor of the ratio, the floor of the ratio being the largest integer that is less than or equal to the ratio, follows directly from the teachings of Gangadharan and Kanamaru, and the concept of timing constraints. Specifically, the timing constraints of Gangadharan and Kanamaru require that a signal propagate within a certain number of clock cycles. Gangadharan teaches that a timing constraint for a path with a slower clock is relaxed by the ratio of the slower clock to the faster clock. In Gangadharan’s example, the faster clock is four times faster than the slow clock, so the slow path timing constraint can be relaxed by a factor of four, since four cycles of the faster clock occur in the same period as one cycle of the slow clock. However, if, for example, the reference clock were 4.5x faster than the slow clock, the constraint would necessarily be relaxed by 4, rather than 5, because each cycle of the slow clock occurs in the same period as 4.5 cycles of the fast clock, so relaxing by 5 would set the constraint late – the signal must actually arrive within 4.5 cycles of the fast clock for the design to function, but the constraint is set at 5 cycles. Thus, it would be immediately apparent to persons having ordinary skill in the art that the constraint cannot be relaxed by more than 4.5 cycles, and must be less than or equal to 4.5 cycles. Since Kanamaru specifies that multicycle constraint relaxation increases the cycles from 1 to an integer number of clock cycles, the constraint is thus relaxed to the largest integer that is not greater than the clock ratio, which is the claimed floor.
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Gangadharan, Shah, and Kanamaru, because doing so would have involved merely the routine combination of known elements according to known techniques, or the routine use of a known technique to improve similar devices in the same way, to produce merely the predictable results of correctly testing slow paths using fast clocks. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395-1396. Gangadharan discloses setting multicycle constraints on slow paths when testing with faster clocks, based on the ratio between the slower clock and the faster clock. Kanamaru teaches that the multicycle constraint has an integer number of cycles, and persons having ordinary skill in the art would recognize that the number of cycles for the multicycle constraint is necessarily a floor of the ratio in order to ensure that signals do not arrive late. The teachings of Kanamaru are directly applicable to Gangadharan in the same way, so that Gangadharan would similarly use an integer floor of the clock ratio, so that slow paths are correctly tested when using faster clocks.
Gangadharan does not appear to explicitly disclose the ratio being a non-integer; Chakrabarty discloses the same (¶¶57, 61, 65). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Gangadharan, Shah, Kanamaru, and Chakrabarty, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of testing a design at various clock speeds. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Gangadharan discloses signal paths tested in DFT/test modes, where the test clocks are slower than functional clocks, and are selected by designers or test equipment according to test conditions, as taught by Chakrabarty. The teachings of Chakrabarty are directly applicable to Gangadharan in the same way, so that Shah would similarly test designs at various clock frequencies.
Regarding claim 3, Gangadharan discloses that configuring the time sequence constraint for the third path in the function mode includes: setting a time sequence constraint command of set_multicycle_path for the third path (p. 188, last paragraph).
Claims 4 and 6 are directed to systems comprising a processor and memory for performing the methods of claims 1 and 3, and are rejected under the same reasoning. Gangadharan further discloses systems comprising a processor and memory for performing the claimed methods (p. 169, §14.4, SDC (Synopsys Design Constraints) and commands are computer-implemented); Shah also discloses the same (Fig. 1; col. 3, lines 14-16). Motivation to combine remains consistent with claim 1.
Claims 7 and 9 are directed to computer-readable storage media for storing a computer-executable program product that, when executed by a processor, causes the processor to perform the methods of claims 1 and 3. Gangadharan further discloses computer-readable storage media for storing a computer-executable program product that, when executed by a processor, causes the processor to perform the claimed methods (p. 169, §14.4, SDC (Synopsys Design Constraints) and commands are computer-implemented); Shah also discloses the same (Fig. 1; col. 3, lines 14-16). Motivation to combine remains consistent with claim 1.
Regarding claim 10, Gangadharan discloses that the third path extends from an output of a first flip-flop to a scan input of a second flip-flop (p. 168, Fig. 14.1 and related text, e.g., path F1-F2/SI).
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection. Applicant asserts that the prior art fails to teach newly-added limitations, which are addressed above using newly-cited prior art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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24 August 2026
/ARIC LIN/ Examiner, Art Unit 2851
/JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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