DETAILED ACTION
This office action addresses Applicant’s response filed on 24 November 2025. Claims 1-9 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4, 6, 7, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shah (US 10,685,730) in view of Wright (US 2003/0211641), Venkataramani (US 10,078,717), Kanamaru (US 2008/0059938), Chakrabarty (US 2014/0122951), and Ginetti (US 5,825,658).
Regarding claim 1, Shah discloses a path verification method in a logic circuit for chip test (col. 2, lines 40-53; col. 3, lines 1-7), the method comprising:
determining a plurality of first paths that are to be tested in a design for test (DFT) mode, wherein a DFT includes an additional logic added to a design of integrated circuit (IC) for simplifying a manufacturing test of an IC chip (col. 2, lines 40-53; col. 3, lines 43-44; col. 6, lines 34-38, 48-50, and 58-60);
determining a plurality of second paths that are to be tested in a function mode (col. 3, line 42; col. 6, lines 42-44);
determining a third path from the plurality of first paths that needs to be tested in the DFT mode and not in the function mode, the third path being one of the plurality of first paths (col. 6, lines 34-38, 48-50, and 58-60).
Shah does not appear to explicitly disclose configuring a time sequence constraint for the third path in the function mode to have a number AA clock cycles for the additional logic of the DFT to have target performance, AA being a floor of a ratio of a clock frequency in the function mode to a clock frequency in the DFT mode, and AA being a positive integer greater than 1; and performing a hold analysis in (AA-1)-th clock cycle and performing a setup analysis in the AA-th clock cycle for the third path to minimize a quantity of clock cycles waiting for the third path in the function mode, thereby improving work efficiency.
Persons having ordinary skill in the art would recognize that the clock frequency in the function mode is faster than the clock frequency in the DFT mode, as taught by Wright (¶36). Venkataramani discloses configuring a time sequence constraint for the third path in the faster mode to have a number AA clock cycles for the additional logic of the DFT to have target performance, AA being less than or equal to a ratio of a clock frequency in the faster mode to a clock frequency in the slower mode, and AA being a positive integer greater than 1 (col. 16, lines 30-32, 42-46, 50-51; slow path is treated as multi-cycle path, so timing constraint is relaxed by the ratio of the slow vs functional clock rate, e.g. a path is considered a five-cycle path because the clock frequency is five times slower than the functional clock). Kanamaru also teaches configuring a time sequence constraint for the third path in the function mode to have a number AA clock cycles for the additional logic of the DFT to have target performance, AA being a floor of a ratio of a clock frequency, and AA being a positive integer greater than 1 (¶7). Specifically, Venkataramani teaches that a slower path is treated as a multi-cycle path and the timing constraint is relaxed by the ratio of the slow vs functional clock rate, so the slow path is considered a five-cycle path, and Kanamaru teaches that relaxing constraints for multi-cycle paths sets the number of clock cycles to have target performance from the usual 1 clock cycle to n (AA) clock cycles, where n is an integer not less than 2.
That n is the floor of the ratio, the floor of the ratio being the largest integer that is less than or equal to the ratio, follows directly from the teachings of Venkataramani and Kanamaru, and the concept of timing constraints. Specifically, the timing constraints of Venkataramani and Kanamaru require that a signal propagate within a certain number of clock cycles. Venktaramani teaches that a timing constraint for a path with a slower clock is relaxed by the ratio of the slower clock to the reference clock. In Venkataramani’s example, the reference clock is five times faster than the slow clock, so the slow path timing constraint can be relaxed by a factor of five, since five cycles of the reference clock occur in the same period as one cycle of the slow clock. However, if, for example, the reference clock were 4.5x faster than the slow clock, the constraint would necessarily be relaxed by 4, rather than 5, because each cycle of the slow clock occurs in the same period as 4.5 cycles of the fast clock, so relaxing by 5 would set the constraint late – the signal must actually arrive within 4.5 cycles of the fast clock for the design to function, but the constraint is set at 5 cycles. Thus, it would be immediately apparent to persons having ordinary skill in the art that the constraint cannot be relaxed by more than 4.5 cycles, and must be less than or equal to 4.5 cycles. Since Kanamaru specifies that multicycle constraint relaxation increases the cycles from 1 to an integer number of clock cycles, the constraint is thus relaxed to the largest integer that is not greater than the clock ratio, which is the claimed floor.
Ginetti discloses configuring a time sequence constraint for the third path in the function mode to have a number AA clock cycles for the additional logic of the DFT to have target performance, AA being a positive integer (col. 3, lines 26-30); and performing a hold analysis in (AA-1)-th clock cycle (col. 2, lines 62 to col. 3, line 7; col. 3, lines 38-40) and performing a setup analysis in the AA-th clock cycle for the third path minimize a quantity of clock cycles waiting for the third path in the function mode (col. 2, lines 45-49; col. 3, lines 26-30).
Thus, Shah teaches identifying paths that are exercised in DFT mode, which is known to operate at slower frequency (as taught by Wright), Venkataramani teaches that timing constraints should be relaxed for paths in slower modes (treated as multi-cycle paths) according to the ratio of the frequency of the slower mode to the functional mode, Kanamaru teaches that such relaxation of constraints for multi-cycle paths loosens the requirement to achieve target performance from the usual 1 clock cycle to n clock cycles, where n is an integer not less than 2, and Ginetti teaches that such relaxed timing constraints include setup and hold constraints at N and N-1 cycles.
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Shah, Wright, Venkataramani, Kanamaru, and Ginetti, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of correctly verifying timing behavior of testing paths, and operating circuits at faster speeds in functional modes than allowed in DFT modes. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Shah discloses signal paths tested in DFT/test modes. Wright provides evidence of the known fact that functional mode clock frequencies are larger than testing mode clock frequencies. Venkataramani teaches relaxing timing constraints for lower-frequency modes by a ratio of the different frequencies, while Kanamaru teaches that constraint relaxation loosens the timing requirement to n clock cycles. Ginetti teaches performing setup and hold timing tests of paths, and testing paths having different clock frequencies, in order to verify correct behavior. The teachings of Wright, Venkataramani, Kanamaru, and Ginetti are directly applicable to Shah, so that Shah would similarly perform setup and hold test of Shah’s paths using relaxed timing constraints based on slower DFT mode clock frequencies in order to correctly verify operation of the paths, without unnecessary timing optimization (Kanamaru ¶8), while still operating a device at higher speeds in functional mode than allowed in DFT modes.
Shah does not appear to explicitly disclose that the ratio is a non-integer. Chakrabarty discloses the same (¶¶57, 61, 65). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Shah, Wright, Venkataramani, Kanamaru, Ginetti, and Chakrabarty, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of testing a design at various clock speeds. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Shah discloses signal paths tested in DFT/test modes. Persons having ordinary skill in the art would know that test clocks are slower than functional clocks, as taught by Wright, and are selected by designers or test equipment according to test conditions, as taught by Chakrabarty. The teachings of Chakrabarty are directly applicable to Shah in the same way, so that Shah would similarly test designs at various clock frequencies.
Regarding claim 3, Shah does not appear to explicitly disclose that configuring the time sequence constraint for the third path in the function mode includes setting a time sequence constraint command of set_multicycle_path for the third path. Ginetti discloses these limitations (col. 3, lines 16-24; col. 11, lines 47 and 50). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Shah, Wright, Venkataramani, Kanamaru, and Ginetti, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of allowing users to relax timing constraints on DFT paths. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Shah teaches paths tested DFT/test modes. Ginetti teaches relaxing timing constraints on paths by setting a constraint command of set multicycle path. The teachings of Ginetti are directly applicable to Shah in the same way, so that Shah would similarly relax timing constraints on DFT paths by setting a constraint command of set multicycle path.
Claims 4 and 6 are directed to systems comprising a processor and memory for performing the methods of claims 1 and 3, and are rejected under the same reasoning. Shah further discloses systems comprising a processor and memory for performing the claimed methods (Fig. 1; col. 3, lines 14-16). Ginetti also discloses systems comprising a processor and memory for performing the claimed methods (Fig. 13).
Claims 7 and 9 are directed to computer-readable storage media for storing a computer-executable program product that, when executed by a processor, causes the processor to perform the methods of claims 1 and 3. Shah further discloses computer-readable storage media for storing a computer-executable program product that, when executed by a processor, causes the processor to perform the claimed methods (Fig. 1; col. 3, lines 14-16). Ginetti also discloses computer-readable storage media for storing a computer-executable program product that, when executed by a processor, causes the processor to perform the claimed methods (Fig. 13).
Claim(s) 2, 5, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shah in view of Wright, Venkataramani, Kanamaru Ginetti, Chakrabarty, and Chandrakar (US 9,372,953).
Regarding claims 2, 5, and 8, Shah discloses third path in the DFT mode (col. 2, lines 40-53; col. 3, lines 43-44; col. 6, lines 48-50 and 58-60), but does not appear to explicitly disclose removing the time sequence constraint configured for the third path. Chandrakar discloses these limitations (col. 6, lines 31-35). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Shah, Wright, Venkataramani, Kanamaru, Ginetti, Chakrabarty, and Chandrakar, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of relaxing timing constraints. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Shah discloses paths tested in DFT modes. Ginetti teaches relaxing constraints of tested paths. Chandrakar teaches that relaxing constraints can be done by removing the constraints. The teachings of Chandrakar are directly applicable to Shah and Ginetti, so that constraint relaxation would similarly be done by removing the constraints.
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection. Applicant asserts that the prior art fails to teach newly-added limitations, which are addressed above using newly-cited prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIC LIN whose telephone number is (571)270-3090. The examiner can normally be reached M-F 07:30-17:00 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
7 March 2026
/ARIC LIN/Examiner, Art Unit 2851