DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Drawing Objections
Applicant has amended the drawings at issue and the previous objections have therefore been withdrawn.
Claim Rejections – 35 USC 112
Applicant has amended the claims at issue and the previous rejections have therefore been withdrawn. However, new claim objections are made in view of the amendments.
Prior Art Rejections
Applicant's arguments filed 4/24/2026 have been fully considered but they are not persuasive.
Applicant asserts Lukyanov fails to teach or show obvious the combination of the first buffer and the second buffer in amended claim 1, and does not mention “store the activation value and the weight value in the second buffer when at least one of the activation precision and weight precision corresponds to the second precision”. Examiner respectfully disagrees.
The scope of the current independent claims merely recites a processing element comprising a first buffer, storing a first number of values based on the first precision and multiply and accumulate (MAC) circuity precision, and a second buffer, storing a second number of values based on the second precision and multiply and accumulate (MAC) circuity precision. Lukyanov Fig. 10 element 1030 R6 corresponds with a first buffer, with a first number of values being 4 based on the values being fp8 and the FMAD being single precision ([0061]), and at least one of R0-R3 corresponds to a second buffer, with a second number of values being at least 1 based on the values being fp32 and the FMAD being single precision ([0061]). In other words, Lukyanov teaches registers that stores a number of values based on the input value precision and FMAD precision. However, the Examiner interprets the “the first(/second) number determined based on a precision of the multiply accumulate circuitry and the first(/second) precision” to mean the first number and the second number to be different, as the first precision and the second precision are different. Therefore, for Lukyanov Fig. 10 element 1030, R0-R3 cannot be a set of registers that corresponds with the second buffer because the number of values would be 4, which would be equal to the corresponding first number for R6. Furthermore, Lukyanov suggests storing “the activation value and weight value in the second buffer when at least one of the activation precision and weight precision corresponds to the second precision” ([0088]-[0089]) as the registers discussed above corresponds to a first buffer and a second buffer.
Claim Objections
Claims 1, 10, 19 are objected to because of the following informalities:
Claims 1, 10, 19, reinsert “of” before “the multiply and accumulate circuitry and the second precision”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 7, 10-11, 13-14, 16, 19-20, 22, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Lukyanov et al. (US 20150378741 A1, hereinafter “Lukyanov”) in view of Kim (US 20230058095 A1, hereinafter “Kim”). Regarding claims 1, 10, 19, the preamble has not been given patentable weight. The claim body is complete such that the preamble merely recites the intended use of the invention. It is therefore not limiting. See MPEP 2111.02(II).
As per claim 1, Lukyanov teaches a first buffer to store data corresponding to a first precision, the first buffer to store a first number of values of the first precision, the first number determined based on a precision of multiply and accumulate circuitry and the first precision (Lukyanov: Fig. 10 element 1030; [0081], wherein the first buffer corresponds to R6);
a second buffer to store data corresponding to a second precision higher than the first precision, the second buffer to store a second number of values of the second precision, the second number determined based on the precision the multiply and accumulate circuitry and the second precision (Lukyanov: Fig. 10 element 1030; [0081], wherein the second buffer corresponds to at least one of R0-R3);
and store the activation value and the weight value in the second buffer when the activation precision or the weight precision corresponds to the second precision (Lukyanov: [0088]-[0089], wherein Lukyanov suggests lower precision inputs are deposited in larger precision registers corresponding to the expected precision of the operation).
However, while Lukyanov discloses data in compressed for [0088], Lukyanov does not explicitly disclose how the system may determine the precisions of the data in compressed form. Thus, Lukyanov does not teach hardware control circuitry to: process a first multibit bitmap to determine an activation precision of an activation value, the first multibit bitmap including values corresponding to different precisions; process a second multibit bitmap to determine a weight precision of a weight value, the second multibit bitmap including values corresponding to different precisions;
Kim teaches hardware control circuitry to: process a first multibit bitmap to determine an activation precision of an activation value, the first multibit bitmap including values corresponding to different precisions (Kim: Fig. 4 element 403; [0091], wherein Flag A corresponds to a first multibit bitmap);
process a second multibit bitmap to determine a weight precision of a weight value, the second multibit bitmap including values corresponding to different precisions (Kim: Fig. 4 element 404; [0091], wherein Flag B corresponds to a second multibit bitmap);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the processing element of Lukyanov (Fig. 4) with the bit-width information of Kim. One would have been motivated to combine these references because both references disclose architectures for mixed precision computation, and Kim increases throughput by reducing precisions when applicable ([0094]).
As per claim 2, Lukyanov/Kim further teaches The processing element of claim 1, further including bitmap generation circuitry to generate the first multibit bitmap based on the activation precision (Kim: Fig. 4 element 410; [0091]).
As per claim 4, Lukyanov/Kim further teaches The processing element of claim 1, wherein the hardware control circuitry is to, if the activation value and the weight value are stored in the second buffer, add a value to at least one the activation value or the weight value to fill space in the second buffer (Lukyanov: [0089], it follows that to store a 16-bit value into a 32-bit register, the remaining values must be filled with 0s to prevent error in computation).
As per claim 5 Lukyanov/Kim further teaches The processing element of claim 1, further including a multiplexer including inputs coupled to the first buffer and the second buffer and an output coupled to the multiply and accumulate circuitry (Lukyanov: Fig. 4, register read route multiplexers).
As per claim 7, Lukyanov/Kim further teaches The processing element of claim 1, further including quantization circuitry to quantize (a) the activation value into the activation precision and (b) the weight value into the weight precision to reduce overhead (Kim: Fig. 4 element 410; [0089]).
As per claims 10-11, 13-14, 16, the claims are directed to an apparatus that implements the same or similar features as the processing element of claims 1-2, 4-5, 7, and is therefore rejected for at least the same reasons therein.
As per claims 19-20, 22, 24, the claims are directed to a non-transitory computer readable medium that implements the same or similar features as the processing element of claims 1-2, 4, 7, and is therefore rejected for at least the same reasons therein.
Claims 3, 8-9, 12, 17-18, 21, 25 are rejected under 35 U.S.C. 103 as being unpatentable over Lukyanov/Kim in further view of Raha et al (US 20210397414 A1, hereinafter “Raha”).
As per claim 3, Lukyanov/Kim further teaches The processing element of claim 1,
However, Lukyanov/Kim does not teach wherein the first multibit bitmap identifies precisions of non-zero values of dense activation values.
Raha teaches wherein the first multibit bitmap identifies precisions of non-zero values of dense activation values (Raha: Fig. 19; [0073]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the processing element of Lukyanov (Fig. 4) with the sparsity acceleration logic of Raha. One would have been motivated to combine these references because both references disclose architectures for mixed precision computation, and Raha teaches including sparsity logic reduces processing overhead ([0073]).
As per claim 8, Lukyanov/Kim further teaches The processing element of claim 1,
However, Lukyanov/Kim does not teach further including a logic gate to generate a combined multibit bitmap based on a logic AND function of the first multibit bitmap corresponding to the activation value and the second multibit bitmap corresponding to the weight value.
Raha teaches further including a logic gate to generate a combined multibit bitmap based on a logic AND function of the first multibit bitmap corresponding to the activation value and the second multibit bitmap corresponding to the weight value (Raha Fig. 9; [0073]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the processing element of Lukyanov (Fig. 4) with the sparsity acceleration logic of Raha for at least the same reasons as discussed above in claim 3.
As per claim 9, Lukyanov/Kim/Raha further teaches The processing element of claim 8, wherein the hardware control circuitry is to discard the activation value and the weight value when the combined bitmap indicates that the activation value or the weight value is zero (Raha Fig. 9; [0073]).
As per claims 12, 17-18, the claims are directed to an apparatus that implements the same or similar features as the processing element of claims 3, 8-9 and is therefore rejected for at least the same reasons therein.
As per claims 21, 25, the claims are directed to a non-transitory computer readable medium that implements the same or similar features as the processing element of claims 3, 8 and is therefore rejected for at least the same reasons therein.
Allowable Subject Matter
Claims 6, 15, 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claims 6, 15, 23, the prior art of record does not teach or suggest a combination as claimed including: the first buffer to store a first number of values of the first precision, the first number determined based on a precision of multiply and accumulate circuitry and the first precision;
a second buffer to store data corresponding to a second precision higher than the first precision, the second buffer to store a second number of values of the second precision, the second number determined based on the precision the multiply and accumulate circuitry and the second precision;
control the multiplexer to (a) output values stored in the first buffer when the first buffer is full and (b) output values stored in the second buffer when the second buffer is full.
Lukyanov discloses register files storing values based on units of work ([0081]) and performing the multiply add based on the units of work ([0088]). Thus, Lukyanov teaches performing a multiply-add operation when the indicated units of work are met. Lukyanov does not suggest outputting the values of the corresponding registers when they store a number of values based on the respective precisions of the inputs and the FMAD circuit. Therefore, Lukyanov does not teach or suggest a combination as claimed including the limitations identified above.
Kim discloses using flag bits to represent the different input precisions (Fig. 4; [0091]). Kim does not suggest buffers storing the inputs based on the respective precisions. Therefore, Kim does not teach or suggest a combination as claimed including the limitations identified above.
Raha discloses multibit bitmaps indicating non-zero values of activation and weights (Fig. 19). Raha does not suggest controlling a multiplexer to output values stored in buffers configured to store a number of values based on the input precisions when the buffers are full. Therefore, Raha does not teach or suggest a combination as claimed including the limitations identified above.
Carvalho et al. (Towards a Transprecision Polymorphic Floating-Point Unit for Mixed-precision Computing, hereinafter “Carvalho”) discloses a polymorphic register file that includes tag bits to indicate the precision of the value stored in the corresponding register (Fig. 1). Carvalho does not suggest outputting the values of the corresponding registers when they store a number of values based on the respective precisions of the inputs and FPU pipeline. Therefore, Carvalho does not teach or suggest a combination as claimed including the limitations identified above.
Devic et al. (Highly-Adaptive Mixed-Precision MAC Unit for Smart and Low-Power Edge Computing, hereinafter “Devic”) discloses a mixed-precision MAC unit that accommodates different precision operands by partitioning with smaller multipliers (Section III.B). Devic does not suggest different buffers to store data corresponding to a respective precision. Therefore, Devic does not teach or suggest a combination as claimed including the limitations identified above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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