DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because Figures 3A-3C label the MAC circuitry with the reference number 214, but the reference number should be 216 based on paragraphs [0050], [0052], and [0054].
Additionally, in Fig. 3C, the MAC circuitry shows an adder between the MUX and accumulator when it should be a multiplier based on [0056].
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 9, 10, 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "store… the weight value in the second buffer when at least one of the activation prevision or the weight precision corresponds to the second precision". There is insufficient antecedent basis for this limitation in the claim as the second buffer and second precision are only recited to correspond with the activation precision and is silent that a weight precision may correspond to the second buffer and second precision.
Claims 10, 19 are rejected for the same reasons as claim 1 recited as above.
Claim 1 recites the limitation "determine an activation precision of an activation value". It is unclear whether the activation value should correspond with the first number of activation values or the second number of activation values. Furthermore, claim 1 recites “store the activation values… when… the activation precision… corresponds to the second precision.” The claim language is unclear in this condition, when the activation value is of the first number of activation values.
Claims 10, 19 are rejected for the same reasons as claim 1 recited as above.
Claims 9, 18 recites the limitation "the precision". There is insufficient antecedent basis for this limitation in the claim. It is unclear which precision is being referred to. For examination purposes, “the precision” will be interpreted as “the activation precision”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7, 10-11, 13-16, 19-20, 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Lukyanov et al. (US 20150378741 A1, hereinafter “Lukyanov”) in view of . Regarding claims 1, 10, 19, the preamble has not been given patentable weight. The claim body is complete such that the preamble merely recites the intended use of the invention. It is therefore not limiting. See MPEP 2111.02(II).
As per claim 1, Lukyanov teaches a first buffer to store data corresponding to a first precision, the first buffer sized to store a first number of activation values corresponding to a structure of multiply and accumulate circuitry (Lukyanov: Fig. 10 element 1030; [0081], wherein the first buffer corresponds to at least one of R4, R5, or R6);
a second buffer to store data corresponding to a second precision higher than the first precision, the second buffer sized to store a second number of activation values corresponding to the structure of the multiply and accumulate circuitry (Lukyanov: Fig. 10 element 1030; [0081], wherein the second buffer corresponds to at least one of R0-R3);
and store the activation value and the weight value in the second buffer when at least one of the activation precision or the weight precision corresponds to the second precision (Lukyanov: [0088]-[0089], wherein Lukyanov suggests lower precision inputs are deposited in larger precision registers corresponding to the expected precision of the operation).
However, while Lukyanov discloses data in compressed for [0088], Lukyanov does not explicitly disclose how the system may determine the precisions of the data in compressed form. Thus, Lukyanov does not teach hardware control circuitry to: process a first multibit bitmap to determine an activation precision of an activation value, the first multibit bitmap including values corresponding to different precisions; process a second multibit bitmap to determine a weight precision of a weight value, the second multibit bitmap including values corresponding to different precisions;
Kim teaches hardware control circuitry to: process a first multibit bitmap to determine an activation precision of an activation value, the first multibit bitmap including values corresponding to different precisions (Kim: Fig. 4 element 403; [0091], wherein Flag A corresponds to a first multibit bitmap);
process a second multibit bitmap to determine a weight precision of a weight value, the second multibit bitmap including values corresponding to different precisions (Kim: Fig. 4 element 404; [0091], wherein Flag B corresponds to a second multibit bitmap);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the processing element of Lukyanov (Fig. 4) with the bit-width information of Kim. One would have been motivated to combine these references because both references disclose architectures for mixed precision computation, and Kim increases throughput by reducing precisions when applicable ([0094]).
As per claim 2, Lukyanov/Kim further teaches The processing element of claim 1, further including bitmap generation circuitry to generate the first multibit bitmap based on the activation precision (Kim: Fig. 4 element 410; [0091]).
As per claim 4, Lukyanov/Kim further teaches The processing element of claim 1, wherein the hardware control circuitry is to, if the activation value and the weight value are stored in the second buffer, add a value to at least one the activation value or the weight value to fill space in the second buffer (Lukyanov: [0089], it follows that to store a 16-bit value into a 32-bit register, the remaining values must be filled with 0s to prevent error in computation).
As per claim 5 Lukyanov/Kim further teaches The processing element of claim 1, further including a multiplexer including inputs coupled to the first buffer and the second buffer and an output coupled to the multiply and accumulate circuitry (Lukyanov: Fig. 4, register read route multiplexers).
As per claim 6, Lukyanov/Kim further teaches The processing element of claim 5, wherein the hardware control circuitry is to control the multiplexer to (a) output values stored in the first buffer when the first buffer is full and (b) output values stored in the second buffer when the second buffer is full (Lukyanov: [0088]-[0089], it follows that registers are not read until data transfer to the register is completed).
As per claim 7, Lukyanov/Kim further teaches The processing element of claim 1, further including quantization circuitry to quantize (a) the activation value into the activation precision and (b) the weight value into the weight precision to reduce overhead (Kim: Fig. 4 element 410; [0089]).
As per claims 10-11, 13-16, the claims are directed to an apparatus that implements the same or similar features as the processing element of claims 1-2, 4-7, and is therefore rejected for at least the same reasons therein.
As per claims 19-20, 22-24, the claims are directed to a non-transitory computer readable medium that implements the same or similar features as the processing element of claims 1-2, 4, 6-7, and is therefore rejected for at least the same reasons therein.
Claims 3, 8-9, 12, 17-18, 21, 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Lukyanov/Kim in further view of Raha et al (US 20210397414 A1, hereinafter “Raha”).
As per claim 3, Lukyanov/Kim further teaches The processing element of claim 1,
However, Lukyanov/Kim does not teach wherein the first multibit bitmap identifies precisions of non-zero values of dense activation values.
Raha teaches wherein the first multibit bitmap identifies precisions of non-zero values of dense activation values (Raha: Fig. 19; [0073]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the processing element of Lukyanov (Fig. 4) with the sparsity acceleration logic of Raha. One would have been motivated to combine these references because both references disclose architectures for mixed precision computation, and Raha teaches including sparsity logic reduces processing overhead ([0073]).
As per claim 8, Lukyanov/Kim further teaches The processing element of claim 1,
However, Lukyanov/Kim does not teach further including a logic gate to generate a combined multibit bitmap based on a logic AND function of the first multibit bitmap corresponding to the activation value and the second multibit bitmap corresponding to the weight value.
Raha teaches further including a logic gate to generate a combined multibit bitmap based on a logic AND function of the first multibit bitmap corresponding to the activation value and the second multibit bitmap corresponding to the weight value (Raha Fig. 9; [0073]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the processing element of Lukyanov (Fig. 4) with the sparsity acceleration logic of Raha for at least the same reasons as discussed above in claim 3.
As per claim 9, Lukyanov/Kim/Raha further teaches The processing element of claim 8, wherein the hardware control circuitry is to discard at least one of the activation value or the weight value when at least a value of the combined bitmap corresponding to the activation value and the precision corresponds to zero (Raha Fig. 9; [0073]).
As per claims 12, 17-18, the claims are directed to an apparatus that implements the same or similar features as the processing element of claims 3, 8-9 and is therefore rejected for at least the same reasons therein.
As per claims 21, 25-26, the claims are directed to a non-transitory computer readable medium that implements the same or similar features as the processing element of claims 3, 8-9 and is therefore rejected for at least the same reasons therein.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Carvalho et al. (Towards a Transprecision Polymorphic Floating-Point Unit for Mixed-precision Computing) discloses a polymorphic register file that includes tag bits to indicate the precision of the value stored in the corresponding register, in addition to adding null values to the unused bits of the register (Fig. 1).
Devic et al. (Highly-Adaptive Mixed-Precision MAC Unit for Smart and Low-Power Edge Computing) discloses a mixed-precision MAC unit that accommodates different precision operands by partitioning with smaller multipliers (section III.B)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHAT N LE whose telephone number is (571)272-0546. The examiner can normally be reached Monday-Friday 8:30AM-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182