Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendments submitted August 26, 2026 to claims 1, 3 and 5 are acknowledged and have since been entered.
Claim Interpretation
Claim 1 cites “an inner field effect transistor” and “an outer field effect transistor,” which examiner notes refers to a lower FET and upper FET respectively as specified in paragraph [0045] of the instant application. As such, the terms “inner” and “upper” in relation to each FET and their corresponding components are interpreted to mean “lower” and “upper” respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-9 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 20210265345 A1) and Paul (US 20190214469 A1) and further in view of Hwang (US 20230046885 A1).
Regarding Claim 1, Xie teaches a semiconductor structure (see Fig. 1) comprising:
an inner field effect transistor (lower FET, see Fig. 26, see also “lower nanosheets” labeled in Fig. 2) having an inner source (1706), an inner drain (1706), and a group of inner nanosheet channel structures (210’b and 214’b) interconnecting the inner source and the inner drain (shown Fig. 26);
an outer field effect transistor (upper FET, shown Fig. 26, see also “upper nanosheets” labeled in Fig. 2) having an outer source (1710), an outer drain (1710), and a group of outer nanosheet channel structures (222’b and 226’b) interconnecting the outer source and the outer drain (shown Fig. 26);
an isolation region (1708) between the inner field effect transistor and the outer field effect transistor (shown Fig. 26);
a metal gate stack (2002, 2602 and 2604) between the inner source and inner drain and between the outer source and the outer drain (shown Fig. 26), the metal gate stack at least partially surrounding the group of inner nanosheet channel structures and the group of outer nanosheet channel structures (shown Fig. 27, see also [0092] which describes a “gate-all-around” configuration), the metal gate stack having a dielectric region (1502’) adjacent the isolation region;
a substrate (202), wherein the inner field effect transistor and the metal gate stack are formed on the substrate (shown Fig. 26); and
shallow trench isolation (304) material recessed into the substrate (see Fig. 3 and [0010]) adjacent to the inner source and the inner drain (see Figs. 1 and 26-27, wherein it is understood that the STI extends along a protruding portion of the substrate and is adjacent to lower source and drain 1706).
Paul (US 10418449 B2) being further incorporated by reference in Xie (see [0069]), of which Paul (US 20190214469 A1) is deemed an equivalent disclosure, teaches circuitry based on complementary field-effect transistors, wherein the metal gate stack includes a side region electrically coupling an inner gate of the inner field effect transistor and an outer gate of the outer field effect transistor and forming an input node (see Paul: Fig. 14D and [0065] which describes the functional gate structures being coupled to a contact in metallization level 92).
Xie and Paul are silent regarding a specific position of the side region of the metal gate stack being used to couple the inner gate and outer gate.
Hwang teaches a vertically stacked CFET (see Figs. 4A-4C) wherein a side region (shown Fig. 4A and 4C, corresponding to region annotated by II-II’ in Fig. 1A) includes a gate contact plug (420) coupling an inner gate (405G) of an inner field effect transistor (405) and an outer gate (415G) of an outer field effect transistor (415) and the side region is disposed outside a group of inner nanosheet channel structures (405C, shown Fig. 4B) and outer nanosheet channel structures (415C, shown Fig. 4B).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to provide the gate contact plug of Hwang at a side region disposed outside a group of inner nanosheet channel structure and outer nanosheet channel structures as this would enable the necessary coupling of the complementary gate structures to form an input node outside the active channel regions without sacrificing an area of gain achieved by the multi-stack semiconductor device in a simplified process of forming a gate contact plug (see also Hwang: [0056]).
Regarding Claim 2, Xie teaches the semiconductor structure of Claim 1, wherein the inner field effect transistor comprises one of an n-type field effect transistor and a p-type field effect transistor (see [0036]), and wherein the outer field effect transistor comprises another one of an n-type field effect transistor and a p-type field effect transistor (see [0036]).
Regarding Claim 3, Xie teaches the semiconductor structure of Claim 2, wherein the inner field effect transistor comprises the n-type field effect transistor and the outer field effect transistor comprises the p-type field effect transistor (see [0036]). Paul (US 10418449 B2) being further incorporated by reference in Xie (see [0069]), of which Paul (US 20190214469 A1) is deemed an equivalent disclosure, teaches circuitry based on complementary field-effect transistors, wherein a stacked semiconductor structure further comprises a first electrically conductive pathway (Paul: 88, shown Fig. 14C) coupling an inner drain (38) and an outer drain (46) and forming an output node (shown Paul: Fig. 14C),
Regarding Claim 4, Xie teaches the semiconductor structure of Claim 3, further comprising:
a first rail (Paul: 96, shown Fig. 14D) electrically coupled to the outer source; and
a second rail (Paul: 100, shown Fig. 14D) electrically coupled to the inner source.
Regarding Claim 5, Xie teaches the semiconductor structure of Claim 4, further comprising:
a plurality of additional p-type inner field effect transistors having a plurality of additional inner sources, a plurality of additional inner drains, and a plurality of additional groups of inner nanosheet channel structures interconnecting the plurality of additional inner sources and the plurality of additional inner drains (shown Fig. 26, see also Xie: [0042] which discloses a number of FETs shown being “merely an example”);
a plurality of additional n-type outer field effect transistors having a plurality of additional outer sources, a plurality of additional outer drains, and a plurality of additional groups of outer nanosheet channel structures interconnecting the plurality of additional outer sources and the plurality of additional outer drains (as suggested in Xie: [0042], any number of devices may be implemented to match the exemplary pattern shown in Fig. 26);
a plurality of additional metal gate stacks between the plurality of additional inner sources and the plurality of additional inner drains and between the plurality of additional outer sources and the plurality of additional outer drains, the plurality of additional metal gate stacks at least partially surrounding the plurality of additional groups of inner and outer nanosheet channel structures; and
a plurality of additional first electrically conductive pathways coupling the plurality of additional inner drains and the plurality of additional outer drains and forming a plurality of additional output nodes (as evidenced by Paul: Fig. 14D and [0032]); and
wherein:
the isolation region extends between the plurality of additional p-type inner field effect transistors and the plurality of additional n-type outer field effect transistors (shown Xie: Fig. 26), the plurality of additional metal gate stacks each having a dielectric region (1502’) adjacent the isolation region (shown Fig. 26);
the plurality of additional outer sources are electrically coupled to the first rail (as evidenced by Paul, see also Fig. 14D and [0065] which describes a first power rail supplying a positive supply voltage, which is understood to be common to any number of implemented transistors within the designed cell);
the plurality of additional inner sources are electrically coupled to the second rail (as evidenced by Paul, see also Fig. 14D).
Regarding Claim 6, Xie teaches the semiconductor structure of Claim 5, further comprising a power supply coupled to the first rail (see evidenced by Paul: [0065]).
Regarding Claim 7, Xie teaches the semiconductor structure of Claim 4, wherein the second rail comprises a buried power rail (shown Paul: Fig. 14D).
Regarding Claim 8, Xie teaches the semiconductor structure of Claim 1, wherein the dielectric region comprises SiOx, SiC, SiCO or another suitable “material for dielectric spacers” (see Xie: [0065]). Xie further teaches a list of suitable dielectric materials for inner spacers being SiOx, SiC, SiCO or SiN (see [0068]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement silicon nitride as the material of the dielectric region of Xie as “[t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness” (see also MPEP 2144.07).
Regarding Claim 9, Xie teaches the semiconductor structure of Claim 8, wherein the inner and outer nanosheet channel structures comprise silicon (see [0043]).
Regarding Claim 12, Xie teaches the semiconductor structure of Claim 1, further comprising gate spacers (1704) located adjacent the metal gate stack (shown Fig. 26).
Regarding Claim 13, Xie teaches the semiconductor structure of Claim 12, wherein the dielectric region comprises SiOx, SiC, SiCO or another suitable “material for dielectric spacers” (see Xie: [0065]), and the gate spacers comprise SiOx, SiC, SiCO or SiN (see also [0068]).
Xie further teaches a list of suitable dielectric materials for inner spacers being SiOx, SiC, SiCO or SiN (see [0068]) and Paul further teaches a suitable dielectric material for a gate spacer (Paul: 24) being silicon oxycarbonitride (SiOCN) (see also Paul: 0035]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement silicon nitride as a material of the dielectric region and SiOCN as a material of the gate spacers of Xie as “[t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness” (see also MPEP 2144.07).
Claim(s) 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 20210265345 A1) and Hwang (US 20230046885 A1) in further view of Singh (US 20130334700 A1).
Regarding Claim 10, Xie teaches the semiconductor structure of Claim 1, but does not explicitly teach wherein the dielectric region has a void located therein.
Singh teaches a semiconductor device comprising a low-k dielectric layer (221), wherein the low-k dielectric layer further comprises a void (air gap 223, see Singh: [0045]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the dielectric region of Xie to further comprise an air gap as suggested by Singh as this may reduce the dielectric constant by 5% or more (see Singh: [0045]) and further provide low capacitance (see Singh: [0048]).
Specifically, this modification would teach the dielectric region having a void, wherein the void is an air gap.
Regarding Claim 11, Xie as modified by Singh teaches the semiconductor structure of Claim 10, wherein the void comprises an air gap.
Response to Arguments
Applicant’s arguments with respect to claim 1 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASEY PAUL BOATMAN whose telephone number is (703)756-4778. The examiner can normally be reached M-F 7:30 AM - 5:30 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.P.B./ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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