Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment submitted December 19, 2025 to claims 2, 3, and 14 is acknowledged and has since been entered.
Claim Interpretation
Claim 1 cites “an inner field effect transistor” and “an outer field effect transistor,” which examiner notes refers to a lower FET and upper FET respectively as specified in paragraph [0045] of the instant application. As such, the terms “inner” and “upper” in relation to each FET and their corresponding components are interpreted to mean “lower” and “upper” respectively.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 8-9 and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 20220059414 A1).
Regarding Claim 1, Yang teaches a semiconductor structure (100-1, shown Fig. 1A) comprising:
an inner field effect transistor (102A) having an inner source (110A, see [0037]), an inner drain (110A), and a group of inner nanosheet channel structures (122A) interconnecting the inner source and the inner drain (see Fig. 1B);
an outer field effect transistor (102B) having an outer source (110B), an outer drain (110B), and a group of outer nanosheet channel structures (122B) interconnecting the outer source and the outer drain (shown Fig. 1B);
an isolation region (120) between the inner field effect transistor and the outer field effect transistor (shown Fig. 1D); and
a metal gate stack (112, see also [0043]) between the inner source and inner drain and between the outer source and the outer drain (shown Fig. 1B), the metal gate stack at least partially surrounding the inner and outer nanosheet channel structures (see [0042] which describes a common GAA-FET configuration), the metal gate stack having a dielectric region (114, shown Fig. 1B) adjacent the isolation region (shown Fig. 1B).
Regarding Claim 2, Yang teaches the semiconductor structure of Claim 1, wherein the inner field effect transistor comprises one of an n-type field effect transistor and a p-type field effect transistor and wherein the outer field effect transistor comprises another one of an n-type field effect transistor and a p-type field effect transistor (see [0030] which describes that either FET may be one of each conductivity type finFET).
Regarding Claim 8, Yang teaches the semiconductor structure of Claim 1, wherein the dielectric region comprises silicon nitride (see [0044]).
Regarding Claim 9, Yang teaches the semiconductor structure of Claim 8, wherein the inner and outer nanosheet channel structures comprise silicon (see [0033]).
Regarding Claim 12, Yang teaches the semiconductor structure of Claim 1, further comprising gate spacers (116) located adjacent the metal gate stack (shown Fig. 1B).
Regarding Claim 13, Yang teaches the semiconductor structure of Claim 12, wherein the dielectric region comprises silicon nitride and the gate spacers comprise silicon oxycarbonitride (SiOCN) (see [0044] which lists SiN as a material for the isolation region and SiOCN for the gate inner spacers).
Claim(s) 1-2 and 8-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie (US 11069684 B1).
Regarding Claim 1, Xie teaches a semiconductor structure (see Fig. 14) comprising:
an inner field effect transistor (106a) having an inner source (126), an inner drain (126), and a group of inner nanosheet channel structures (shown Fig. 14) interconnecting the inner source and the inner drain (shown Fig. 14);
an outer field effect transistor (106b) having an outer source (130), an outer drain (130), and a group of outer nanosheet channel structures (shown Fig. 14) interconnecting the outer source and the outer drain (shown Fig. 14);
an isolation region (146, portion between the inner S/D and outer S/D regions, shown FIG. 14) between the inner field effect transistor and the outer field effect transistor; and
a metal gate stack (134, 122 and 124) between the inner source and inner drain and between the outer source and the outer drain (shown Fig. 14), the metal gate stack at least partially surrounding the inner and outer nanosheet channel structures (see Fig. 1 and Col. 4, Ln. 59-61 which describes the gate structure wrapping around the nanosheet stacks), the metal gate stack having a dielectric region (liner layer 120 and air gap 146 between metal gates of the inner FET and outer FET) adjacent the isolation region (shown Fig. 14).
Regarding Claim 2, Xie teaches the semiconductor structure of Claim 1, wherein the inner field effect transistor comprises one of an n-type field effect transistor and a p-type field effect transistor and wherein the outer field effect transistor comprises another one of an n-type field effect transistor and a p-type field effect transistor (See Col. 3, Ln. 23-29).
Regarding Claim 8, Xie teaches the semiconductor structure of Claim 1, wherein the dielectric region comprises silicon nitride (see Col. 6, Ln. 61-63 which lists SiN as a material for portion 120 of the dielectric region).
Regarding Claim 9, Xie teaches the semiconductor structure of Claim 8, wherein the inner and outer nanosheet channel structures comprise silicon (described as SiGe layers, see Col. 5, Ln. 32-60).
Regarding Claim 10, Xie teaches the semiconductor structure of Claim 1, wherein the dielectric region has a void located therein (shown Fig. 14, wherein an air gap 146 is within the dielectric region).
Regarding Claim 11, Xie teaches the semiconductor structure of Claim 10, wherein the void comprises an air gap (shown Fig. 14, see also Col. 10, Ln. 24-29).
Regarding Claim 12, Xie teaches the semiconductor structure of Claim 1, further comprising gate spacers (124) located adjacent the metal gate stack (shown Fig. 14).
Regarding Claim 13, Xie teaches the semiconductor structure of Claim 12, wherein the dielectric region comprises silicon nitride (See Col. 6, Ln. 61-63 which lists SiN as a material for portion 120 of the dielectric region) and the gate spacers comprise silicon oxycarbonitride (SiOCN) (see Col. 7, Ln. 30-34).
Regarding Claim 14, Xie teaches the semiconductor structure of Claim 1, further comprising:
a substrate (102), wherein the inner field effect transistor and the metal gate stack are formed on the substrate (shown Fig. 14); and
shallow trench isolation material (104, described as a buried oxide, see also Col. 6, Ln. 10-16) recessed into the substrate adjacent the inner source and the inner drain (shown Fig. 14).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20220059414 A1) as applied to the claims above, and further in view of Shao (US 20200286831 A1).
Regarding Claim 3, Yang teaches the semiconductor structure of Claim 2, wherein the inner field effect transistor comprises the n-type field effect transistor and the outer field effect transistor comprises the p-type field effect transistor (see [0030]), wherein the metal gate stack includes a side region (112, shown Fig. 1A) electrically coupling an inner gate of the inner field effect transistor and an outer gate of the outer field effect transistor and forming an input node (see also [0050] which describes an interconnect 111 being connected to gate regions 112A and 112B through gate connection 101).
Paragraph [0030] of Yang further suggests that the semiconductor structure of Fig. 1A may be configured as an inverter logic device, wherein “the use of other structural components, such as contacts, conductive vias, conductive lines, dielectric layers, and passivation layers, that are not shown for simplicity.”
Thus, Yang does not explicitly teach a first electrically conductive pathway coupling the inner drain and the outer drain and forming an output node.
Shao teaches a similar stacked inverter (see Fig. 1) wherein an inner FET (defined by active region 104) and an outer FET (defined by active region 102) are stacked (see [0025]) and drain regions of the inner FET and outer FET are coupled by a first electrically conductive pathway (106-3), thus forming an output node (described in Shao: [0025]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to configure the suggested inverter logic device of Yang to have a first electrically conductive pathway electrically coupling the inner drain and outer drain as this would provide the necessary output node, as evidenced by Shao (see [0025]), for a functioning inverter logic device.
Regarding Claim 4, Yang as modified by Shao teaches the semiconductor structure of Claim 3, further comprising:
a first rail (see described in [0049], wherein a power supply rail is coupled to interconnect 113) electrically coupled to the outer source (shown Fig. 1A); and
a second rail (see described in [0049], wherein a power supply rail is coupled to interconnect 115) electrically coupled to the inner source (shown Fig. 1A).
Regarding Claim 5, Yang as modified by Shao teaches the semiconductor structure of Claim 4, further comprising:
a plurality of additional p-type inner field effect transistors having a plurality of additional inner sources (see [0030] which describes Fig. 1A illustrating a device according to a single gate structure, but a plurality of gate structures with a same configuration may further be implemented), a plurality of additional inner drains, and a plurality of additional groups of inner nanosheet channel structures interconnecting the plurality of additional inner sources and the plurality of additional inner drains (as described in [0030] when the structure of Fig. 1A is implemented as an array of stacked FETs);
a plurality of additional n-type outer field effect transistors having a plurality of additional outer sources, a plurality of additional outer drains, and a plurality of additional groups of outer nanosheet channel structures interconnecting the plurality of additional outer sources and the plurality of additional outer drains;
a plurality of additional metal gate stacks between the plurality of additional inner sources and the plurality of additional inner drains and between the plurality of additional outer sources and the plurality of additional outer drains, the plurality of additional metal gate stacks at least partially surrounding the plurality of additional groups of inner and outer nanosheet channel structures (see described in [0030]); and
a plurality of additional first electrically conductive pathways coupling the plurality of additional inner drains and the plurality of additional outer drains and forming a plurality of additional output nodes (as modified by Shao, wherein any number of desired inverters may have any number of inner and outer drains electrically coupled to form an output node); and
wherein:
the isolation region extends between the plurality of additional inner field effect transistors and the plurality of additional outer field effect transistors, the plurality of additional metal gate stacks each having a dielectric region adjacent the isolation region (see described in [0030]);
the plurality of additional outer sources are electrically coupled to the first rail (see [0049]);
the plurality of additional inner sources are electrically coupled to the second rail (see [0049]).
Regarding Claim 6, Yang as modified by Shao teaches the semiconductor structure of Claim 5, further comprising a power supply coupled to the first rail (see [0049]).
Regarding Claim 7, Yang as modified by Shao teaches the semiconductor structure of Claim 4, wherein the second rail comprises a buried power rail (see described in [0049], wherein interconnects 113 and 115 are connected to “bottom power rails” on an opposite side of substrate 106).
Response to Arguments
Applicant's arguments filed December 19, 2025 have been fully considered but they are not persuasive.
Applicant argues that the gate dielectrics (114A and 114B) of Yang are not positioned adjacent to the isolation structure (120). Examiner notes that the term “adjacent” may be interpreted broadly to mean “next to.” Fig. 1B of Yang gives a cross-sectional view in which gate dielectrics (114A and 114B), which may be interpreted as “dielectric regions” are positioned vertically adjacent to an isolation region (120).
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., an isolation region being “adjacent” to the metal gate stack) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Furthermore, Xie teaches an isolation region (146) being formed between the inner FET and outer FET as cited in claim 1. Applicant further argues that the dielectric region (120 and 146), which is adjacent to the metal gate stack, does not lie “within” the metal gate stack nor does it function as part of the gate dielectric configuration. Examiner notes that the liner layer (120) is a dielectric region which is vertically stacked with the metal gate structures and thus is interpreted as part of the metal gate stack. Furthermore, the dielectric region being implemented to “function as part of the gate dielectric configuration” is not explicitly cited in the claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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