DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This communication is considered fully responsive to the Arguments/Remarks filed on 6/12/2026.
Claims 1, 3-8, 10-15, 17-22, 24, 25, and 36-39 have been amended.
Claims 1, 3-8, 10-15, 17-22, 24, 25 and 36-39 rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph are withdrawn. However there are new 112(b) issues to be addressed.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8, 15, 22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-7, 15, 17-21, 36 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 recites “cause storage of a timestamp of the transmission in external storage circuitry that is shared between the NIC and at least one main processor circuit”. It also states in the preamble that the NIC comprising of at least one processor circuit to be programmed by the machine-readable instructions. It is not clear how if the external storage circuitry is shared between the NIC and one of its components, at least one processor circuit. Is “at least one processor circuit” in bold above in the cause storage limitation different than the “at least one processor circuit” in italic that is part of the NIC?. Its dependent claims are also rejected for the same reasoning.
Claim 15 recites “at least one processor circuit” and then “at least one main processor circuit”. It is not clear if these the same processor circuit or different ones. Its dependent claims are also rejected for the same reasoning.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8, 15, 22 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Guiavarc’h et al. (US 2024/0320195, hereinafter “Guiavarc’h” in view of Marcondes et al. (US 2008/0144624 hereinafter “Marcondes”) and further in view of “Kasichainula” (US 2021/0014177).
For claims 1, 8, 15 and 22, Guiavarc’h discloses Network interface circuitry (NIC) comprising:
machine-readable instructions (The operating system 10 controls the execution of the application 12. The applications 12a, 12b constitute (or comprise) computer programs (or computer-readable program code) according to particular embodiments of the invention, these computer programs comprising instructions to implement methods according to particular embodiments of the invention; see Guiavarc’h par. 0151); and
at least one processor circuit to be programmed by the machine-readable instructions to (these instructions may form an application program tangibly embodied on a processor-readable medium. Instructions to perform methods according to particular embodiments of the invention may be, for example, in hardware, firmware, software, or a combination thereof. Instructions may be found in, for example, an operating system, a separate application, or a combination of the two; see Guiavarc’h par. 0151):
permit a descriptor of data to be overwritten before transmission of the data (in the sending step S56, the second computing device DV2 sends the second version of the object descriptor file ODF2 to the cloud CL, thereby causing overwriting of the first updated version of the object descriptor file ODF1 at the cloud. A synchronization conflict thus occurs at the sending step S56. The second version of the object descriptor file ODF2 overwrites the first version of the object descriptor file ODF1 at the cloud whereas the second timestamp t2 of the object descriptor 0B2 is earlier than the first timestamp t1 of object descriptor 0B1. Therefore, the object descriptor file version of the cloud does not include the latest updated value v1 and the latest timestamp t1 of the content; see Guiavarc’h par. 0239-0240, 0185-0187); and
Guiavarc’h does not explicitly disclose cause storage of a timestamp of the transmission in external storage circuitry that is shared between the NIC and at least one main processor circuit, the timestamp indicative of a time at which the data was transmitted. Marcondes discloses cause storage of a timestamp of the transmission in external storage circuitry that is shared between the NIC and at least one main processor circuit, the timestamp indicative of a time at which the data was transmitted (the NIC processor may place a timestamp (215) indicating an arrival time of the data packet (200) in the packet header (210). In one or more embodiments, placing the timestamp (215) in the packet header (210) allows the data packet (200) to be transferred into system memory in exactly the same manner as a non-timestamped data packet. Upon accessing the data packet (200) in System memory, a client may then process the packet header (210) to obtain the timestamp (215). Any client not using the timestamp (215) may simply ignore the additional header information. Alternatively, the NIC processor may transfer timestamps and data packets into system memory separately, i.e., in separate data structures. For example, as shown in FIG. 2B, one or more timestamps (e.g., timestamp A (220), times tamp N (225)) are stored in data structure X (240), and one or more data packets (e.g., data packet A (230), data packet N (235)) are stored in data structure Y (245); see Marcondes par. 0026-0027). It would have been obvious to the ordinary skilled in the art before the effective filing date to use Marcondes's arrangement in Guiavarc’h's invention to improve performance of tasks executing in the computer system by offloading timestamping from the system processor and system clock to the NIC processor and NIC clock, therefore more system processing cycles are available for execution of other tasks (see Marcondes par. 0036).
Specifically for claim 8, Guiavarc’h discloses memory access control circuitry to: (The memories 8a, 8b are non-transitory (or nonvolatile) computer readable storage media (or recording media) in accordance with particular embodiments of the present invention; see Guiavarc’h par. 0148 and Fig. 1).
Guiavarc’h does not explicitly disclose a cache to store data associated with a descriptor; and. Kasichainula discloses a cache to store data associated with a descriptor (a descriptor cache 410; see Kasichainula par. 0092 and Fig. 4 ); and. It would have been obvious to the ordinary skilled in the art before the effective filing date to use Kasichainula's arrangement in Guiavarc’h's invention to provide deterministic packet scheduling and DMA for time sensitive networking (see Kasichainula par. 0001).
Specifically for claim 15, Guiavarc’h discloses At least one non-transitory computer readable medium comprising instructions to cause at least one processor circuit of network interface circuitry (NIC) to: (there is provided a non-transitory storage medium carrying instructions of program code for executing the method of the first and/or second aspects; see Guiavarc’h par. 0059).
For claim 36, the combination of Guiavarc’h and Marcondes does not explicitly disclose The NIC of claim 1, wherein the external storage circuitry is first storage circuitry, and the at least one processor circuit includes one or more of: at least one of a central processor unit (CPU), a graphics processor unit (GPU), or a digital signal processor (DSP), the at least one of the CPU, the GPU, or the DSP having control circuitry to control data movement within the at least one processor circuit, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a first result of the one or more first operations; a Field Programmable Gate Array (FPGA), the FPGA including first logic gate circuitry, a plurality of configurable interconnections, and second storage circuitry, the first logic gate circuitry and the interconnections to perform one or more second operations, the second storage circuitry to store a second result of the one or more second operations; or Application Specific Integrated Circuitry (ASIC) including second logic gate circuitry to perform one or more third operations, one or more of the at least one processor circuit to perform at least one of the first operations, the second operations, or the third operations to instantiate the machine-readable instructions. Kasichainula discloses The NIC of claim 1, wherein the external storage circuitry is first storage circuitry, and the at least one processor circuit includes one or more of: at least one of a central processor unit (CPU), a graphics processor unit (GPU), or a digital signal processor (DSP), the at least one of the CPU, the GPU, or the DSP having control circuitry to control data movement within the at least one processor circuit, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a first result of the one or more first operations; a Field Programmable Gate Array (FPGA), the FPGA including first logic gate circuitry, a plurality of configurable interconnections, and second storage circuitry, the first logic gate circuitry and the interconnections to perform one or more second operations, the second storage circuitry to store a second result of the one or more second operations (The processor(s) of processor circuitry 1402 may include, for example, one or more processor cores (CPUs), application processors, GPUs, RISC processors, Acorn RISC Machine (ARM) processors, CISC processors, one or more DSPs, one or more FPGAs, one or more PLDs, one or more ASICs, one or more baseband processors, one or more radio-frequency integrated circuits (RFIC), one or more microprocessors or controllers, or any suitable combination thereof. The processors (or cores) of the processor circuitry 1402 may be coupled with or may include memory/storage and may be configured to execute instructions stored in the memory/storage to enable various applications or operating systems to run on the platform 1400; see Kasichainula par. 0180); or Application Specific Integrated Circuitry (ASIC) including second logic gate circuitry to perform one or more third operations, one or more of the at least one processor circuit to perform at least one of the first operations, the second operations, or the third operations to instantiate the machine-readable instructions (In some embodiments, the memory circuitry 1404 and/or storage circuitry 1408 may be divided into one or more trusted memory regions for storing applications or software modules of the TEE 1490. Although the instructions 1482 are shown as code blocks included in the memory circuitry 1404 and the computational logic 1483 is shown as code blocks in the storage circuitry 1408, it should be understood that any of the code blocks may be replaced with hardwired circuits, for example, built into an FPGA, ASIC, or some other suitable circuitry; see Kasichainula par. 0193-0194). It would have been obvious to the ordinary skilled in the art before the effective filing date to use Kasichainula's arrangement in Guiavarc’h's invention to provide deterministic packet scheduling and DMA for time sensitive networking (see Kasichainula par. 0001).
Allowable Subject Matter
Claims 3-6, 10-13, 17-20, 24, 25, 37-39 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and also if they overcome the 112b rejections above.
The following is one of an examiner’s statement of reasons for allowance: claims 3-6, 10-13, 17-20, 24, 25, 37-39 would be allowable because the closest prior arts listed above either alone or in combination, fail to anticipate or render obvious, the claimed invention of “parse the descriptor to determine a pointer indicative of a first address in the external storage circuitry that is reserved for storage of the timestamp; and in response to the transmission of the data, cause storage of the timestamp at the first address”, in combination with all other limitations in the claim(s) above as defined by applicant.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAE S LEE whose telephone number is (571)272-8236. The examiner can normally be reached 8:30AM - 5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey Rutkowski can be reached at (571) 270-1215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHAE S LEE/Primary Examiner, Art Unit 2415
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