DETAILED ACTION
Claims 1-2 and 4-22 are presented for examination. Claims 1, 5, 9-11, 13-14, 16-17, and 21 are amended. Claim 3 is cancelled. Claim 22 is new. This office action is response to the submission on 10/21/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/22/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings filed on 10/21/2025 are acceptable for examination proceedings.
Specification
The corrected specification entered 10/21/2025 is acceptable for examination proceedings. The objection is withdrawn.
Response to Arguments
With respect to Claim Objections:
Applicant’s arguments, see page 8 of applicant response filed 10/21/2025, with respect to claims 5, 9, 11, and 17 have been fully considered and are persuasive in light of the amendments to the claim. The objections to the claims have been withdrawn.
With respect to 35 U.S.C. §112(a) Rejection:
Applicant’s arguments, see page 8 of applicant response filed 10/21/2025, with respect to claims 1-21 have been fully considered and are persuasive in light of the amendments to the claims. The 35 U.S.C. §112(a) rejection of the claims has been withdrawn.
With respect to 35 U.S.C. §103 Rejection:
Applicant’s arguments, see pages 8-10 of applicant response filed 10/21/2025, with respect to claim 1 have been fully considered and are not persuasive. Applicant argues that Herdrich does not teach the limitation of adjusting memory bandwidth. Herdrich is not relied upon to teach this claim limitation, Hunt et al. (US20190190805A1) is. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments, see pages 10-11 of applicant response filed 10/21/2025, with respect to claim 1 have been fully considered and are not persuasive. Applicant argues that Herdrich and Hu are not properly combinable because Examiner did not provide rationale as to why it would be obvious to combine the teachings. Examiner disagrees. As cited in previous office action, a PIDNN may have perfect performance in many situations, providing an alternative to standard PID controllers which may use a neural network to determine the PID parameters. Additionally, Hu states that the PIDNN can do learning and control duties at the same time and that the training time is short, which would save the user time compared to using a PID controller of Herdrich in Hu [Pages 443-444, Conclusion] "From the introduction and the test results displayed above, we can get conclusion as follows. PIDNN not only have Pneurons but also have I-neurons and D-neurons in its hidden layers. PIDNN is a dynamic multi-layer network and suits to control multivariable objects. PIDNN can do learning and control duties at the same time. The training time of PIDNN is short and the final control result is very good."
Applicant’s arguments, see page 11 of applicant response filed 10/21/2025, with respect to claim 14 have been fully considered and are not persuasive. The same responses above apply mutatis mutandis to claim 14.
Applicant’s arguments, see page 11 of applicant response filed 10/21/2025, with respect to claim 5 have been fully considered and are not persuasive. Applicant argues that the teachings of Herdrich, Hu, and West are not properly combinable but provides no argument for this aside from the argument with respect to Herdrich and Hu on pages 10-11.
Applicant’s arguments, see pages 11-12 of applicant response filed 10/21/2025, with respect to claim 5 have been fully considered and are not persuasive. Applicant argues that West fails to teach consideration of a priority of a workload in determining CPI. Applicant’s arguments with respect to claim 5 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments, see page 12 of applicant response filed 10/21/2025, with respect to claim 5 have been fully considered and are not persuasive. Applicant argues that Herdrich fails to teach adjustment of memory bandwidth. Applicant’s arguments with respect to claim 5 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments, see page 13 of applicant response filed 10/21/2025, with respect to claim 17 have been fully considered and are not persuasive. The same responses above apply mutatis mutandis to claim 17.
Applicant’s arguments, see page 13 of applicant response filed 10/21/2025, with respect to claim 12 have been fully considered and are not persuasive. Applicant argues that the teachings of Herdrich, Hu, and Choi are not properly combinable but provides no argument for this aside from the argument with respect to Herdrich and Hu on pages 10-11.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-11, and 13-22 are rejected under 35 U.S.C. 103 as being unpatentable over Herdrich et al. (US20160077844A1), in view of HU, Huailin, GUO, Xiucai, and SHU, Hua. "PID neural networks in multivariable systems", Proceedings of the IEEE international Symposium on Intelligent Control, IEEE, October 2002, 5 pages. (Hereinafter referred to as “Hu”, citations provided to applicant provided copy), further in view of Hunt et al. (US20190190805A1), further in view of West et al. (US20110055479A1).
Claim 1:
Herdrich teaches “An apparatus comprising: an interface and circuitry, coupled to the interface, to utilize a proportional, derivative, integral (Herdrich teaches a network interface 730 in Herdrich [0082] "Main memory 715 may be implemented in various memory sources, such as dynamic random-access memory (DRAM), hard disk drive (HDD) 720, solid state disk 725 based on NVRAM technology, or a memory source located remotely from the computer system via network interface 730 or via wireless interface 740 containing various storage devices and technologies."; Herdrich [0031] "In one embodiment, PI controller 120 is coupled to power/performance setting logic 110 via 111 to receive a set point (e.g., power consumption target, CPI target value). In one embodiment, the set point is for a CPI value of a core associated with a high priority application."; Herdrich teaches that PI controller 120 may be a PID controller in Herdrich [0045] "In one embodiment, operating point control 128 sets an operating point (a combination of P-state and T-state) based on determination from decision logic 127. In one embodiment, decision logic 127 further operates in conjunction with information including misses per instruction, a number of cache line fills, and a number of cache line evictions to avoid overcorrecting by PID controller 120."; Herdrich [0054-0055] "In one embodiment, processing logic monitors CPI of a core executing a high priority program i.e. the CPI of the high priority program may be the set point or target parameter (process block 204). In one embodiment, processing logic also monitors information, such as, for example, misses per instruction (MPI), cache line fills, cache line evictions, etc.In one embodiment, processing logic compares data from the monitoring with the set point (process block 205). In one embodiment, no action is taken if the performance data are within a predetermined range. if the performance data are higher than the set point, a PI control mechanism generates an output based at least on the difference (error) between the set point and performance data (process block 206). In one embodiment, processing logic determines, based on the output, whether to increase a T-state (less enforcement) or to decrease a T-state (more enforcement) of cores associated with low priority programs i.e. the PID controller adjusts a parameter of a first workload to reach a target parameter of a second workload (process block 207)."; Herdrich teaches PID controller 120 is used in conjunction with the flow diagram Fig. 2 in Herdrich [0049] "FIG. 2 is a flow diagram of one embodiment of a process to control resource contention to shared resources. The process is performed by processing logic that may comprise hardware (circuitry, dedicated logic, etc.), software (such as is run on a general purpose computer system or a dedicated machine), or a combination of both. In one embodiment, the process is performed in conjunction with a PI controller (e.g., PI controller 120 with respect to FIG. 1). In one embodiment, the process is performed by a computer system with respect to FIG. 5."
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Herdrich does not appear to explicitly disclose “An apparatus comprising: circuitry to utilize a proportional, derivative, integral neural network (PIDNN) controller to adjust one or more parameters” However, Hu does teach this limitation (Hu [Page 442 section IV - Page 443] "PIDNN can control the multivariable objects. An example is as follows. A strong-coupled nonlinear object is
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A PIDNN is used to control this 2-variable object as shown in Fig 4. If the n=n'=0.1, The sample point m=100, Let R10, R01 and Rsin input system to training PIDNN. After 300 training steps, the system output responses are shown in Fig.5. The Fig.5(a) is the response for R10, the Fig.5 (b) is the response for R01, the Fig.5(c) is the response for Rsin and the fig.5 (d) is the training aim curve in the first 30 steps.
It is known from Fig.5(a), (b) and (c) that PIDNN has controlled this coupled nonlinear system perfectly. The system output responses are very quick, the overheads are very small and no static error. It is also known from Fig,5 (d) that the training time of PIDNN is short and the training aim J is achieved quickly and monotonically."
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Herdrich and Hu are analogous art because they are from the same field of endeavor of controlling a variable to achieve a target. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having teachings of Herdrich and Hu before him/her, to modify the teachings of a method and apparatus for controlling resource contention to shared resources by regulating clock throttling and power of a processor of Herdrich to include the teachings of a PID neural network including a P neuron, I neuron, and D neuron of Hu because adding the PID neural network of Hu would allow the controller to provide perfect performance in many situations as described in Hu [Page 440, Section I] “The hybrid systems of PlD controller and neural networks. (NNs) have become a new research area in automatic control field, Normally, the PID controllers are helped by NNs. That is, using NNs to choose or adjust the P, land D parameters of the PID controllers, These hybrid systems want to improve the performances of the conventional PID controllers but the other problems are produced at the same time such as the complicated structures, the constringency of the NNs, etc. This paper will introduce a new neural network that is called PID neural networks (PIDNN), The PIDNN isn't a PlD controller or a hybrid system of the PID and the NNs but is a neural network because its structure, algorithms and theory base are those of NNs. The PIDNN also different from other NNs and its most obvious properties different from other NNs are that the functions in the hidden layer of the PIDNN are the proportional (P) neuron, the integral (I) neuron and the derivative (D) neuron respectively. A lot of research results have been taken and the results prove that PIDNN has perfect performance in many situations.”
Neither Herdrich or Hu appear to explicitly teach “wherein the adjusted one or more parameters comprises memory bandwidth.” However, Hunt in view of West does teach this claim limitation (Hunt teaches reducing the memory bandwidth allocated to a non latency sensitive program i.e. low priority workload in order to meet a target memory latency of a latency sensitive program i.e. high priority workload in Hunt [0026-0028] "FIG. 3 is a flow diagram illustrating a method for operating a system having a SLO scheduler in accordance with some embodiments. In FIG. 3, the method 300 includes measuring memory bandwidth use (MBU) by all processes at block 301. At block 302, memory latency (ML) is measured for all processes... At block 303, if none of the LS processes are consuming their respective MBU floors (“no” leaving block 303), the LS processes are not abundantly active with respect to MBU. At block 305, the system determines whether any LS process is throttled. If so, the system at 308 reduces or eliminates throttling on the throttled LDS processes. At block 306, the system determines whether the system ML is at or below a contracted latency. The system ML is an example of a global target. If so, at block 307 the system determines whether the system ML is substantially below the contracted latency. If so, the system has ML available for consumption, and at block 308, the system reduces throttling on LS processes and/or NLS processes to take advantage of the low system ML. If the system ML is not at or below the contracted latency, starting at block 309 the system takes further steps. At block 309, the system determines whether every NLS process is at a maximum throttle value (maximally throttled). If not, at block 311, the SLO scheduler increases throttling on one or more NLS processes that are not already maximally throttled."
Herdrich, Hu, and Hunt are analogous art because they are from the same field of endeavor of controlling a variable to achieve a target. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having teachings of Herdrich, Hu, and Hunt before him/her, to modify the teachings of a method and apparatus for controlling resource contention to shared resources by regulating clock throttling and power of a processor of Herdrich modified to include the teachings of a PID neural network including a P neuron, I neuron, and D neuron of Hu to include the teachings of adjusting a memory bandwidth allocated to an NLS process in order to achieve a target latency of all processes of Hunt because adding the Scheduling memory bandwidth based on quality of service floorbackground of Hunt would allow for non-latency sensitive processes to use more memory bandwidth as long as latency sensitive processes meet their memory bandwidth usage floor as described in Hunt [0011] "If the system throttles back the NLS processes until the system achieves the contracted latency, which is not a minimum memory latency possible, that is as far as the system throttles the NLS processes. That is, the system guarantees that the system will deliver the LR floor memory bandwidth use or a nominal latency (the contracted latency) and the system is thereby optimized so that the system does not overly penalize the NLS processes by completely stopping operation of the NLS processes in an effort to get to a bare minimum latency to try to get more memory bandwidth to the LS processes. The system allows the NLS processes to use more memory bandwidth and drive the system latency above the contract latency as long as the latency does not go so high that the LS processes fail to meet their LR floor. According to some embodiments, success in such a system is managing the NLS memory bandwidth use so that either the contract system latency is achieved, or the bandwidth floor is met for the LS processes at substantially all times. In other embodiments, both of these conditions are met at substantially all times."
West teaches that cache interference and memory interconnect bandwidth influences CPI i.e. the bandwidth adjustment of Hunt influences the CPI of applications in West [0055-0056] "In an alternate embodiment, the effective CPU time is given by:
e=q*(ideal CPI/current CPI) (Eq. 10)
wherein e is the effective CPU time, q is the total CPU time, i.e., the time spent executing in the most recent execution interval, the ideal CPI is the average number of cycles (clock ticks) that would elapse for each instruction if there were no cache interference or memory interconnect contention, and the current CPI is the average number of cycles (clock ticks) that elapsed for each instruction executed during the most recent execution interval. Equation 10 therefore takes into account not just the time required to repopulate cache lines evicted from the LLC by other threads, but also time spent waiting for the memory interconnect to become available when memory interconnect contention becomes an issue, as described above with reference to FIG. 4."; West [0059-0060] "The values of ideal CPI and current CPI could easily be replaced with their inverses, i.e., instructions per cycle (IPC), and Equation 10 modified by inverting the fraction to give:
e=q*(current IPC/ideal IPC) (Eq. 11)
which is equivalent to Equation 10. Conceptually, the effective CPU time is being defined as the actual execution time, q, times a value representative of the reduction of speed of execution of the thread attributable to any effect caused by other threads sharing the same cache. The value takes into account not only cache contention, but all sources of contention, including any other shared microarchitectural resources, including memory interconnect bandwidth"
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Herdrich, Hu, Hunt, and West are analogous art because they are from the same field of endeavor of controlling a variable to achieve a target. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having teachings of Herdrich, Hu, and West before him/her, to modify the teachings of a method and apparatus for controlling resource contention to shared resources by regulating clock throttling and power of a processor of Herdrich modified to include the teachings of a PID neural network including a P neuron, I neuron, and D neuron of Hu further modified to include the adjusting a memory bandwidth allocated to an NLS process in order to achieve a target latency of all processes of Hunt to include the teachings of memory bandwidth adjustment influencing CPI of West because adding the memory bandwidth modification of West would allow the controller to modify the bandwidth allocated to a process which would reduce the CPI, improving the performance as described in West [0035] “FIG. 4 shows a graph 220 having miss rate curves (MRC) 222, 224, 226, 228 that reflect by way of example the impact of available bandwidth on the relationship between thread occupancy of the LLC and the miss rate… Referring back to FIG. 4, the impact of memory interconnect contention can cause a flattening of MRC 222, as shown by MRCs 224, 226, 228 due to the reduced instructions per cycle that can be executed when memory access requests are queued by the memory interconnect controller. That is, when a greater percentage of instructions require a memory access due to reduced cache occupancy, and the memory accesses are further delayed due to memory interconnect contention, the rate of instruction processing as a whole is greatly reduced which also reduces the miss rate as expressed in terms of misses per unit time.”
Claim 2:
Herdrich in view of Hu, further in view of Hunt, further in view of West teaches “The apparatus of claim 1, wherein the second group of one or more workloads are a same, lower, or higher priority level than that of the first group of one or more workloads.” (Herdrich [0054-0055] "In one embodiment, processing logic monitors CPI of a core executing a high priority program (process block 204). In one embodiment, processing logic also monitors information, such as, for example, misses per instruction (MPI), cache line fills, cache line evictions, etc.In one embodiment, processing logic compares data from the monitoring with the set point (process block 205). In one embodiment, no action is taken if the performance data are within a predetermined range. if the performance data are higher than the set point, a PI control mechanism generates an output based at least on the difference (error) between the set point and performance data (process block 206). In one embodiment, processing logic determines, based on the output, whether to increase a T-state (less enforcement) or to decrease a T-state (more enforcement) of cores associated with low priority programs (process block 207).").
Claim 4:
Herdrich in view of Hu, further in view of Hunt, further in view of West teaches “The apparatus of claim 1, wherein the one or more target parameters for the second group of one or more workloads is based on a target parameter.” (Herdrich [0031] "In one embodiment, PI controller 120 is coupled to power/performance setting logic 110 via 111 to receive a set point (e.g., power consumption target, CPI target value). In one embodiment, the set point is for a CPI value of a core associated with a high priority application.").
Claim 5:
Herdrich in view of Hu, further in view of West teaches “The apparatus of claim 1, wherein the adjustment of one or more parameters allocated to the first group of one or more workloads based on one or more target parameters for the second group of one or more workloads comprises adjust memory bandwidth allocated to at least one low priority workload based on a target cycles per instruction (CPI) for at least one high priority workload.” (Hunt teaches reducing the memory bandwidth allocated to a non latency sensitive program i.e. low priority workload in order to meet a target memory latency of a latency sensitive program i.e. high priority workload in Hunt [0026-0028] "FIG. 3 is a flow diagram illustrating a method for operating a system having a SLO scheduler in accordance with some embodiments. In FIG. 3, the method 300 includes measuring memory bandwidth use (MBU) by all processes at block 301. At block 302, memory latency (ML) is measured for all processes... At block 303, if none of the LS processes are consuming their respective MBU floors (“no” leaving block 303), the LS processes are not abundantly active with respect to MBU. At block 305, the system determines whether any LS process is throttled. If so, the system at 308 reduces or eliminates throttling on the throttled LDS processes. At block 306, the system determines whether the system ML is at or below a contracted latency. The system ML is an example of a global target. If so, at block 307 the system determines whether the system ML is substantially below the contracted latency. If so, the system has ML available for consumption, and at block 308, the system reduces throttling on LS processes and/or NLS processes to take advantage of the low system ML. If the system ML is not at or below the contracted latency, starting at block 309 the system takes further steps. At block 309, the system determines whether every NLS process is at a maximum throttle value (maximally throttled). If not, at block 311, the SLO scheduler increases throttling on one or more NLS processes that are not already maximally throttled."
West teaches that cache interference and memory interconnect bandwidth influences CPI i.e. the bandwidth adjustment of Hunt influences the CPI of applications in West [0055-0056] "In an alternate embodiment, the effective CPU time is given by:
e=q*(ideal CPI/current CPI) (Eq. 10)
wherein e is the effective CPU time, q is the total CPU time, i.e., the time spent executing in the most recent execution interval, the ideal CPI is the average number of cycles (clock ticks) that would elapse for each instruction if there were no cache interference or memory interconnect contention, and the current CPI is the average number of cycles (clock ticks) that elapsed for each instruction executed during the most recent execution interval. Equation 10 therefore takes into account not just the time required to repopulate cache lines evicted from the LLC by other threads, but also time spent waiting for the memory interconnect to become available when memory interconnect contention becomes an issue, as described above with reference to FIG. 4."; West [0059-0060] "The values of ideal CPI and current CPI could easily be replaced with their inverses, i.e., instructions per cycle (IPC), and Equation 10 modified by inverting the fraction to give:
e=q*(current IPC/ideal IPC) (Eq. 11)
which is equivalent to Equation 10. Conceptually, the effective CPU time is being defined as the actual execution time, q, times a value representative of the reduction of speed of execution of the thread attributable to any effect caused by other threads sharing the same cache. The value takes into account not only cache contention, but all sources of contention, including any other shared microarchitectural resources, including memory interconnect bandwidth"), and
“The apparatus of claim 1, wherein the adjustment of one or more parameters allocated to the first group of one or more workloads based on one or more target parameters for the second group of one or more workloads comprises adjust (Herdrich [0031] "In one embodiment, PI controller 120 is coupled to power/performance setting logic 110 via 111 to receive a set point (e.g., power consumption target, CPI target value). In one embodiment, the set point is for a CPI value of a core associated with a high priority application."; Herdrich [0054-0055] "In one embodiment, processing logic monitors CPI of a core executing a high priority program (process block 204). In one embodiment, processing logic also monitors information, such as, for example, misses per instruction (MPI), cache line fills, cache line evictions, etc.In one embodiment, processing logic compares data from the monitoring with the set point (process block 205). In one embodiment, no action is taken if the performance data are within a predetermined range. if the performance data are higher than the set point, a PI control mechanism generates an output based at least on the difference (error) between the set point and performance data (process block 206). In one embodiment, processing logic determines, based on the output, whether to increase a T-state (less enforcement) or to decrease a T-state (more enforcement) of cores associated with low priority programs (process block 207).").
Claim 6:
Herdrich in view of Hu, further in view of Hunt, further in view of West teaches “The apparatus of claim 1, wherein the neural network comprises a single input single output neural network.” (Hu [Page 441 Section III.A.] "A 2-input and 1-output PIDNN is shown in Fig.2 (a). It is a basic PIDNN and can be used to control a single variable object as shown in Fig.2 (b). It has three layers, which are the input layer, the hidden layer and the output layer. The input layer has two neurons and the output layer has one. The neurons in the input and the output layers are P neurons. The hidden layer has three neurons and these neurons are the P-neuron, the I-neuron and the D-neuron respectively. If the origin values of its connect weights are select according to some regulation, the PIDNN in original state equals to a conventional PID controller. This is one of the motivations for choosing such structure."; Examiner notes that applicant's specification defines the same type of PIDNN shown in Hu Fig. 2 as being a single input and single output system in [0028-0029].
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Claim 7:
Herdrich in view of Hu, further in view of Hunt, further in view of West teaches “The apparatus of claim 1, wherein the neural network comprises an input layer, single hidden layer, and an output layer.” (Hu [Page 441 Section III.A.] "A 2-input and 1-output PIDNN is shown in Fig.2 (a). It is a basic PIDNN and can be used to control a single variable object as shown in Fig.2 (b). It has three layers, which are the input layer, the hidden layer and the output layer. The input layer has two neurons and the output layer has one. The neurons in the input and the output layers are P neurons. The hidden layer has three neurons and these neurons are the P-neuron, the I-neuron and the D-neuron respectively. If the origin values of its connect weights are select according to some regulation, the PIDNN in original state equals to a conventional PID controller. This is one of the motivations for choosing such structure."; Hu Fig. 2 [As shown above in claim 6] teaches the PIDNN having an input, hidden, and output layer.
Claim 8:
Herdrich in view of Hu, further in view of Hunt, further in view of West teaches “The apparatus of claim 1, wherein the neural network comprises a multiple input multiple output neural network.” (Hu [Page 441 Section III.A.] "A multi-input and multi-output PlDNN consists of n coordinate basic PIDNNs and can be used to control a multivariable system. The structure of the system is shown in Fig. 3"; Hu Fig. 3 teaches a multiple input multiple output neural network.
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Claim 9:
Herdrich in view of Hu, further in view of Hunt, further in view of West teaches “The apparatus of claim 8, wherein the multiple input multiple output neural network is to receive performance targets for multiple workloads” (Herdrich [0050] "Referring to FIG. 2, the process begins by processing logic reading configurations, such as, for example, performance goal in terms of CPI (processing block 200). In one embodiment, processing logic also receive information including priorities of applications, power constraints, performance targets, etc. (process block 250)."), and
“and adjust multiple shared resources.” (West teaches that cache interference and memory interconnect bandwidth influences CPI i.e. rather than the PIDNN adjusting a throttling parameter of low priority processes, it may adjust the memory bandwidth of low priority processes in West [0055-0056] "In an alternate embodiment, the effective CPU time is given by:
e=q*(ideal CPI/current CPI) (Eq. 10)
wherein e is the effective CPU time, q is the total CPU time, i.e., the time spent executing in the most recent execution interval, the ideal CPI is the average number of cycles (clock ticks) that would elapse for each instruction if there were no cache interference or memory interconnect contention, and the current CPI is the average number of cycles (clock ticks) that elapsed for each instruction executed during the most recent execution interval. Equation 10 therefore takes into account not just the time required to repopulate cache lines evicted from the LLC by other threads, but also time spent waiting for the memory interconnect to become available when memory interconnect contention becomes an issue, as described above with reference to FIG. 4."; West [0059-0060] "The values of ideal CPI and current CPI could easily be replaced with their inverses, i.e., instructions per cycle (IPC), and Equation 10 modified by inverting the fraction to give:
e=q*(current IPC/ideal IPC) (Eq. 11)
which is equivalent to Equation 10. Conceptually, the effective CPU time is being defined as the actual execution time, q, times a value representative of the reduction of speed of execution of the thread attributable to any effect caused by other threads sharing the same cache. The value takes into account not only cache contention, but all sources of contention, including any other shared microarchitectural resources, including memory interconnect bandwidth").
Claim 10:
Herdrich in view of Hu, further in view of Hunt, further in view of West teaches “The apparatus of claim 9, wherein the multiple shared resources are interrelated and comprise two or more of: (Herdrich teaches modifying T-states as stated earlier, which are clock throttling states i.e. adjusting processor frequency in Herdrich [0036] "In one embodiment, a computer system, and in particular, processor 130 supports different operating points (e.g., performance states (P-states) and clock throttling states (T-states)), in accordance with Advanced Configuration and Power Interface (ACPI) specification (see, Advanced Configuration and Power Interface Specification, revision 3.0b, Oct. 10, 2006). In one embodiment, C0 working state of a processor is divided into P-states (performance states) in which clock rate is reduced and T-states (throttling states) in which clock rate is throttled by inserting STPCLK (stop clock) signals and thus omitting duty cycles. In one embodiment, a P-state and a T-state of processor 130 are set by changing values of one or more model specific registers (MSRs)."), and
“The apparatus of claim 9, wherein the multiple shared resources are interrelated and comprise two or more of: memory bandwidth, cache allocation, (West teaches that cache interference and memory interconnect bandwidth influences CPI i.e. rather than the PIDNN adjusting a throttling parameter of low priority processes, it may adjust the memory bandwidth of low priority processes in West [0055-0056] "In an alternate embodiment, the effective CPU time is given by:
e=q*(ideal CPI/current CPI) (Eq. 10)
wherein e is the effective CPU time, q is the total CPU time, i.e., the time spent executing in the most recent execution interval, the ideal CPI is the average number of cycles (clock ticks) that would elapse for each instruction if there were no cache interference or memory interconnect contention, and the current CPI is the average number of cycles (clock ticks) that elapsed for each instruction executed during the most recent execution interval. Equation 10 therefore takes into account not just the time required to repopulate cache lines evicted from the LLC by other threads, but also time spent waiting for the memory interconnect to become available when memory interconnect contention becomes an issue, as described above with reference to FIG. 4."; West [0059-0060] "The values of ideal CPI and current CPI could easily be replaced with their inverses, i.e., instructions per cycle (IPC), and Equation 10 modified by inverting the fraction to give:
e=q*(current IPC/ideal IPC) (Eq. 11)
which is equivalent to Equation 10. Conceptually, the effective CPU time is being defined as the actual execution time, q, times a value representative of the reduction of speed of execution of the thread attributable to any effect caused by other threads sharing the same cache. The value takes into account not only cache contention, but all sources of contention, including any other shared microarchitectural resources, including memory interconnect bandwidth").
Claim 11:
Herdrich in view of Hu, further in view of Hunt, further in view of West teaches “The apparatus of claim 1, wherein the circuitry is to tune weights of the neural network based on incremental backpropagation format.” (Hu [Page 442] "B. Back-propagation algorithms in PID neural multivariable control system. The aim of the PIDNN algorithms is to minimize
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where r~ (k) is the given-inputs and y 0 (k) is the outputs of the system as shown in Fig. 3. The weights of PIDNN is changed by gradient algorithms during on-line training process. After n training steps, the weights from hidden layer to output layer are
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where
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where n' is the !earning step, h (= J, 2, ... , n) is the variables and the output neurons' serial number, j (= l, 2, 3) is the hidden neurons' serial number in every sub-net, s = (l, 2, ... , n) is the sub-nets' serial number, k is the training step serial number and m is the sample points in every step. xsj is the output of the hidden layer's neuron. The weights from input layer to hidden layer are
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where
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where n is study step, i (= 1, 2) is hidden neurons' serial number in every sub-net, x’si is outputs of input layer's neurons and j, h, k, n, m are defined as formula (10).").
Claim 13:
Herdrich in view of Hunt, further in view of Hunt, further in view of West teaches “The apparatus of claim 1, further comprising: a server comprising: at least one processor to execute the first group of one or more workloads and the second group of one or more workloads;” (Herdrich [0016] "The method and apparatus described herein are for controlling resource contention by regulating clock throttling and power. Specifically, regulating clock throttling and power is discussed in reference to multi-core processor computer systems. However, the methods and apparatus for controlling resource contention are not so limited, as they may be implemented on or in association with any integrated circuit device or system, such as cell phones, personal digital assistants, embedded controllers, mobile platforms, desktop platforms, and server platforms, as well as in conjunction with any type of processing element, such as a core, a hardware thread, a software thread, or a logical processor, an accelerator core or other processing resource. In addition, controlling resource contention may take place in any hardware/software environment, such as an operating system or a hypervisor executing on hardware.),
“at least one memory device;” (Herdrich [0015] "Embodiments of present invention also relate to apparatuses for performing the operations herein. Some apparatuses may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, DVD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, NVRAMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus."),
“at least one device interface;” (Herdrich [0082] "Main memory 715 may be implemented in various memory sources, such as dynamic random-access memory (DRAM), hard disk drive (HDD) 720, solid state disk 725 based on NVRAM technology, or a memory source located remotely from the computer system via network interface 730 or via wireless interface 740 containing various storage devices and technologies. "),
“at least one cache device” (Herdrich [0018] "Referring to FIG. 1, the computer system includes power/performance setting logic 110, proportional-integral controller (PI controller) 120, monitor logic 160, decision logic 127, operating point control logic 128, processor 130, cache 150, and memory (not shown). In one embodiment, PI controller 120, decision logic 127, operating point control 128, cache 150, or any combination thereof is integrated in processor 130."
[AltContent: rect]
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), and
“and at least one cache device, wherein the one or more parameters allocated to the first group of one or more workloads comprises one or more of: memory bandwidth allocation of the at least one memory device, (West teaches that cache interference and memory interconnect bandwidth influences CPI i.e. rather than the PIDNN adjusting a throttling parameter of low priority processes, it may adjust the memory bandwidth of low priority processes in West [0055-0056] "In an alternate embodiment, the effective CPU time is given by:
e=q*(ideal CPI/current CPI) (Eq. 10)
wherein e is the effective CPU time, q is the total CPU time, i.e., the time spent executing in the most recent execution interval, the ideal CPI is the average number of cycles (clock ticks) that would elapse for each instruction if there were no cache interference or memory interconnect contention, and the current CPI is the average number of cycles (clock ticks) that elapsed for each instruction executed during the most recent execution interval. Equation 10 therefore takes into account not just the time required to repopulate cache lines evicted from the LLC by other threads, but also time spent waiting for the memory interconnect to become available when memory interconnect contention becomes an issue, as described above with reference to FIG. 4."; West [0059-0060] "The values of ideal CPI and current CPI could easily be replaced with their inverses, i.e., instructions per cycle (IPC), and Equation 10 modified by inverting the fraction to give:
e=q*(current IPC/ideal IPC) (Eq. 11)
which is equivalent to Equation 10. Conceptually, the effective CPU time is being defined as the actual execution time, q, times a value representative of the reduction of speed of execution of the thread attributable to any effect caused by other threads sharing the same cache. The value takes into account not only cache contention, but all sources of contention, including any other shared microarchitectural resources, including memory interconnect bandwidth").
Claim 14:
Herdrich teaches “At least one non-transitory computer-readable medium comprising instructions stored thereon,” (Herdrich [0015] "Embodiments of present invention also relate to apparatuses for performing the operations herein. Some apparatuses may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, DVD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, NVRAMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus."), and
“that if executed by one or more processors, cause the one or more processors to: cause utilization of a proportional, integral, derivative in a system comprising the PIDNN controller and an interface to the PIDNN controller, to adjust one or more parameters allocated to a first group of one or more workloads based on one or more target parameters for a second group of one or more workloads.” (Herdrich [0031] "In one embodiment, PI controller 120 is coupled to power/performance setting logic 110 via 111 to receive a set point (e.g., power consumption target, CPI target value). In one embodiment, the set point is for a CPI value of a core associated with a high priority application."; Herdrich teaches that PI controller 120 may be a PID controller in Herdrich [0045] "In one embodiment, operating point control 128 sets an operating point (a combination of P-state and T-state) based on determination from decision logic 127. In one embodiment, decision logic 127 further operates in conjunction with information including misses per instruction, a number of cache line fills, and a number of cache line evictions to avoid overcorrecting by PID controller 120."; Herdrich [0054-0055] "In one embodiment, processing logic monitors CPI of a core executing a high priority program i.e. the CPI of the high priority program may be the set point or target parameter (process block 204). In one embodiment, processing logic also monitors information, such as, for example, misses per instruction (MPI), cache line fills, cache line evictions, etc.In one embodiment, processing logic compares data from the monitoring with the set point (process block 205). In one embodiment, no action is taken if the performance data are within a predetermined range. if the performance data are higher than the set point, a PI control mechanism generates an output based at least on the difference (error) between the set point and performance data (process block 206). In one embodiment, processing logic determines, based on the output, whether to increase a T-state (less enforcement) or to decrease a T-state (more enforcement) of cores associated with low priority programs i.e. the PID controller adjusts a parameter of a first workload to reach a target parameter of a second workload (process block 207)."; Herdrich teaches PID controller 120 is used in conjunction with the flow diagram Fig. 2 in Herdrich [0049] "FIG. 2 is a flow diagram of one embodiment of a process to control resource contention to shared resources. The process is performed by processing logic that may comprise hardware (circuitry, dedicated logic, etc.), software (such as is run on a general purpose computer system or a dedicated machine), or a combination of both. In one embodiment, the process is performed in conjunction with a PI controller (e.g., PI controller 120 with respect to FIG. 1). In one embodiment, the process is performed by a computer system with respect to FIG. 5.").
Herdrich does not appear to explicitly disclose “cause utilization of a proportional, integral, derivative neural network (PIDNN) controller in a system comprising the PIDNN controller and an interface to the PIDNN controller, to adjust one or more parameters” However, Hu does teach this limitation (Hu [Page 442 section IV - Page 443] "PIDNN can control the multivariable objects. An example is as follows. A strong-coupled nonlinear object is
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where nonlinear parts are
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If there are three types of inputs on the system, they are
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A PIDNN is used to control this 2-variable object as shown in Fig 4. If the n=n'=0.1, The sample point m=100, Let R10, R01 and Rsin input system to training PIDNN. After 300 training steps, the system output responses are shown in Fig.5. The Fig.5(a) is the response for R10, the Fig.5 (b) is the response for R01, the Fig.5(c) is the response for Rsin and the fig.5 (d) is the training aim curve in the first 30 steps.
It is known from Fig.5(a), (b) and (c) that PIDNN has controlled this coupled nonlinear system perfectly. The system output responses are very quick, the overheads are very small and no static error. It is also known from Fig,5 (d) that the training time of PIDNN is short and the training aim J is achieved quickly and monotonically.").
Herdrich and Hu are analogous art because they are from the same field of endeavor of controlling a variable to achieve a target. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having teachings of Herdrich and Hu before him/her, to modify the teachings of a method and apparatus for controlling resource contention to shared resources by regulating clock throttling and power of a processor of Herdrich to include the teachings of a PID neural network including a P neuron, I neuron, and D neuron of Hu because adding the PID neural network of Hu would allow the controller to provide perfect performance in many situations as described in Hu [Page 440, Section I] “The hybrid systems of PlD controller and neural networks. (NNs) have become a new research area in automatic control field, Normally, the PID controllers are helped by NNs. That is, using NNs to choose or adjust the P, land D parameters of the PID controllers, These hybrid systems want to improve the performances of the conventional PID controllers but the other problems are produced at the same time such as the complicated structures, the constringency of the NNs, etc. This paper will introduce a new neural network that is called PID neural networks (PIDNN), The PIDNN isn't a PlD controller or a hybrid system of the PID and the NNs but is a neural network because its structure, algorithms and theory base are those of NNs. The PIDNN also different from other NNs and its most obvious properties different from other NNs are that the functions in the hidden layer of the PIDNN are the proportional (P) neuron, the integral (I) neuron and the derivative (D) neuron respectively. A lot of research results have been taken and the results prove that PIDNN has perfect performance in many situations.”
Neither Herdrich or Hu appear to explicitly teach “wherein the adjusted one or more parameters comprises memory bandwidth.” However, Hunt in view of West does teach this claim limitation (Hunt teaches reducing the memory bandwidth allocated to a non latency sensitive program i.e. low priority workload in order to meet a target memory latency of a latency sensitive program i.e. high priority workload in Hunt [0026-0028] "FIG. 3 is a flow diagram illustrating a method for operating a system having a SLO scheduler in accordance with some embodiments. In FIG. 3, the method 300 includes measuring memory bandwidth use (MBU) by all processes at block 301. At block 302, memory latency (ML) is measured for all processes... At block 303, if none of the LS processes are consuming their respective MBU floors (“no” leaving block 303), the LS processes are not abundantly active with respect to MBU. At block 305, the system determines whether any LS process is throttled. If so, the system at 308 reduces or eliminates throttling on the throttled LDS processes. At block 306, the system determines whether the system ML is at or below a contracted latency. The system ML is an example of a global target. If so, at block 307 the system determines whether the system ML is substantially below the contracted latency. If so, the system has ML available for consumption, and at block 308, the system reduces throttling on LS processes and/or NLS processes to take advantage of the low system ML. If the system ML is not at or below the contracted latency, starting at block 309 the system takes further steps. At block 309, the system determines whether every NLS process is at a maximum throttle value (maximally throttled). If not, at block 311, the SLO scheduler increases throttling on one or more NLS processes that are not already maximally throttled."
Herdrich, Hu, and Hunt are analogous art because they are from the same field of endeavor of controlling a variable to achieve a target. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having teachings of Herdrich, Hu, and Hunt before him/her, to modify the teachings of a method and apparatus for controlling resource contention to shared resources by regulating clock throttling and power of a processor of Herdrich modified to include the teachings of a PID neural network including a P neuron, I neuron, and D neuron of Hu to include the teachings of adjusting a memory bandwidth allocated to an NLS process in order to achieve a target latency of all processes of Hunt because adding the Scheduling memory bandwidth based on quality of service floorbackground of Hunt would allow for non-latency sensitive processes to use more memory bandwidth as long as latency sensitive processes meet their memory bandwidth usage floor as described in Hunt [0011] "If the system throttles back the NLS processes until the system achieves the contracted latency, which is not a minimum memory latency possible, that is as far as the system throttles the NLS processes. That is, the system guarantees that the system will deliver the LR floor memory bandwidth use or a nominal latency (the contracted latency) and the system is thereby optimized so that the system does not overly penalize the NLS processes by completely stopping operation of the NLS processes in an effort to get to a bare minimum latency to try to get more memory bandwidth to the LS processes. The system allows the NLS processes to use more memory bandwidth and drive the system latency above the contract latency as long as the latency does not go so high that the LS processes fail to meet their LR floor. According to some embodiments, success in such a system is managing the NLS memory bandwidth use so that either the contract system latency is achieved, or the bandwidth floor is met for the LS processes at substantially all times. In other embodiments, both of these conditions are met at substantially all times."
West teaches that cache interference and memory interconnect bandwidth influences CPI i.e. the bandwidth adjustment of Hunt influences the CPI of applications in West [0055-0056] "In an alternate embodiment, the effective CPU time is given by:
e=q*(ideal CPI/current CPI) (Eq. 10)
wherein e is the effective CPU time, q is the total CPU time, i.e., the time spent executing in the most recent execution interval, the ideal CPI is the average number of cycles (clock ticks) that would elapse for each instruction if there were no cache interference or memory interconnect contention, and the current CPI is the average number of cycles (clock ticks) that elapsed for each instruction executed during the most recent execution interval. Equation 10 therefore takes into account not just the time required to repopulate cache lines evicted from the LLC by other threads, but also time spent waiting for the memory interconnect to become available when memory interconnect contention becomes an issue, as described above with reference to FIG. 4."; West [0059-0060] "The values of ideal CPI and current CPI could easily be replaced with their inverses, i.e., instructions per cycle (IPC), and Equation 10 modified by inverting the fraction to give:
e=q*(current IPC/ideal IPC) (Eq. 11)
which is equivalent to Equation 10. Conceptually, the effective CPU time is being defined as the actual execution time, q, times a value representative of the reduction of speed of execution of the thread attributable to any effect caused by other threads sharing the same cache. The value takes into account not only cache contention, but all sources of contention, including any other shared microarchitectural resources, including memory interconnect bandwidth").
Herdrich, Hu, Hunt, and West are analogous art because they are from the same field of endeavor of controlling a variable to achieve a target. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having teachings of Herdrich, Hu, and West before him/her, to modify the teachings of a method and apparatus for controlling resource contention to shared resources by regulating clock throttling and power of a processor of Herdrich modified to include the teachings of a PID neural network including a P neuron, I neuron, and D neuron of Hu further modified to include the adjusting a memory bandwidth allocated to an NLS process in order to achieve a target latency of all processes of Hunt to include the teachings of memory bandwidth adjustment influencing CPI of West because adding the memory bandwidth modification of West would allow the controller to modify the bandwidth allocated to a process which would reduce the CPI, improving the performance as described in West [0035] “FIG. 4 shows a graph 220 having miss rate curves (MRC) 222, 224, 226, 228 that reflect by way of example the impact of available bandwidth on the relationship between thread occupancy of the LLC and the miss rate… Referring back to FIG. 4, the impact of memory interconnect contention can cause a flattening of MRC 222, as shown by MRCs 224, 226, 228 due to the reduced instructions per cycle that can be executed when memory access requests are queued by the memory interconnect controller. That is, when a greater percentage of instructions require a memory access due to reduced cache occupancy, and the memory accesses are further delayed due to memory interconnect contention, the rate of instruction processing as a whole is greatly reduced which also reduces the miss rate as expressed in terms of misses per unit time.”
Claim 15:
The limitations of claim 15 are substantially the same as those of claim 2 and it is rejected for the same reasons.
Claim 16:
Herdrich in view of Hu, further in view of Hunt, further in view of West teaches “The computer-readable medium of claim 14, wherein the one or more parameters allocated to the first group of one or more workloads comprises allocated memory bandwidth” (West teaches that cache interference and memory interconnect bandwidth influences CPI i.e. rather than the PIDNN adjusting a throttling parameter of low priority processes, it may adjust the memory bandwidth of low priority processes in West [0055-0056] "In an alternate embodiment, the effective CPU time is given by:
e=q*(ideal CPI/current CPI) (Eq. 10)
wherein e is the effective CPU time, q is the total CPU time, i.e., the time spent executing in the most recent execution interval, the ideal CPI is the average number of cycles (clock ticks) that would elapse for each instruction if there were no cache interference or memory interconnect contention, and the current CPI is the average number of cycles (clock ticks) that elapsed for each instruction executed during the most recent execution interval. Equation 10 therefore takes into account not just the time required to repopulate cache lines evicted from the LLC by other threads, but also time spent waiting for the memory interconnect to become available when memory interconnect contention becomes an issue, as described above with reference to FIG. 4."; West [0059-0060] "The values of ideal CPI and current CPI could easily be replaced with their inverses, i.e., instructions per cycle (IPC), and Equation 10 modified by inverting the fraction to give:
e=q*(current IPC/ideal IPC) (Eq. 11)
which is equivalent to Equation 10. Conceptually, the effective CPU time is being defined as the actual execution time, q, times a value representative of the reduction of speed of execution of the thread attributable to any effect caused by other threads sharing the same cache. The value takes into account not only cache contention, but all sources of contention, including any other shared microarchitectural resources, including memory interconnect bandwidth"), and
“and the one or more target parameters for the second group of one or more workloads is based on a target cycles per instruction (CPI).” (Herdrich [0031] "In one embodiment, PI controller 120 is coupled to power/performance setting logic 110 via 111 to receive a set point (e.g., power consumption target, CPI target value). In one embodiment, the set point is for a CPI value of a core associated with a high priority application.").
Claim 17:
The limitations for claim 17 are substantially the same as those of claim 5 and it is rejected for the same reasons.
Claim 18:
The limitations of claim 18 are substantially the same as those of claim 6 and it is rejected for the same reasons.
Claim 19:
The limitations of claim 19 are substantially the same as those of claim 7 and it is rejected for the same reasons.
Claim 20:
The limitations of claim 20 are substantially the same as those of claim 8 and it is rejected for the same reasons.
Claim 21:
The limitations for claim 21 are substantially the same as those of claim 10 and it is rejected for the same reasons.
Claim 22:
Herdrich in view of Hu, further in view of Hunt, further in view of West teaches “The apparatus of claim 1, comprising circuitry to throttle a number of memory requests sent to memory from the first group of one or more workloads and based on a percentage of memory bandwidth allocation to the first group of one or more workloads (Hunt teaches reducing the number of tokens corresponding to the number of concurrent memory requests for a non-latency sensitive process, reducing memory latency for other processes in Hunt [0073] “The cap on memory bandwidth consumed by the NLS processes could be achieved by any suitable means. According to one embodiment, a method includes reducing a number of available tokens of a pool of available tokens corresponding to the number of concurrent memory requests that are in process at a given time for a given NLS process. Accordingly, the particular process then is in less competition during the next control cycle or cycles for consuming memory bandwidth. This reduction in total demand for memory bandwidth reduces the memory latency experienced by all processes in the system.”).
“The apparatus of claim 1, comprising circuitry to throttle (Herdrich [0031] "In one embodiment, PI controller 120 is coupled to power/performance setting logic 110 via 111 to receive a set point (e.g., power consumption target, CPI target value). In one embodiment, the set point is for a CPI value of a core associated with a high priority application."; Herdrich teaches that PI controller 120 may be a PID controller in Herdrich [0045] "In one embodiment, operating point control 128 sets an operating point (a combination of P-state and T-state) based on determination from decision logic 127. In one embodiment, decision logic 127 further operates in conjunction with information including misses per instruction, a number of cache line fills, and a number of cache line evictions to avoid overcorrecting by PID controller 120."; Herdrich [0054-0055] "In one embodiment, processing logic monitors CPI of a core executing a high priority program i.e. the CPI of the high priority program may be the set point or target parameter (process block 204). In one embodiment, processing logic also monitors information, such as, for example, misses per instruction (MPI), cache line fills, cache line evictions, etc.In one embodiment, processing logic compares data from the monitoring with the set point (process block 205). In one embodiment, no action is taken if the performance data are within a predetermined range. if the performance data are higher than the set point, a PI control mechanism generates an output based at least on the difference (error) between the set point and performance data (process block 206). In one embodiment, processing logic determines, based on the output, whether to increase a T-state (less enforcement) or to decrease a T-state (more enforcement) of cores associated with low priority programs i.e. the PID controller adjusts a parameter of a first workload to reach a target parameter of a second workload (process block 207).").
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Herdrich et al. (US20160077844A1), in view of HU, Huailin, GUO, Xiucai, and SHU, Hua. "PID neural networks in multivariable systems", Proceedings of the IEEE international Symposium on Intelligent Control, IEEE, October 2002, 5 pages. (Hereinafter referred to as “Hu”, citations provided to applicant provided copy), further in view of Hunt et al. (US20190190805A1), further in view of West et al. (US20110055479A1), further in view of Choi (US20240320464A1).
Claim 12:
Herdrich in view of Hu, further in view of Hunt, further in view of West teaches “The apparatus of claim 1” as described above. Herdrich in view of Hu, further in view of Hunt, further in view of West does not appear to explicitly teach “wherein the circuitry is to adjust a linearly adjusted input range to the PIDNN controller for at least one control loop iteration.” However, Choi does teach this claim limitation (Choi [0074] "Meanwhile, the controller 302 can determine the quantization range by using feedback control i.e. the range is determined over multiple control loops based on the current saturation ratio and the target saturation ratio of activations. Here, the feedback control includes at least one of proportional integral derivative (PID) control, PI control, ID control, PD control, proportional control, integral control, and differential control."
Herdrich, Hu, Hunt, West, and Choi are analogous art because they are from the same field of endeavor of controlling a variable to achieve a target. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having teachings of Herdrich, Hu, Hunt, West, and Choi before him/her, to modify the teachings of a method and apparatus for controlling resource contention to shared resources by regulating clock throttling and power of a processor of Herdrich modified to include the teachings of a PID neural network including a P neuron, I neuron, and D neuron of Hu, further modified to include the adjusting a memory bandwidth allocated to an NLS process in order to achieve a target latency of all processes of Hunt, further to include the teachings of memory bandwidth adjustment influencing CPI of West to include the teachings of a method and a device for determining a quantization range based on a saturation ratio for quantization of an artificial neural network of Choi because adding the quantization range control of Choi would allow the accuracy of the neural network to be improved as described in Choi [0038] "the quantization range can be adjusted in the inference stage of the artificial neural network, so the accuracy of the neural network can be improved through adaptive calibration for user data."
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li et al. (CN111123698A) teaches linearizing a model in Li [0021] “Furthermore, in step (2), the unit model is established using the characteristic line method, and the model is linearized using the compact dynamic linearization method (CFDL).”
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Z.A.C./ Examiner, Art Unit 2116
/KAMINI S SHAH/ Supervisory Patent Examiner, Art Unit 2116