DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 24, 2025 has been entered.
Response to Amendment
This Non-Final Office Action is in response to the applicant’s remarks and arguments filed on June 24, 2025.
Claims 1, 3-4, 8, 10-11, 15 and 17-18 were amended.
Claims 1-20 remain pending in the application. Claims 1-20 are being considered on the merits.
Response to Arguments
Rejections Under 35 U.S.C. § 103
Applicant argue that :
“Applicant respectfully asserts that the amendments overcome the current rejection at least because the Office Action fails to reject the claims as amended and at least for the reasons indicated above”.
Examiner’s response :
Applicant’s arguments with respect to the newly added limitations have been considered but are moot because the arguments do not apply to the reference Maislos et al. (US 2016/0026489) and Mcgraw et al. (US 2022/0350767) being used in the current rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-21 are rejected under 35 U.S.C. 103 as being unpatentable over Maislos et al. (US 2016/0026489, Maislos hereinafter) in view of Mcgraw et al. (US 2022/0350767. McGraw hereinafter).
As to claim 1, Maislos teaches a non-transitory computer readable medium having stored thereon a sequence of instructions which, when stored in memory and executed by a processor cause the processor to perform acts for handling memory of a virtual machine (e.g., para 9, “non-transitory computer-readable medium in which program instructions”, “processors of first and second compute nodes that communicate with one another over a communication network”, cause the processors to run a Virtual Machine (VM) on the first compute node and to migrate the VM from the first compute node to the second compute node”) , the acts comprising:
issuing a first memory command of a first virtual machine of a first virtualization system running on a first computing node, the first memory command being issued by a first CPU of the first computing node to perform a memory operation on a first memory location of the first computing node (e.g., see FIG. 2, para 51” memories 36 of the source and destination nodes “ , “ FIG. 2, VM_SRC is a source VM running on a source node NODE_A. In addition, VM_DST 72 is a destination VM, which is a migrated instance of VM_A running on NODE_B, which is the destination node” and “copying the content of the pages” , “ copies the content of the pages to the destination node.” , “identifiers of the externalized pages are transferred during the respective stop-and-copy steps 234 and 268” in para 53, 95 . Thus, one of the “memories 36 of the source “ coupled with “identifiers” include a first memory location of the first computing node, the “copying “ coupled with “copies the content of the pages” and ““ the storage location of the page and a hash value computed over the page content” in para 104 , therefore issuing a first memory command of a first virtual machine of a first virtualization system running on a first computing node, the first memory command being issued by a first CPU of the first computing node to perform a memory operation on a first memory location of the first computing node); and
accessing a corresponding second memory location of a second computing node to perform the memory operation issued by the first CPU ( para 102, “VMs 470 and provides the VMs with resources such as memory, storage and CPU resources” and “instructions, when read by processors of first and second compute nodes that communicate with one another over a communication network” in para 9. Thus, the “instructions” coupled with CPU resources for “storage location of the page and a hash value computed over the page content” in para 103. Therefore, accessing a corresponding second memory location of a second computing node to perform the memory operation issued by the first CPU ) using an interconnection (e.g., para 103, “a transport layer 484 and a shard component 488”, “Transport layer 484 is responsible for communicating and exchanging pages with peer transport layers 484 of other nodes” and “ the storage location of the page and a hash value computed over the page content” In para 104, see FIG. 7. Thus, the “a transport layer 484 “ include interconnection) ,
However, Maislos does not teaches using an interconnection fabric, the interconnection fabric comprising first specialized hardware at the first computing node and second specialized hardware at the second computing node, wherein the first specialized hardware determines that the first memory command corresponds to the second memory location at the second computing node, the first specialized hardware forwards the first memory command to the second specialized hardware, and the second specialized hardware accesses the corresponding second memory location to perform the first memory command.
McGraw teaches an interconnection fabric comprising first specialized hardware at a first computing node and second specialized hardware at a second computing node (see FIG. 3, para 64, “interconnection fabrics (e.g., 342, 344)” and “physical infrastructure modules” and “C-RAs 414 utilizing CXL” in para 68, see FIG. 4) , wherein the first specialized hardware determines that the first memory command corresponds to the second memory location at the second computing node, the first specialized hardware forwards the first memory command to the second specialized hardware, and the second specialized hardware accesses the corresponding second memory location to perform the first memory command (e.g.,
See FIG. 3, para 31, para 64 wherein “multiple parallel interconnection fabrics (e.g., 342, 344) and see FIG. 4. , para 69,70 , “Target/IO resources 434 the provide a physical function (PF) and corresponding T-RAs 432. Resources 434 can be connected to T-RAs 414 utilizing CXL or PCIe protocols, for example. Processing cores 412 can be any type of resource that can be utilized to support processing cores 412, for example, memory modules, smart I/O modules” , “Interconnection fabrics 421 and 425 “, “ interconnections between compute modules 410 and target modules 430” , “the interconnection fabrics are PCIe-based interconnection fabrics” for “/O target bindings (e.g., logical memory ranges” in para 79. Thus, the “/O modules” represent the commands , the “logical memory ranges” include the memory location. Therefore , wherein the first specialized hardware determines that the first memory command corresponds to the second memory location at the second computing node, the first specialized hardware forwards the first memory command to the second specialized hardware, and the second specialized hardware accesses the corresponding second memory location to perform the first memory command) .
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the method of Maislos by adopting the teachings of McGraw to have accessing a corresponding second memory location of a second computing node to perform the memory operation issued by the first CPU using an interconnection fabric, the interconnection fabric comprising first specialized hardware at the first computing node and second specialized hardware at the second computing node, wherein the first specialized hardware determines that the first memory command corresponds to the second memory location at the second computing node, the first specialized hardware forwards the first memory command to the second specialized hardware, and the second specialized hardware accesses the corresponding second memory location to perform the first memory command in order to “provide parallel paths between the various nodes to provide maximum available bandwidth” (see McGraw, para 65) or to allow “ I/O utilization can be more efficient as I/O resources can be shared between compute resources sequentially or concurrently.” (see McGraw, para 54).
As to claim 2, Maislos does not teach wherein the first specialized hardware comprises a first CXL device and the second specialized hardware comprises a second CXL device. However, McGraw teaches wherein the first specialized hardware comprises a first CXL device and the second specialized hardware comprises a second CXL device (e.g., para 102, “Processing cores”, “ utilizing CXL “) . Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the method of Maislos by adopting the teachings of McGraw to allow “ I/O utilization can be more efficient as I/O resources can be shared between compute resources sequentially or concurrently.” (see McGraw, para 54).
As to claim 3, Maislos teaches issuing a second memory command of a second virtual machine of a virtualization system running on the second computing node, the second memory command being issued by a second CPU of the second computing node to perform a second memory operation on the second memory location of the second computing node; and rather than accessing the second memory location of the second computing node, instead accessing a corresponding first memory location of the first computing node to perform the second memory operation issued by the second, wherein the first specialized hardware accesses the corresponding second memory location to perform the second memory command (e.g., para 9, “which instructions, when read by processors of first and second compute nodes that communicate with one another over a communication network”. Thus, the another one of the include the second command”. Also, see FIG. 7). However, Maislos does not teach using the interconnection fabric. McGraw teaches using the interconnection fabric (see rejection of claim1 above). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the method of Maislos by adopting the teachings of McGraw to have issuing a second memory command of a second virtual machine of a virtualization system running on the second computing node, the second memory command being issued by a second CPU of the second computing node to perform a second memory operation on [[a]] the second memory location of the second computing node; andrather than accessing the second memory location of the second computing node, instead accessing a corresponding first memory location of the first computing node to perform the second memory operation issued by the second CPU using the interconnection fabric, wherein the first specialized hardware accesses the corresponding second memory location to perform the second memory command in order to allow “ I/O utilization can be more efficient as I/O resources can be shared between compute resources sequentially or concurrently.” (see McGraw, para 54).
As to claim 4, Maislos teaches wherein the first memory command corresponds to a virtual address of the first virtual machine and is mapped to a first physical address determines that the first memory command corresponds to the second memory location at the second computing node based on at least a determination that the memory operation is mapped to the second memory location at the second computing node, the second memory location comprising a second physical address at the second computing node (e.g., para 103, “ Transport layer 484 is responsible for communicating and exchanging pages with peer transport layers 484 of other nodes” coupled with “ the ability to map pages in and out of a virtual machine's address space” in para 111. Thus , wherein the first memory command corresponds to a virtual address of the first virtual machine and is mapped to a first physical address determines that the first memory command corresponds to the second memory location at the second computing node based on at least a determination that the memory operation is mapped to the second memory location at the second computing node, the second memory location comprising a second physical address at the second computing node would have been inherent ) . However, Maislos does not teach the first specialized hardware. McGraw teaches memory command corresponds to a virtual address of the first virtual machine and is mapped to a first physical address of the first specialized hardware ( e.g., para 67, “mapping physical and virtual functions provided by compute modules and target modules to achieve a logical server architecture. This figure shows both Physical Infrastructure with parallel fabrics and the Logical Infrastructure, where the parallel fabrics are invisible and only mapped resources are visible to a server”. Thus, memory command corresponds to a virtual address of the first virtual machine and is mapped to a first physical address of the first specialized hardware would have been inherent ). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the method of Maislos by adopting the teachings of McGraw to have wherein the first memory command corresponds to a virtual address of the first virtual machine and is mapped to a first physical address of the first specialized hardware and the first specialized hardware determines that the first memory command corresponds to the second memory location at the second computing node based on at least a determination that the memory operation is mapped to the second memory location at the second computing node, the second memory location comprising a second physical address at the second computing node in order to allow “ I/O utilization can be more efficient as I/O resources can be shared between compute resources sequentially or concurrently.” (see McGraw, para 54).
As to claim 5, Maislos teaches copying, a memory page of the second virtual machine on the first computing node into physical memory of the second computing node after performing the second memory operation (see FIGs. 1 and 2, para 45 and 53 “copying the content of the pages”, “ pages in memory 36 of NODE_A”, “ copies of such a page” and “ exporting to other nodes.” In para111, see FIG. 7). However, Maislos does not teach using the interconnection fabric. McGraw teaches using the interconnection fabric (see rejection of claim1 above) . Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the method of Maislos by adopting the teachings of McGraw to copying, using the interconnection fabric, a memory page of the second virtual machine on the first computing node into physical memory of the second computing node after performing the second memory operation in order to allow “ I/O utilization can be more efficient as I/O resources can be shared between compute resources sequentially or concurrently.” (see McGraw, para 54).
As to claim 6, Maislos teaches instantiating a copy of the first virtual machine of the first virtualization system running on the first computing node to the second computing node (e.g., para 114, wherein “the source VM, destination VM “ for” transferring the content “ , “ memory pages during migration” . Thus, instantiating a copy of the first virtual machine of the first virtualization system running on the first computing node to the second computing node).
As to claim 7, Maislos teaches wherein at least a portion of the copy of the first virtual machine of the first virtualization system is stored in physical memory (e.g., see FIG. 2, para 53, “copying the content of the pages.” , “pages in memory 36 of NODE_A,” ) . However, Maislos does not teach of the interconnection fabric. McGraw teaches teaches physical memory of the interconnection fabric ( see rejection of claim 1 above). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the method of Maislos by adopting the teachings of McGraw to have wherein at least a portion of the copy of the first virtual machine of the first virtualization system is stored in physical memory of the interconnection fabric in order to allow “ I/O utilization can be more efficient as I/O resources can be shared between compute resources sequentially or concurrently.” (see McGraw, para 54).
As to claim 8, see rejection of claim 1 above
As to claims 9-14 see rejection of claims 2-7 above.
As to claim 15, see rejection of claim 1 above
As to claims 16-21, see rejection of claims 2-7 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Debbage et al. (US 20210119930) discloses “use the network interface as an interface with a network, fabric, or interconnect. Various embodiments can be used as part of a switch. Various embodiments of the network interface can be used as a transmitter or receiver NIC that can be part of an RTA. In some examples, network interface 1400 can be implemented as a network interface controller, network interface card, a host fabric interface (HFI), or host bus adapter (HBA), and such examples can be interchangeable. Network interface 1400 can be coupled to one or more servers using a bus, PCIe, CXL, or DDR. Network interface 1400 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors” .
PRATEEK SHANTHARAMA “ardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies”, July 29, 2020. Discloses “a PCIe compliant interconnect focusing primarily on providing cache coherency across either side of the CXL link. The CXL link is targeted for accelerators on the platform as current chip-to-chip interconnects that connect accelerators do not support cache-to-cache coherency between the CPU LLC and the local cache of the accelerator. As the computing demands increase, there will be accelerators with large processing units (i.e., local CPU), large local memory (i.e., local to accelerator), and an associated local cache.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDOU K SEYE whose telephone number is (571)270-1062. The examiner can normally be reached M-F 9-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached at 5712724215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ABDOU K SEYE/Examiner, Art Unit 2198
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
Prosecution Insights