DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA and is in response to communications filed on 1/27/2026 in which claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 10, 13, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Testardi et al. US 20070016754 A1 (hereinafter referred to as “Testardi”) in view of Maciocco et al. US 20210014133 A1 (hereinafter referred to as “Maciocco”) in view of Brooks et al. US 10534606 B2 (hereinafter referred to as “Brooks”) and further in view of Shilimkar et al. US 20220210225 A1 (hereinafter referred to as “Shilimkar”).
As per claim 1, Testardi teaches:
A system, comprising:
a node, of a distributed cluster of nodes (Testardi, [0064]-[0066] – A distributed virtualization engine (DVE) may be implemented anywhere between a host application and physical storage devices) …
configured to store data across distributed storage managed by the distributed cluster of nodes (Testardi, [0227] – There may be a list of those nodes that maintain a copy of the metadata locally in memory of all of the DVEs that are caching a particular metadata),
the node comprising one or more processors to execute one or more instructions to:
determine whether the first set of journal data is to be stored in a cache within a storage platform perform region based on a status of a region of a block storage device in which the first set of journal data is stored (Testardi, [0016] – A general control path is used. A portion of the extent table corresponding to a current data operation is loaded into a memory local to the fast path. The portion of the extent table is included in a memory managed using a cache management technique. [0017] – Machine executable code loads into a memory local to the fast path a portion of said extent table corresponding to a current data operation. The portion of the extent table is included in a memory managed using a cache management technique. [0088] – Otherwise, control proceeds to step 102 where a further determination is made as to whether the I/O logical block address or LBA extent is cached) …
Testardi doesn’t explicitly teach an orchestration platform, however, Maciocco teaches:
hosted within a container orchestration platform (Maciocco, [0061] – This arrangement is further adapted for use in system arrangement 540, which provides containers 542, 543, or execution of the various functions, applications, and functions on compute nodes 544, as coordinated by an container-based orchestration system),
It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Testardi’s invention as modified in view of Maciocco in order to include an orchestration platform; this is advantageous because through known platforms such as orchestration platforms, the system can perform operations related to managing the computation as well as the storage and caching of data on nodes (Maciocco, [0121]).
Although Testardi teaches fast path and cold path storage which is used for different types of data and for different reasons as well as mentioning transferring data in [0115], Testardi isn’t clear with respect to detecting a transfer type to exchange data with cores and/or cache, however, Brooks teaches:
determine a type of transfer mode implemented for transferring a first set of journal data associated with a first of a plurality of I/O operations (Brooks, column 18, lines 39-45 – I/O interface 1150 may be configured to provide a central interface for such sources to exchange data with cores 1110 and/or L3 cache 1130 via coherence unit 1160. In some embodiments, I/O interface 1150 may be configured to coordinate Direct Memory Access (DMA) transfers of data between external peripherals and system memory via coherence unit 1160 and memory interface 1140);
…upon determining that a first type of transfer mode is implemented (Brooks, column 26-31 – Memory interface 1140 may be configured to manage the transfer of data between L3 cache 1130 and system memory, for example, in response to L3 fill requests and data evictions. In some embodiments, multiple instances of memory interface 1140 may be implemented, with each instance configured to control a respective bank of system memory); and
It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Testardi’s invention as modified in view of Brooks in order to detecting a transfer type to exchange data with cores and/or cache; this is advantageous to provide an implementation- or system-specific sequence of boot instructions and data. Such a boot sequence may, for example, coordinate reset testing, initialization of peripheral devices and initial execution of a processor, before the boot process proceeds to load data from a disk or network device (Brooks, [0016]).
Although Testardi as modified with Brooks teaches DMA transfers, Brooks doesn’t explicitly teach determining different types of transfers for utilizing cache memory, however, Shilimkar teaches:
determine whether the first set of journal data is to be stored in the cache based on characteristics of the first set of journal data upon determining that a second type of transfer mode is implemented (Shilimkar, [0043] – Such transfers require little to no work to be done by CPUs or caches and avoid context switches of the computer, and the transfers may continue in parallel with other system operations. [0185] – The value of a quality-of-service (QoS) data field is indicated by the type of RDMA over Converged Ethernet (RoCE) transfer that is being performed (e.g., according to a predetermined mapping of QoS priority values to RDMA transfer types). RoCE packets carrying a high-volume data transfer may be tagged with a different QoS than RoCE packets carrying a low-volume data transfer that is extremely latency-sensitive, for example. Examples of high-volume transfers may include backups, reporting, or batch messages, while examples of low-latency critical transfers may include congestion information notifications, cluster heartbeat, transaction commits, cache fusion operations, and the like).
It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Testardi’s invention as modified in view of Shilimkar in order to determine different types of transfers for utilizing cache memory; this is advantageous for when high-volume data transfers vs low-volume data transfers occur because the system can determine which storage is needed for latency requirements (Shilimkar, [0185]).
As per claim 4, Testardi as modified teaches:
The system of claim 1, wherein the one or more processors execute the one or more instructions to:
determine one or more second characteristics associated with a second set of journal data, wherein the one or more second characteristics comprise at least one of:
a second type of I/O operation of a second 1/O operation of the plurality of I/O operations (Testardi, [0131] – An I/O request 400 may include a VDEVICE 402, an LBA 404, a TYPE 406 and a SIZE 408. The VDEVICE 402 may include a virtual device destination for the I/O operation. The TYPE 406 may identify a type of I/O operation);
a second size of the second set of journal data (Testardi, [0131] – An I/O request 400 may include a VDEVICE 402, an LBA 404, a TYPE 406 and a SIZE 408. The VDEVICE 402 may include a virtual device destination for the I/O operation. The TYPE 406 may identify a type of I/O operation. [0179] – The journal may be fixed in size and writes to a full journal may be forwarded to the CP for processing); or
a second client associated with the second 1/O operation (East, [0162] – Blockchains may be designed to be resistant to modification of the data and can serve as an open, distributed ledger that can record transactions between two parties efficiently and in a verifiable and permanent way); and
determine, based upon the one or more second characteristics, to store the second set of journal data in the block storage device and in the cache (Testardi, [0010] – The data operation is routed to a fast path for processing if the data operation has the at least one predetermined criteria, and routing the data operation to a general control path for processing otherwise).
As per claim 5, Testardi as modified teaches:
The system of claim 4, wherein the one or more processors execute the one or more instructions to use the one or more second characteristics to determine whether or not to store the second set of journal data in the cache when a sync transfer mode is implemented for transferring sets of data to a journal maintained by the node (Testardi, [0074] – The CP may handle all error processing, all coherency and synchronization operations in connection with other CPs and all intervolume coherency, for example, as may be included in complex systems such as those using mirroring, striping, snapshots, on-line migrations, and the like. All errors may be returned to the host or forwarded through the CP. An FP may also notify a CP about I/Os, for example, in connection with gathering statistics or error recovery purposes. See also paragraphs [0125]-[0127], [0137] and [0179]).
As per claim 10, Testardi as modified teaches:
The system of claim 1, wherein the one or more processors execute the one or more instructions to implement a plurality of flushing threads to facilitate concurrent data transfers from clients to a journal hosted by the node (Testardi, [0215] – There may be many processes within a single DVE competing for a single lock, such as sweep threads, migration threads and the like, all executing simultaneously. [0246] – Each of the non-volatile inter-DVE oplocks may be represented by the following: [0247] owner (current and recent, if known) [0248] slist--"share broadcast list" (all joined DVEs) [0249] alist--"acquire broadcast list" (all sharing DVEs) [0250] dirty--indicates dirty (unrestrictive) metadata needs to be flushed. Also [0254]).
Claim 13 is directed to a method performing steps recited in claim 1 with substantially the same limitations. Therefore, the rejection made to claim 1 is applied to claim 13.
As per claim 15, Testardi as modified teaches:
The method of claim 13, wherein the first status of the first region is used to determine whether or not to store the first set of journal data in the cache when an async transfer mode is implemented for transferring sets of data to the journal (Testardi, [0181] – An FP may support operations such as, for example, LUN pooling, multi-pathing, snapshots, on-line migration, incremental storage, RAID0 using I/O striping, RAID1 using the write splitting primitive to implement synchronous replication with a fast resynchronization, RAID 10 sing the I/O striping and write splitting, asynchronous ordered replication (AOR) using the write splitting and write journaling primitives, and others).
As per claim 16, Testardi as modified teaches:
The method of claim 13, comprising:
facilitating concurrent data transfers, from clients of the plurality of clients to the journal, using a plurality of flushing threads implemented by a data management system (Testardi, [0215] – There may be many processes within a single DVE competing for a single lock, such as sweep threads, migration threads and the like, all executing simultaneously. [0246] – Each of the non-volatile inter-DVE oplocks may be represented by the following: [0247] owner (current and recent, if known) [0248] slist--"share broadcast list" (all joined DVEs) [0249] alist--"acquire broadcast list" (all sharing DVEs) [0250] dirty--indicates dirty (unrestrictive) metadata needs to be flushed. Also [0254]).
Claim 17 is directed to a non-transitory machine readable medium performing steps recited in claim 1 with substantially the same limitations. Therefore, the rejection made to claim 1 is applied to claim 17.
As per claim 20, Testardi as modified teaches:
The non-transitory machine readable medium of claim 17, comprising instructions, which when executed by a machine, further causes the machine to perform operations, the operations comprising:
providing byte addressable access to the first set of journal data stored in the cache (Testardi, [0090] – In one embodiment, the extent redirect index may be, for example, 4 bits used to access, for example, directly or indirectly, a hundred bytes of other information).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Testardi in view of Maciocco in view of Brooks in view of Shilimkar and further in view of Kumar et al. US 20170206166 A1 (hereinafter referred to as “Kumar”).
As per claim 2, Testardi as modified teaches:
The system of claim 1, wherein determining whether the first set of journal data is to be stored in the cache based on the characteristics of the first set of journal data comprises
the one or more processors execute the one or more instructions to
determine whether one or more characteristics of a first set of journal data associated with a first of a plurality of I/O operations satisfies a caching condition (Testardi, [0010] – The data operation is routed to a fast path for processing if the data operation has the at least one predetermined criteria, and routing the data operation to a general control path for processing otherwise. [0095] – A determination is made as to whether the particular I/O operation is for a mirroring device or involves a write to a journal);
store the first set of journal data in a block storage device and the cache within a storage platform upon determining that the one or more characteristics satisfies the caching condition (Testardi, [0010] – The data operation is routed to a fast path for processing if the data operation has the at least one predetermined criteria, and routing the data operation to a general control path for processing otherwise. [0126] – The portion of the rmap table that is cached within the FP is synchronized with the complete copy maintained by the CP, wherein this means that both the CP and FP are utilized to store the same data); and
Testardi doesn’t include criteria for data to either be stored in cache or in other memory based on a caching condition, however, Kumar teaches:
store the first set of journal data in the block storage device without storing the first set of journal data in the cache upon determining that the one or more characteristics does not satisfy the caching condition (Kumar, [0024] – Caching may be bypassed for certain operations such as large, sequential writes, as indicated by operation 130. As will be described below, a caching adaptation layer will include features that allow cache bypass to occur with minimal caching library overhead and reducing lock contention).
It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Testardi’s invention in view of Kumar in order to include criteria for data to either be stored in cache or in other memory; this is advantageous for efficient storage for balancing between cost and speed, and tier storage is a known technique which allows for general data arrangement (Kumar, [0016]).
As per claim 3, Testardi as modified teaches:
The system of claim 2, wherein the one or more characteristics comprises a client identifier (Testardi, [0218] – “owner” is an identifier of a client).
Claims 6-7, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Testardi in view of Maciocco in view of Brooks in view of Shilimkar and further in view of Golden et al. US 20220027472 A1 (hereinafter referred to as “Golden”).
As per claim 6, Testardi as modified doesn’t explicitly teach a dormant or active status in a region of the block storage device, however, Golden teaches:
The system of claim 1, wherein determining whether the first set of journal data is to be stored in the block storage device or the cache based on the status of the region of the block storage device comprises the one or more processors to execute the one or more instructions to:
determine a status of a region, of the block storage device, in which the first set of journal data is stored (Golden [0095] – Reservation or exclusion primitives may be provided so that, in a storage system with two storage controllers providing a highly available storage service, one storage controller may prevent the other storage controller from accessing or continuing to access the storage device. [0279] – Dormant storage regions are determined and preventative action can be taken for security issues); and
store the first set of journal data in the cache (Golden [0095] – Prevent the other storage controller from accessing or continuing to access the storage device. [0279] – Dormant storage regions are determined and preventative action can be taken for security issues).
It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Testardi’s invention as modified in view of Golden in order to determine dormant or active storage regions; this is advantageous because the storage system can detect possibly malicious action (Golden, paragraph [0279]).
As per claim 7, Testardi as modified teaches:
The system of claim 6, wherein the one or more processors execute the one or more instructions to use the status to determine whether or not to store the first set of journal data in the cache when an async transfer mode is implemented for transferring sets of data to the journal (Testardi, [0181] – An FP may support operations such as, for example, LUN pooling, multi-pathing, snapshots, on-line migration, incremental storage, RAID0 using I/O striping, RAID1 using the write splitting primitive to implement synchronous replication with a fast resynchronization, RAID 10 using the I/O striping and write splitting, asynchronous ordered replication (AOR) using the write splitting and write journaling primitives, and others).
Claim 14 is directed to a method performing steps recited in claim 6 with substantially the same limitations. Therefore, the rejection made to claim 6 is applied to claim 14.
Claims 18-19 are directed to non-transitory machine readable medium performing steps recited in claims *** with substantially the same limitations. Therefore, the rejections made to claims *** are applied to claims 18-19.
Claims 8, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Testardi in view of Maciocco in view of Brooks in view of Shilimkar and further in view of East et al. US 20190361626 A1 (hereinafter referred to as “East”).
As per claim 8, Testardi as modified teaches:
The system of claim 1, one or more processors execute the one or more instructions to:
determine a status of a region, of the block storage device, in which the second set of journal data is stored (Testardi, [0017] – The mapping tables include an extent table corresponding to a logical block address range and a storage redirect table includes physical storage location information associated with the logical block address range. [0120] – Status); and
Testardi as modified doesn’t explicitly teach that authorities 168 are stateless, i.e., they cache active data and metadata in their own blades' 252 DRAMs for fast access, but the authorities store every update in their NVRAM 204 partitions on three separate blades 252 until the update has been written to flash 206, however, East teaches:
determine, based upon the status being active, to store the second set of journal data in the cache (East, [0094] – One feature of elasticity is that authorities 168 are stateless, i.e., they cache active data and metadata in their own blades' 252 DRAMs for fast access, but the authorities store every update in their NVRAM 204 partitions on three separate blades 252 until the update has been written to flash 206).
It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Testardi’s invention as modified in view of East in order to keep data cached as key-value pairs in a persistent manner until written to distributed storage; this is advantageous because the storage system can survive concurrent failure of two blades 252 with no loss of data, metadata, or access to either (East, paragraph [0094]).
As per claim 11, although Testardi teaches key values and persistent memory, Testardi as modified doesn’t explicitly teach that the data is cached as key-value pairs until written in a distributed manner, however, East teaches:
The system of claim 1, wherein the one or more processors execute the one or more instructions to cache the data as key-value record pairs within a persistent key-value store for read and write access until written in a distributed manner across the distributed storage (East, [0210] – Integrated storage manager may be stateless, where being stateless and also providing persistent storage across container instances or across multiple applications may be dependent upon the integrated storage manager. The integrated storage manager (400) may use a key-value pair for storing and referencing such metadata. Fig. 2F and [0094] – They cache active data and metadata in their own blades’ 252 DRAMs for fast access, but the authorities store every update in their NVRAM 204 partitions on three separate blades 252 until the update has been written to flash 206).
It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Testardi’s invention as modified in view of East in order to keep data cached as key-value pairs in a persistent manner until written to distributed storage; this is advantageous because it allows for fast access while also allowing for backup of data in case of failures of partitions (East, paragraph [0094]).
As per claim 12, Testardi as modified with East teaches:
The system of claim 11, wherein the one or more processors execute the one or more instructions to:
track metrics associated with storage utilization by at least one of the journal or the persistent key-value store, wherein the metrics are used to determine when to store data from a journal to the distributed storage (East, [0048] – Tracking statistics related to the use and reuse of Flash memory pages, erase blocks, and cells. [0054] – Stored energy device 122 may be used to store accumulated statistics and other parameters kept and tracked by the Flash memory devices 120a-n and/or the storage device controller. Also, [0215]).
Claims 9 are rejected under 35 U.S.C. 103 as being unpatentable over Testardi in view of Maciocco in view of Brooks in view of Shilimkar in view of East and further in view of Kumar.
As per claim 9, Testardi as modified with East doesn’t adequately teach bypassing cache storage, however, Kumar teaches:
The system of claim 8, wherein the one or more processors execute the one or more instructions to not store the first set of journal data in the cache upon determining that the status of the region is dormant (Kumar, [0024] – Caching may be bypassed for certain operations such as large, sequential writes, as indicated by operation 130. As will be described below, a caching adaptation layer will include features that allow cache bypass to occur with minimal caching library overhead and reducing lock contention).
It would have been obvious for one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Testardi’s invention in view of Kumar in order to include criteria for data to either be stored in cache or in other memory; this is advantageous for efficient storage for balancing between cost and speed, and tier storage is a known technique which allows for general data arrangement (Kumar, [0016]).
Response to Arguments
Applicant’s arguments with respect to claims have been considered but are generally moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Budovski et al. US 20220382743 A1
Vig et al. US 10853182 B1 teaches In response to determining that a secondary index is to be created for a particular table of a non-relational database service, a service component verifies that automated transmission of change records of the table to a log-structured journal has been configured (Abstract).
Li et al. June 19, 2014, “Nitro: A capacity-Optimized SSD Cache for Primary Storage”, https://www.usenix.org/system/files/conference/atc14/atc14-paper-li_cheng_nitro.pdf, Pgs 501-512. Teaches a cache replacement policy that tracks the status of WEUs instead of compressed data, which reduces SSD erasures (pg. 501, column 2). Pgs 501-512.
Palantir Blog, May 16, 2019, “Spark Scheduling in Kubernetes”, https://blog.palantir.com/spark-scheduling-in-kubernetes-4976333235f3, teaches in paragraph 4 - Spark on Kubernetes - Kubernetes objects such as pods or services are brought to life by declaring the desired object state via the Kubernetes API.
Yanovsky et al. US 20170272209 A1 teaches memory allocation policy for a file stored within the processing system cache. File caching parameters include maximum number of compound blocks allocated for a file and a parallel transferring threshold. R/w block size may be also considered as a parameter, where r/w block size indicates granularity of data writes and reads.
Lee et al. US 20230214115 A1 teaches in [0072] – Recorded or logged write I/Os of the log are processed and flushed whereby the recorded write I/O operation that writes to a target logical address or location (e.g., target LUN and offset) is read from the log and then executed or applied to a non-volatile BE PD location mapped to the target logical address (e.g., where the BE PD location stores the data content of the target logical address).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Matthew Ellis whose telephone number is (571)270-3443. The examiner can normally be reached on Monday-Friday 8AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Neveen Abel-Jalil can be reached on (571)270-0474. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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April 13, 2026
/MATTHEW J ELLIS/Primary Examiner, Art Unit 2152
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