DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed March 31st, 2022. Claims 1-21 are pending, of which claims 1-21 are currently rejected.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/31/2022 are in compliance with the provisions of 37 CFR 1.97. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Specification
The disclosure is objected to because of the following informalities:
[0001] blank spaces where application numbers should be
[0036] “the scenario of FIG. 4 involving only two processes” should be “the scenario of FIG. 3 involving only two processes”, which would be consistent with what is disclosed in [0035].
Claim Objections
Claims 4 and 11 are objected to because of the following informalities:
Line 2 “for a period time” should be “for a period of time”.
Line 11 line 2 “for a period time” should be “for a period of time”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Salmon et al. ("Parallel Random Numbers: As Easy as 1, 2, 3", 2011) (hereinafter “Salmon”).
Regarding claim 1, Salmon teaches:
A method comprising:
initializing, by a computer system, a shared counter (Pg. 9 Col. 2 Section 5.1 Lines 19-39 a shared counter n is initialized by computer system);
creating, by the computer system, a plurality of software processes, each software process being programmed to increment the shared counter a predefined number of times (Pg. 9 Col. 2 Section 5.1 Lines 1-4 streams i.e., software processes; Pg. 9 Col. 2 Section 5.1 Lines 19-39 shared counter n is incremented by plurality of software processes based on key, or identifier of process that increments the counter, and time);
running, by the computer system, the plurality of software processes concurrently (Pg. 9 Col. 2 Section 5.1 Lines 1-4 streams i.e., software processes running in parallel i.e., concurrently);
upon completion of the plurality of software processes, applying, by the computer system, one or more functions to the shared counter, the applying resulting in a value (Pg. 2 Col. 1 Lines 12-17 function applied to counter to provide random number value xn as output value);
outputting, by the computer system, the value (Pg. 2 Col. 1 Lines 12-17 function applied to counter to provide random number value xn as output value).
Regarding claim 2, Salmon teaches:
The method of claim 1 wherein the computer system is a multiprocessor system (Pg. 8 Col. 2 footnote 12 Lines 1-2 program run on 3.07 GHz quad-core Intel Xeon X 5667 CPU i.e., multiprocessor system) and wherein each of the plurality of software processes is run on a separate physical processing core or hardware thread of the multiprocessor system (Pg. 9 Col. 2 Section 5.1 Lines 1-4 streams i.e., software processes function on their own computational unit i.e., hardware thread as discussed in Pg. 1 Col. 2 Lines 38-41).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Salmon further in view of North et al. (6055619) (hereinafter “North”).
While Salmon teaches the method of claim 1, and a function being performed on a counter (Salmon: Pg. 2 Col. 1 Lines 12-17), Salmon does not explicitly teach a function for sampling the least significant byte.
However, North teaches a sampling function for selecting i.e., sampling the least significant bytes of a value (North: Col. 23 Lines 13-28).
It would be obvious to combine the sampling function as taught by North with the method as taught by Salmon as both teachings are directed towards digital design. One with ordinary skill in the art would be motivated to combine the teachings of Salmon and North because North enables resolving down to byte samples (North: Col. 23 Lines 29-30), which can increase entropy.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Salmon further in view of Burns et al. (6665620) (hereinafter “Burns”).
While Salmon teaches the method of claim 1, Salmon does not explicitly teach having a period of sleep for each of the software processes between each increment.
However, Burns teaches alternating between incrementing a counter and having the programs going into sleep, and therefore having a period of sleep between increments of the counter (Burns: Fig. 5B Elements 560 and 580).
It would be obvious to combine the sleep period as taught by Burns with the method as taught by Salmon as both teachings are directed towards digital design. One with ordinary skill in the art would be motivated to combine the teachings of Salmon and Burns because the improvement of Burns lies in conserving power (Burns: Col. 21 Lines 62-65).
Claims 5, 12, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Salmon further in view of Greiner et al. (US 2014/0270162 A1) (hereinafter “Greiner”), further in view of Wang et al. (US 2020/0042219 A1) (hereinafter “Wang”).
Regarding claim 5, while Salmon teaches the method of claim 1, Salmon does not explicitly teach caches associated with the processing or the periodic flushing of caches.
However, Greiner teaches caches associated with the processing (Greiner: ¶ 0244 and ¶ 0247).
It would be obvious to combine the caches as taught by Greiner with the method as taught by Salmon as both teachings are directed towards pseudorandom number generators. One with ordinary skill in the art would combine the teachings of Salmon and Greiner in order to improve processor performance (Greiner: ¶ 0261).
Salmon in view of Greiner does not explicitly teach periodically flushing the caches.
However, Wang teaches the caches being flushed periodically (Wang: ¶ 0049).
It would be obvious to combine the periodic cache flushes as taught by Wang with the method and caches as taught by Salmon in view of Greiner as all teachings are directed towards random number generation. One with ordinary skill in the art would combine the teachings of Salmon, Greiner, and Wang to improve CPU cache efficiency (Wang: ¶ 0096).
Claim 12 recites the non-transitory computer readable storage medium having instructions stored thereon for executing the method of claim 5 and is therefore rejected for the same reasons. Greiner additionally teaches a non-transitory computer readable storage with the program for performing the pseudorandom number generator method (Greiner: ¶ 0230).
Claim 19 recites the computer system for performing the method of claim 5 and is therefore rejected for same reasons therein. Salmon additionally teaches the CPU as part of the computer system to perform the pseudo random number generation (Salmon: Pg. 8 Col. 2 footnote 12 Lines 1-2 program run on 3.07 GHz quad-core Intel Xeon X 5667 CPU) and Greiner additionally teaches a non-transitory computer readable storage with the program for performing the pseudorandom number generator method (Greiner: ¶ 0230).
Claims 6-7, 8-9, 13-14, 15-16, and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Salmon in view of Greiner.
Regarding claim 6, while Salmon teaches the method of claim 1, Salmon does not explicitly teach an entropy sample being provided to the random number generator for generating random numbers.
However, Greiner teaches a reseed counter that is used for generating a seed material, this seed material being provided to a random number generator for generating random numbers (Greiner: ¶ 0065).
It would be obvious to combine the entropy sample being provided to the random number generator as taught by Greiner with the method as taught by Salmon as both teachings are directed towards pseudorandom number generation. One with ordinary skill in the art would combine the teachings of Salmon and Greiner in order to further add randomness (Greiner: ¶ 0108).
Regarding claim 7, Salmon in view of Greiner further teaches the entropy sample i.e., seed material being used as a seed value for initializing a pseudorandom number generator (Greiner: ¶ 0039 the value from the counter operations is used as an entropy sample i.e., seed material as discussed in ¶ 0065 to provide seed value to the pseudorandom number generator as discussed in ¶ 0054).
The motivation to combine with respect to claim 6 applies equally to claim 7.
Regarding claim 8, Salmon teaches:
initializing a shared counter (Salmon: Pg. 9 Col. 2 Section 5.1 Lines 19-39 a shared counter n is initialized by computer system);
creating a plurality of software processes, each software process being programmed to increment the shared counter a predefined number of times (Salmon: Pg. 9 Col. 2 Section 5.1 Lines 1-4 streams i.e., software processes; Pg. 9 Col. 2 Section 5.1 Lines 19-39 shared counter n is incremented by plurality of software processes based on key, or identifier of process that increments the counter, and time);
running the plurality of software processes concurrently (Salmon: Pg. 9 Col. 2 Section 5.1 Lines 1-4 streams i.e., software processes running in parallel i.e., concurrently);
upon completion of the plurality of software processes, applying one or more functions to the shared counter, the applying resulting in a value (Salmon: Pg. 2 Col. 1 Lines 12-17 function applied to counter to provide random number value xn as output value);
outputting the value (Salmon: Pg. 2 Col. 1 Lines 12-17 function applied to counter to provide random number value xn as output value).
Salmon does not explicitly teach these instructions being stored on a non-transitory computer readable medium to be executed.
However, Greiner teaches a non-transitory computer readable storage with the program for performing the pseudorandom number generator method (Greiner: ¶ 0230).
It would be obvious to combine the non-transitory computer readable medium as taught by Greiner with the instructions to be performed as taught by Salmon as both teachings are directed towards pseudorandom number generation. One with ordinary skill in the art would be motivated to combine the teachings of Salmon and Greiner in order to store computer readable program code means or logic (Greiner: ¶ 0230).
Regarding claim 9, Salmon in view of Greiner further teaches:
The non-transitory computer readable storage medium of claim 8 wherein the computer system is a multiprocessor system (Salmon: Pg. 8 Col. 2 footnote 12 Lines 1-2 program run on 3.07 GHz quad-core Intel Xeon X 5667 CPU i.e., multiprocessor system) and wherein each of the plurality of software processes is run on a separate physical processing core or hardware thread of the multiprocessor system (Salmon: Pg. 9 Col. 2 Section 5.1 Lines 1-4 streams i.e., software processes function on their own computational unit i.e., hardware thread as discussed in Pg. 1 Col. 2 Lines 38-41).
Claims 13-14 recite the non-transitory computer readable storage medium having instructions stored thereon for executing the method of claims 6-7 respectively and are therefore rejected for the same reasons. Greiner additionally teaches a non-transitory computer readable storage with the program for performing the pseudorandom number generator method (Greiner: ¶ 0230).
Regarding claim 15, Salmon teaches:
A computer system comprising:
a central processing unit (CPU) (Salmon: Pg. 8 Col. 2 footnote 12 Lines 1-2 program run on 3.07 GHz quad-core Intel Xeon X 5667 CPU); and
initialize a shared counter (Salmon: Pg. 9 Col. 2 Section 5.1 Lines 19-39 a shared counter n is initialized by computer system);
create a plurality of software processes, each software process being programmed to increment the shared counter a predefined number of times (Salmon: Pg. 9 Col. 2 Section 5.1 Lines 1-4 streams i.e., software processes; Pg. 9 Col. 2 Section 5.1 Lines 19-39 shared counter n is incremented by plurality of software processes based on key, or identifier of process that increments the counter, and time);
run the plurality of software processes concurrently (Salmon: Pg. 9 Col. 2 Section 5.1 Lines 1-4 streams i.e., software processes running in parallel i.e., concurrently);
upon completion of the plurality of software processes, apply one or more functions to the shared counter, the applying resulting in a value (Salmon: Pg. 2 Col. 1 Lines 12-17 function applied to counter to provide random number value xn as output value);
output the value (Salmon: Pg. 2 Col. 1 Lines 12-17 function applied to counter to provide random number value xn as output value).
Salmon does not explicitly teach these instructions being stored on a non-transitory computer readable medium to be executed.
However, Greiner teaches a non-transitory computer readable storage with the program for performing the pseudorandom number generator method (Greiner: ¶ 0230).
The motivation to combine with respect to claim 8 applies equally to claim 15.
Regarding claim 16, Salmon in view of Greiner further teaches:
The computer system of claim 15 wherein the CPU comprises a plurality of physical processing cores or hardware threads (Salmon: Pg. 8 Col. 2 footnote 12 Lines 1-2 program run on 3.07 GHz quad-core Intel Xeon X 5667 CPU i.e., has multiple processing cores) and wherein each of the plurality of software processes is run on a separate physical processing core or hardware thread of the multiprocessor system (Salmon: Pg. 9 Col. 2 Section 5.1 Lines 1-4 streams i.e., software processes function on their own computational unit i.e., hardware thread as discussed in Pg. 1 Col. 2 Lines 38-41).
Claims 20-21 recite the computer system that performs the method of claims 6-7 respectively and are therefore rejected for the same reasons therein.
Claims 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Salmon in view of Greiner in view of North.
Claim 10 recites the non-transitory computer readable storage medium having instructions stored thereon for executing the method of claim 3 and is therefore rejected for the same reasons. Greiner additionally teaches a non-transitory computer readable storage with the program for performing the pseudorandom number generator method (Greiner: ¶ 0230).
Claim 17 recites the computer system that performs the method of claim 3 and is therefore rejected for the same reasons therein.
Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Salmon in view of Greiner in view of Burns.
Claim 11 recites the non-transitory computer readable storage medium having instructions stored thereon for executing the method of claim 4 and is therefore rejected for the same reasons. Greiner additionally teaches a non-transitory computer readable storage with the program for performing the pseudorandom number generator method (Greiner: ¶ 0230).
Claim 18 recites the computer system that performs the method of claim 4 and is therefore rejected for the same reasons therein.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Voldman (6487571) teaches a method for generating random numbers through the use of a first and second processing thread running on separate processing units that read and write to a shared memory space.
Everspaugh et al. (“No-So-Random Numbers in Virtualized Linux and the Whirlwind RNG”, 2014) teaches virtual-machine based random number generators utilizing CPU cycle counters.
Widynski (“Squares: A Fast Counter-Based RNG”, March 15 2022) teaches a counter-based RNG using a John von Neumann’s middle-square implementation.
Conclusion
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/M.D.R./Examiner, Art Unit 2182
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182