DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figures 1A and 1E should be designated by a legend such as --Prior Art-- because only that which is old is illustrated (see description at paras. [0041] and [0048], respectively). See MPEP § 608.02(g).
The drawings are objected to because FIG. 1E appears to show a lead line with no associated reference numeral, specifically as directed to what appears to be a dielectric on the right side of the left one of the fins 156.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “168” has been used to designate both a conductive trench contact and a dielectric layer in paragraph [0052].
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Paragraph [0006]: “illustrating” should read “illustrate”;
Paragraph [0021]: reference to section 112, 6th paragraph should be updated to the AIA code;
Paragraph [0032]: it is unclear why “Surface Area” is capitalized here whereas elsewhere in the specification it is not;
Paragraph [0046]: there appears to be a mark-up deletion inadvertently left in place;
Paragraphs [0050] and [0051]: “overly” should read “overlie”; and
Paragraph [0054]: “illustrating” should read “illustrate”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiang, Kuo-Cheng, et al., US 2021/0305381 A1 (hereinafter “Chiang”). FIGS. 14B and 14D of Chiang are reproduced herein for reference.
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Regarding claim 1, Chiang discloses an integrated circuit structure (see generally FIGS. 14B – 14E, paras. [0047] – [0049], semiconductor device 200), comprising:
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a plurality of stacks of nanowires (see paragraphs [0015] – [0017], semiconductor layers 215);
a plurality of epitaxial source or drain structures around ends of corresponding ones of the stacks of nanowires (see paras. [0035] – [0036], S/D features 260);
a silicide layer on an entirety of a top surface of the plurality of epitaxial source or drain structures (see FIGS. 14B and 14D, paras. [0047] – [0048], silicide features 273);
a conductive trench contact on the silicide layer (see id., S/D contacts 275); and
a dielectric layer vertically intervening between a portion of the conductive trench contact and the silicide layer (see paras. [0022] – [0024], dielectric liner 232 and dielectric helmet 234).
Regarding claim 3, Chiang discloses the integrated circuit structure of claim 1 as above, and further discloses wherein the plurality of epitaxial source or drain structures is a plurality of merged epitaxial source or drain structures (as illustrated in FIGS. 14B and 14D, above).
Regarding claim 5, Chiang discloses the integrated circuit of claim 1 as above, and further discloses wherein the silicide layer comprises titanium and silicon, or molybdenum and silicon, or tungsten and silicon (see para. [0048], disclosing WSi and TiSi).
Claims 6, 8, 10, and 16 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lavric, Dan S., et al., US 2021/0408258 A1 (hereinafter “Lavric”). FIG. 1A of Lavric is reproduced herein for reference.
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Regarding claim 6, Lavric discloses an integrated circuit structure (see generally FIG. 1A and paras. [0028] – [0035], integrated circuit structure 100), comprising:
a plurality of fins (see para. [0029], fins 102);
a plurality of epitaxial source or drain structures overlying ends of corresponding ones of the fins (see para. [0029], epitaxial source or drains structures 104);
a silicide layer on an entirety of a top surface of the plurality of epitaxial source or drain structures (see para. [0029], titanium mono-silicide (TiSi) layer 110);
a conductive trench contact on the silicide layer (see para. [0035], referring to trench contact (TCN)); and
a dielectric layer vertically intervening between a portion of the conductive trench contact and the silicide layer (see para. [0029], dielectric walls 106 and dielectric spacer 108).
Regarding claim 8, Lavric discloses the integrated circuit structure of claim 6 as above, and further discloses wherein the plurality of epitaxial source or drain structures is a plurality of merged epitaxial source or drain structures (as illustrated in FIG. 1A, above).
Regarding claim 10, Lavric discloses the integrated circuit structure of claim 6 as above, and further discloses wherein the silicide layer comprises titanium and silicon, or molybdenum and silicon, or tungsten and silicon (see paras. [0028] – [0035], disclosing titanium mono-silicide (TiSi) and titanium di-silicide (TiSi2)).
Regarding claim 16, as noted above in connection with claim 6, Lavric discloses an integrated circuit structure (see generally FIG. 1A and paras. [0028] – [0035], integrated circuit structure 100), comprising:
a plurality of fins (see para. [0029], fins 102);
a plurality of epitaxial source or drain structures overlying ends of corresponding ones of the fins (see para. [0029], epitaxial source or drains structures 104);
a silicide layer on an entirety of a top surface of the plurality of epitaxial source or drain structures (see para. [0029], titanium mono-silicide (TiSi) layer 110);
a conductive trench contact on the silicide layer (see para. [0035], referring to trench contact (TCN)); and
a dielectric layer vertically intervening between a portion of the conductive trench contact and the silicide layer (see para. [0029], dielectric walls 106 and dielectric spacer 108).
Lavric further discloses that the integrated circuit structure is included in a computing device (see FIG. 8 and paras. [0088] – [0094], computing device 800), which includes a board (motherboard 802) and a component (the IC structure, being within processor 804) coupled to the board.
Regarding claim 17, Lavric discloses the computing device of claim 16 as above, and further discloses a memory coupled to the board (see FIG. 8, e.g., DRAM).
Regarding claim 18, Lavric discloses the computing device of claim 16 as above, and further discloses a communication chip coupled to the board (see FIG. 8, paras. [0088] and [0090], communication chip 806).
Regarding claim 19, Lavric discloses the computing device of claim 16 as above, and further discloses wherein the component is a packaged integrated circuit die (see para. [0091]).
Regarding claims 20, Lavric discloses the computing device of claim 16 as above, and further discloses wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (see FIG. 8, paras. [0088] and [0091], processor 804).
Claim 7 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Qi, Yi, et al., US 2019/0312117 A1 (hereinafter “Qi”). A portion of FIG. 13 of Qi is reproduced herein for reference.
Regarding claim 7, Qi discloses an integrated circuit structure (see generally FIG. 13 and paras. [0012] – [0028], integrated circuit 100), comprising:
a plurality of fins (see paras. [0012] – [0016], fins 103A, 103B);
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a plurality of epitaxial source or drain structures overlying ends of corresponding ones of the fins (see paras. [0019] – [0020], epitaxial source or drains structures 118);
a silicide layer on an entirety of a top surface of the plurality of epitaxial source or drain structures (see paras. [0024] – [0027], silicide material 132);
a conductive trench contact on the silicide layer (see paras. [0025] – [0026], conductive S/D structure 140); and
a dielectric layer vertically intervening between a portion of the conductive trench contact and the silicide layer (see paras. [0021] – [0022], insulating material 124)
wherein the silicide layer is on all outer surfaces of the plurality of epitaxial source or drain structures (as illustrated in FIG. 13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang in view of Radosavljevic; Marko, et al., US 2013/0270512 A1 (hereinafter “Radosavljevic”).
Regarding claim 4, Chiang discloses the integrated circuit structure of claim 1 as above, but does not explicitly disclose wherein the plurality of epitaxial source or drain structures is a plurality of non-merged epitaxial source or drain structures. In a related art, Radosavljevic discloses a nanowire CMOS IC have NMOS and PMOS portions separated from one another (i.e., their S/D structures are not merged) (see FIG. 1, paras. [0023] – [0029], PMOS nanowire device 110 and NMOS nanowire device 120; separate S/D regions 113, 123). It is prima facie obvious to combine prior art elements according to known methods to yield predictable results. (See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 415 – 21 (2007); MPEP 2143(I)(A).) Chiang discloses a nanowire IC with merged epitaxial S/D structures. Radosavljevic discloses a nanowire IC with separate areas for NMOS and PMOS. Combining the disclosures of Chiang and Radosavljevic would predictably result in an overall nanowire IC where the nanowire features of Chiang (i.e. as shown in FIGS. 14B and 14D, above) would have been replicated in separate areas for PMOS and NMOS, those separate areas would therefore not have had merged S/D structures, even though within each PMOS/NMOS they would have been merged as illustrated in Chiang. Stated alternatively, the combination of Chiang and Radosavljevic would have resulted in Chiang being expanded to a CMOS IC with separate, non-S/D merged PMOS and NMOS areas of the IC. Accordingly, it would have been prima facie obvious to person having ordinary skill in the art to have combined the disclosures of Chiang and Radosavljevic in the manner noted above.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lavric in view of Glass, Glenn A., et al., US 2017/0133376 A1 (hereinafter “Glass-1”).
Regarding claim 9, Lavric discloses the integrated circuit structure of claim 6 as above, but does not explicitly disclose wherein the plurality of epitaxial source or drain structures is a plurality of non-merged epitaxial source or drain structures. In a related art, Glass-1 discloses a finFET CMOS IC have NMOS and PMOS portions separated from one another (i.e., their S/D structures are not merged) (see FIG. 6A, para. [0028], NMOS fin 210 and PMOS fin 220; see also para. [0033] describing the S/D regions). As noted above, it is prima facie obvious to combine prior art elements according to known methods to yield predictable results. (See KSR v. Teleflex, supra; MPEP 2143(I)(A).) Lavric discloses a finFET IC with merged epitaxial S/D structures. Glass-1 discloses a finFET IC with separate areas for NMOS and PMOS. Combining the disclosures of Lavric and Glass-1 would predictably result in an overall finFET IC where the finFET features of Lavric (i.e. as shown in FIG. 1A, above) would have been replicated in separate areas for PMOS and NMOS, those separate areas would therefore not have had merged S/D structures, even though within each PMOS/NMOS they would have been merged as illustrated in Lavric. Stated alternatively, the combination of Lavric and Glass-1 would have resulted in Lavric being expanded to a CMOS IC with separate, non-S/D merged PMOS and NMOS areas of the IC. Accordingly, it would have been prima facie obvious to person having ordinary skill in the art to have combined the disclosures of Lavric and Glass-1 in the manner noted above.
Claims 11 – 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang in view of Glass, Glenn A., et al., US 2014/0001520 A1 (hereinafter “Glass-2”).
Regarding claim 11, as noted above in connection with claim 1, Chiang discloses an integrated circuit structure (see generally FIGS. 14B – 14E, paras. [0047] – [0049], semiconductor device 200), comprising:
a plurality of stacks of nanowires (see paragraphs [0015] – [0017], semiconductor layers 215);
a plurality of epitaxial source or drain structures around ends of corresponding ones of the stacks of nanowires (see paras. [0035] – [0036], S/D features 260);
a silicide layer on an entirety of a top surface of the plurality of epitaxial source or drain structures (see FIGS. 14B and 14D, paras. [0047] – [0048], silicide features 273);
a conductive trench contact on the silicide layer (see id., S/D contacts 275); and
a dielectric layer vertically intervening between a portion of the conductive trench contact and the silicide layer (see paras. [0022] – [0024], dielectric liner 232 and dielectric helmet 234).
Chiang differs from claim 11 in that it does not disclose a computing device, comprising: a board; and a component coupled to the board, the component including the integrated circuit structure. In a related art, Glass-2 discloses a nanowire IC device (500) that is configured in a computing device (computing device 600), comprising: a board (motherboard 602); and a component coupled to the board (processor 604), the component including the integrated circuit structure (see FIG. 6, paras. [0061] – [0067]). As noted above, it is prima facie obvious to combine prior art elements according to known methods to yield predictable results. (See KSR v. Teleflex, supra; MPEP 2143(I)(A).) Chiang discloses an integrated circuit structure of the nanowire type recited in claim 11. Glass-2 discloses a computing device including a nanowire IC. It would have therefore have been readily predictable that the IC of Chiang could have been combined with the computing device of Glass-2, as both use nanowire-type ICs, and it would have been understood as useful to implement the IC of Chiang in a practical application. Accordingly, it would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application to have combined the disclosures of Chiang and Glass-2 in the manner noted above.
Regarding claim 12, Chiang in view of Glass-2 is relied upon for the computing device of claim 11 as above, and Glass-2 further discloses a memory coupled to the board (see FIG. 6, e.g., DRAM).
Regarding claim 13, Chiang in view of Glass-2 is relied upon for the computing device of claim 11 as above, and Glass-2 further discloses a communication chip coupled to the board (see FIG. 6, paras. [0061] and [0063], communication chip 606).
Regarding claim 14, Chiang in view of Glass-2 is relied upon for the computing device of claim 11 as above, and Glass-2 further discloses wherein the component is a packaged integrated circuit die (see para. [0064]).
Regarding claims 15, Chiang in view of Glass-2 is relied upon for the computing device of claim 11 as above, and Glass-2 further discloses wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (see FIG. 6, paras. [0061] and [0064], processor 604).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: No prior art reference found during the search conducted in connection with the present application would appear to disclose or fairly suggest the further limitation wherein the silicide layer is on all outer surfaces of the plurality of epitaxial source or drain structures, in connection with source / drain structures around ends of a plurality of stacks of nanowires. Rather, the prior art found, with respect to silicide formation, is similar to that described and illustrated in Chiang, where the silicide is only formed on a portion of the S/D structures that contact with the stacks of nanowire. Accordingly, claim 1, if re-written in independent form, would appear to recite allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Wang, Chen-Han, et al., US 2023/0268422 A1, disclosing finFET structures with silicide surrounding the S/D regions (see FIG. 14 and paras. [0010] – [0028], for example);
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ryan Fortin whose telephone number is 703-756-5649. The examiner can normally be reached on Monday – Friday from 8:30 AM to 12:30 PM and from 2:30 PM to 6:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo, can be reached at telephone number 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.T.F./
Examiner, Art Unit 2897
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights