DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Status of claim(s) to be treated in this office action:
Independent: 8, 21 and 30.
Pending: 8-10 and 21-36.
Canceled: 1-7 and 11-20.
Newly added: 21-36.
Withdrawn: 27
Response to Arguments
Applicant's arguments filed 9/18/2025 have been fully considered but they are not persuasive. Applicants argue, regarding Claim 8, references fails to teach or suggest at least the limitation "the first plated layer extending on the first and second surfaces of the conductive lead and including cobalt boride, and the second plated layer extending on the first plated layer and including gold" because a person of ordinary skill in the art would not be motivated to modify Ziglioli with Daubenspeck. Applicants argue since Ziglioli device would be within the package and would not exposed to outside environment and would not been obvious to combine Daubenspeck’s plated cobalt boride layer in between copper layer and gold plated layer however Examiner disagree, by having Daubenspeck’s cobalt boride material in between a copper and gold plated can act as highly effective diffusion barrier and improve durability of the gold layer (Daubenspeck:¶0072), therefore, Ziglioli and Daubenspeck in combination clearly teaches the limitation and the rejection is maintained. Similar reasons against the combination of Ziglioli and Daubenspeck apply to independent claims 21 and 30.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-10, 21-26 and 28-36 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ziglioli US patent 10930581 in view of Daubenspeck et al., US PG pub. 20120025383 A1.
Re: Independent Claim 8, Ziglioli discloses a package structure (100, fig. 1A and fig. 1B) having six sides, the six sides including opposite first and second sides (left and right sides surface of 100, fig. 1a and 1b) spaced apart from one another along a first direction (horizontal direction, fig. 1b), opposite third and fourth sides (top and bottom side of 100, fig. 1b) spaced apart from one another along a second direction (vertical direction, fig. 1b) that is orthogonal to the first direction (horizontal direction, fig. 1b), and opposite fifth and sixth sides (bottom and top side of 100, fig. 1a) spaced apart from one another along a third direction (up and down direction in figure 1a) that is orthogonal to the first and second direction (vertical direction, fig. 1b)s; and a conductive lead (110 and 132, fig. 1a) having a first surface (left side surface of 100, fig. 1a), a second surface (bottom surface of 100, fig. 1a), a first plated layer (140, fig. 1a),
Ziglioli is silent regarding: a second plated layer, the first surface (left side surface of 100, fig. 1a) extending along the first side (left side surface of 100, fig. 1a) of the package structure (100, fig. 1A and fig. 1B), and the second surface (bottom surface of 100, fig. 1a) extending along the fifth side (bottom surface of 100, fig. 1a) of the package structure (100, fig. 1A and fig. 1B), the first plated layer (140, fig. 1a) extending on the first and second surfaces left side surface of 100 and (bottom surface of 100, fig. 1a) of the conductive lead (110 and 132, fig. 1a) and including cobalt boride, and the second plated layer extending on the first plated layer (140, fig. 1a) and including gold (column 3, lines 46-48).
Daubenspeck discloses in figure 1A, a plated cobalt boride layer 108 formed between a conductive lead 107 and a gold plated layer 109 wherein an solder layer 110 formed attached to gold plated layer 109.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include Daubenspeck’s cobalt boride plated layer in between Ziglioli’s conductive lead and gold plated layer since material cobalt boride has a high resistant to oxidation, which makes it useful for coating metal parts to increase lifespan of the gold and conductive lead which can improve conductivity and long lasting performance, Daubenspeck further teaches in paragraph 72 cobalt boride plated used as a barrier plate between conductive lead 107 and a gold plated layer 109 which can be an effective diffusion barrier.
Re: Claim 9, Ziglioli and Daubenspeck discloses all the limitations of claim 8 on which this claim depends. Ziglioli further discloses: a second conductive lead (110 and 132, fig. 1a) having a first surface (left side surface of 100, fig. 1a), a second surface (bottom surface of 100, fig. 1a), a first plated layer (140, fig. 1a).
Ziglioli is silent regarding: a second plated layer, the first surface (left side surface of 100, fig. 1a) of the second conductive lead (110 and 132, fig. 1a) extending along the second side (right side surface of 100, fig. 1a) of the package structure (100, fig. 1A and fig. 1B), and the second surface (bottom surface of 100, fig. 1a) of the second conductive lead (110 and 132, fig. 1a) extending along the fifth side (bottom surface of 100, fig. 1a) of the package structure (100, fig. 1A and fig. 1B), the first plated layer (140, fig. 1a) of the second conductive lead (110 and 132, fig. 1a) extending on the first and second surfaces left side surface of 100 and (bottom surface of 100, fig. 1a) of the second conductive lead (110 and 132, fig. 1a) and including cobalt boride, and the second plated layer of the second conductive lead (110 and 132, fig. 1a) extending on the first plated layer (140, fig. 1a) of the second conductive lead (110 and 132, fig. 1a) and including gold (column 3, lines 46-48).
Daubenspeck discloses in figure 1A, a plated cobalt boride layer 108 formed between a conductive lead 107 and a gold plated layer 109 wherein an solder layer 110 formed attached to gold plated layer 109.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include Daubenspeck’s cobalt boride plated layer in between Ziglioli’s conductive lead and gold plated layer since material cobalt boride has a high resistant to oxidation, which makes it useful for coating metal parts to increase lifespan of the gold and conductive lead which can improve conductivity and long lasting performance.
Re: Claim 10, Ziglioli and Daubenspeck discloses all the limitations of claim 9 on which this claim depends. Ziglioli further discloses: a third conductive lead (110 and 132, fig. 1a) having a first surface (left side surface of 100, fig. 1a), a second surface (bottom surface of 100, fig. 1a), a first plated layer (140, fig. 1a).
Ziglioli is silent regarding: a second plated layer, the first surface (left side surface of 100, fig. 1a) of the third conductive lead (110 and 132, fig. 1a) extending along the third side of the package structure (100, fig. 1A and fig. 1B), and the second surface (bottom surface of 100, fig. 1a) of the third conductive lead (110 and 132, fig. 1a) extending along the fifth side (bottom surface of 100, fig. 1a) of the package structure (100, fig. 1A and fig. 1B), the first plated layer (140, fig. 1a) of the third conductive lead (110 and 132, fig. 1a) extending on the first and second surfaces left side surface of 100 and (bottom surface of 100, fig. 1a) of the third conductive lead (110 and 132, fig. 1a) and including cobalt boride, and the second plated layer of the third conductive lead (110 and 132, fig. 1a) extending on the first plated layer (140, fig. 1a) of the third conductive lead (110 and 132, fig. 1a) and including gold (column 3, lines 46-48); and a fourth conductive lead (110 and 132, fig. 1a) having a first surface (left side surface of 100, fig. 1a), a second surface (bottom surface of 100, fig. 1a), a first plated layer (140, fig. 1a), and a second plated layer, the first surface (left side surface of 100, fig. 1a) of the fourth conductive lead (110 and 132, fig. 1a) extending along the fourth side of the package structure (100, fig. 1A and fig. 1B), and the second surface (bottom surface of 100, fig. 1a) of the fourth conductive lead (110 and 132, fig. 1a) extending along the fifth side (bottom surface of 100, fig. 1a) of the package structure (100, fig. 1A and fig. 1B), the first plated layer (140, fig. 1a) of the fourth conductive lead (110 and 132, fig. 1a) extending on the first and second surfaces left side surface of 100 and (bottom surface of 100, fig. 1a) of the fourth conductive lead (110 and 132, fig. 1a) and including cobalt boride, and the second plated layer of the fourth conductive lead (110 and 132, fig. 1a) extending on the first plated layer (140, fig. 1a) of the fourth conductive lead (110 and 132, fig. 1a) and including gold (column 3, lines 46-48).
Daubenspeck discloses in figure 1A, a plated cobalt boride layer 108 formed between a conductive lead 107 and a gold plated layer 109 wherein an solder layer 110 formed attached to gold plated layer 109.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include Daubenspeck’s cobalt boride plated layer in between Ziglioli’s conductive lead and gold plated layer since material cobalt boride has a high resistant to oxidation, which makes it useful for coating metal parts to increase lifespan of the gold and conductive lead which can improve conductivity and long lasting performance, Daubenspeck further teaches in paragraph 72 cobalt boride plated used as a barrier plate between conductive lead 107 and a gold plated layer 109 which can be an effective diffusion barrier.
Re: Independent Claim 21, Ziglioli discloses a semiconductor die (106, fig. 1a and 1b) electrically connected to a lead (110 and 132, fig. 1a); and a mold compound (130, fig. 1a and 1b) contacting the semiconductor die (106, fig. 1a and 1b) and the lead (110 and 132, fig. 1a), wherein the lead (110 and 132, fig. 1a) includes at least a first surface (left side surface of 100, fig. 1a) not in contact with the mold compound (130, fig. 1a and 1b), the at least one first surface (left side surface of 100, fig. 1a) in contact with a layer (140, fig. 1a-1b).
Ziglioli is silent regarding: lead (110 and 132, fig. 1a) is contact with of cobalt boride.
Daubenspeck discloses in figure 1A, a plated cobalt boride layer 108 formed between a lead 107 and a gold plated layer 109 wherein an solder layer 110 formed attached to gold plated layer 109.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include Daubenspeck’s cobalt boride plated layer in between Ziglioli’s lead and gold plated layer since material cobalt boride has a high resistant to oxidation, which makes it useful for coating metal parts to increase lifespan of the gold and conductive lead which can improve conductivity and long lasting performance, Daubenspeck further teaches in paragraph 72 cobalt boride plated used as a barrier plate between conductive lead 107 and a gold plated layer 109 which can be an effective diffusion barrier.
Re: Claim 22, Ziglioli and Daubenspeck discloses all the limitations of claim 21 on which this claim depends. Ziglioli is silent regarding: wherein the layer of cobalt boride projects from a surface of the electronic device.
Daubenspeck discloses in figure 1A, a plated cobalt boride layer 108 formed between a lead 107 and a gold plated layer 109 wherein an solder layer 110 formed attached to gold plated layer 109.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include Daubenspeck’s cobalt boride plated layer projects in between Ziglioli electronic device’s lead and gold plated layer since material cobalt boride has a high resistant to oxidation, which makes it useful for coating metal parts to increase lifespan of the gold and conductive lead which can improve conductivity and long lasting performance, Daubenspeck further teaches in paragraph 72 cobalt boride plated used as a barrier plate between conductive lead 107 and a gold plated layer 109 which can be an effective diffusion barrier.
Re: Claim 23, Ziglioli and Daubenspeck discloses all the limitations of claim 22 on which this claim depends. Ziglioli further discloses: wherein the surface of the electronic device includes the mold compound (130, fig. 1a and 1b).
Re: Claim 24, Ziglioli and Daubenspeck discloses all the limitations of claim 21 on which this claim depends. Ziglioli further discloses: wherein the lead (110 and 132, fig. 1a) includes copper (column 2, lines 15-17).
Re: Claim 25, Ziglioli and Daubenspeck discloses all the limitations of claim 21 on which this claim depends. Ziglioli further discloses: wherein the semiconductor die (106, fig. 1a and 1b) is electrically connected to the lead (110 and 132, fig. 1a) via a bond wire (122, fig. 1a).
Re: Claim 26, Ziglioli and Daubenspeck discloses all the limitations of claim 21 on which this claim depends. Ziglioli further discloses: wherein the electronic device (100, fig. 1a-1b) is a quad flat no lead (QFN) package (as shown in figure 1a and 1b).
Re: Claim 28, Ziglioli and Daubenspeck discloses all the limitations of claim 21 on which this claim depends. Ziglioli further discloses: wherein the semiconductor die (106, fig. 1a and 1b) is on a die attach pad (102, fig. 1a).
Re: Claim 29, Ziglioli and Daubenspeck discloses all the limitations of claim 21 on which this claim depends. Ziglioli is silent regarding: wherein the layer of cobalt boride is a plated layer.
Daubenspeck discloses in figure 1A, a plated cobalt boride layer 108 formed between a lead 107 and a gold plated layer 109 wherein an solder layer 110 formed attached to gold plated layer 109.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include Daubenspeck’s cobalt boride plated layer projects in between Ziglioli electronic device’s lead and gold plated layer since material cobalt boride has a high resistant to oxidation, which makes it useful for coating metal parts to increase lifespan of the gold and conductive lead which can improve conductivity and long lasting performance, Daubenspeck further teaches in paragraph 72 cobalt boride plated used as a barrier plate between conductive lead 107 and a gold plated layer 109 which can be an effective diffusion barrier.
Re: Independent Claim 30, Ziglioli discloses a semiconductor die (106, fig. 1a and 1b) electrically connected to a lead (110 and 132, fig. 1a); and a mold compound (130, fig. 1a and 1b) contacting the semiconductor die (106, fig. 1a and 1b) and the lead (110 and 132, fig. 1a), wherein the lead (110 and 132, fig. 1a) includes at least a first surface (left side surface of 100, fig. 1a) not in contact with the mold compound (130, fig. 1a and 1b).
Ziglioli is silent regarding: the at least one first surface (left side surface of 100, fig. 1a) in contact with a first layer including cobalt, and the first layer in contact with a second layer (140, fig. 1a-1b) including gold (column 3, lines 46-48).
Daubenspeck discloses in figure 1A, a plated cobalt boride layer 108 formed between a lead 107 and a gold plated layer 109 wherein an solder layer 110 formed attached to gold plated layer 109.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include Daubenspeck’s cobalt boride plated layer as the second layer projects in between Ziglioli electronic device’s lead and gold plated layer as the first layer since material cobalt boride has a high resistant to oxidation, which makes it useful for coating metal parts to increase lifespan of the gold and conductive lead which can improve conductivity and long lasting performance, Daubenspeck further teaches in paragraph 72 cobalt boride plated used as a barrier plate between conductive lead 107 and a gold plated layer 109 which can be an effective diffusion barrier.
Re: Claim 31, Ziglioli and Daubenspeck discloses all the limitations of claim 30 on which this claim depends. Ziglioli is silent regarding: wherein the first layer and the second layer (140, fig. 1a-1b) project from a surface of the electronic device (100, fig. 1a-1b).
Daubenspeck discloses in figure 1A, a plated cobalt boride layer 108 formed between a lead 107 and a gold plated layer 109 wherein an solder layer 110 formed attached to gold plated layer 109.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include Daubenspeck’s cobalt boride plated layer as the second layer projects in between Ziglioli electronic device’s lead and gold plated layer as the first layer since material cobalt boride has a high resistant to oxidation, which makes it useful for coating metal parts to increase lifespan of the gold and conductive lead which can improve conductivity and long lasting performance, Daubenspeck further teaches in paragraph 72 cobalt boride plated used as a barrier plate between conductive lead 107 and a gold plated layer 109 which can be an effective diffusion barrier.
Re: Claim 32, Ziglioli and Daubenspeck discloses all the limitations of claim 30 on which this claim depends. Ziglioli is silent regarding: wherein the first layer includes cobalt boride.
Daubenspeck discloses in figure 1A, a plated cobalt boride layer 108 formed between a lead 107 and a gold plated layer 109 wherein an solder layer 110 formed attached to gold plated layer 109.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include Daubenspeck’s cobalt boride plated layer as the second layer projects in between Ziglioli electronic device’s lead and gold plated layer as the first layer since material cobalt boride has a high resistant to oxidation, which makes it useful for coating metal parts to increase lifespan of the gold and conductive lead which can improve conductivity and long lasting performance, Daubenspeck further teaches in paragraph 72 cobalt boride plated used as a barrier plate between conductive lead 107 and a gold plated layer 109 which can be an effective diffusion barrier.
Re: Claim 33, Ziglioli and Daubenspeck discloses all the limitations of claim 30 on which this claim depends. Ziglioli further discloses: wherein the surface of the electronic device includes the mold compound (130, fig. 1a and 1b).
Re: Claim 34, Ziglioli and Daubenspeck discloses all the limitations of claim 30 on which this claim depends. Ziglioli further discloses: wherein the lead (110 and 132, fig. 1a) includes copper (column 2, lines 15-17).
Re: Claim 35, Ziglioli and Daubenspeck discloses all the limitations of claim 30 on which this claim depends. Ziglioli further discloses: wherein the semiconductor die (106, fig. 1a and 1b) is electrically connected to the lead (110 and 132, fig. 1a) via a bond wire (122, fig. 1a).
Re: Claim 36, Ziglioli and Daubenspeck discloses all the limitations of claim 30 on which this claim depends. Ziglioli further discloses: wherein the semiconductor die (106, fig. 1a and 1b) is on a die attach pad (102, fig. 1a).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
(“Lei et al., US PG pub. 20120252207 A1”) discloses forming materials on a substrate used for metal gate and other applications. In one embodiment, a method includes forming a cobalt stack over a barrier layer disposed on a substrate by depositing a cobalt layer during a deposition process, exposing the cobalt layer to a plasma to form a plasma-treated cobalt layer during a plasma process, and repeating the cobalt deposition process and the plasma process to form the cobalt stack containing a plurality of plasma-treated cobalt layers. The method further includes exposing the cobalt stack to an oxygen source gas to form a cobalt oxide layer from an upper portion of the cobalt stack during a surface oxidation process and heating the remaining portion of the cobalt stack to a temperature within a range from about 300.degree. C. to about 500.degree. C. to form a crystalline cobalt film during a thermal annealing crystallization process.
(“Zierath et al., US PG pub. 20130270703 A1”) discloses enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on 9-5PM EST.
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/AJAY OJHA/Supervisory Patent Examiner, Art Unit 2898