Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/13/2026 has been entered.
Status of Claims
In the communication filed on 02/13/2026, claims 1-13 and 15-23 are pending. Claims 1, 6-7, 9-13, and 17-19 are amended. Claim 23 is new. Claims 14 is presently cancelled.
Response to Arguments
The prior objections to the Drawings are withdrawn due to the amendments.
Applicant’s arguments with respect to amended independent claims 1, 12, 17, and their dependents have been considered but are moot because the arguments do not apply to the combination of references being used in the current rejection.
Claim Objections
Claims 6-7 and 11 are objected to because of the following informalities:
Claim 6, lines 2-3 recite “based on high voltage indication signal”, which should be revised to “based on the high voltage indication signal”.
Claim 7, line 2 recites “after electrical component”, which should be revised to “after the electrical component”.
Claim 11, line 3 recites “the low pulse”, which should be revised to “the low voltage pulse”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 12-13, 15-16, and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12, lines 13-14 recite “using the at least two discharging paths”. There is insufficient antecedent basis for this claim language. The language is unclear if “discharging paths” are the same as the “first/second discharge path” and the quantity thereof. For examination purposes, this language is interpreted to mean “using the first discharge path and the second discharge path”.
Claims 13, 15-16, and 23 are further rejected for their dependency on other rejected claims.
Claim Rejections - 35 USC § 103
Claims 1-2, 4-5, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Wiederhold et al. (US 2012/0162839 A1; hereinafter “Wied”) in view of Dustert et al. (US 2023/0158896 A1; hereinafter “Dust”).
Regarding Claim 1, Wied discloses an electronic device, comprising the following features.
Wied further discloses a connector (“input connections E1, E2”; Figs. 2-3; ¶ [53]: “E1, E2 are configured … as clamping connections”; ¶ [54]: “E1, E2 are insulated in accordance with the high storage voltages”) configured to couple to an electrical component (“electrical storage element 1”; Fig. 1; ¶ [42]: “E1, E2 which are to be connected to the connections Ea, Eb of the electrical storage element 1”).
Wied further discloses the electrical component (1) is configured to hold an electrical charge (¶ [37]: “1 … is at least one electrical capacitor having a capacitance of 5 mF”; ¶ [37]: “electrical energy stored in … 1 can thus be in the range of up to one watt-hour”).
Wied further discloses a timer circuit (“control device 10”; Fig. 3; ¶ [65]: “a clock generator circuit (not illustrated) having a variable clock ratio can be integrated for example in … the control device 10”) configured to provide a clock signal (output from “10” to “12a”; Fig. 3; ¶ [58]: “driver 12a is driven in a clocked manner by the control device 10”).
Wied further discloses the clock signal (output from “10” to “12a”) oscillating at a clock frequency (Fig. 4 shows the time profile of the switching states of “12” based on the clock signal from “10”; “12” switches at the frequency of the clock signal from “10”; ¶ [15]: “fixed … clock ratio”; ¶ [58]: “a programmed dynamic mark-space ratio (clock ratio)”; ¶ [66-70] describe the switching periods and “clock ratio” in detail).
Wied further discloses a logic circuit (“voltage detection device 9” + “comparison device 14” + “control device 10”; Figs. 2-3) configured to determine whether a voltage (¶ [45]: “storage voltage U1 of the electrical storage element 1”) associated with the electrical component (1) is higher than a threshold (¶ [71]: “proceeding from an initial voltage of 1000 V, the discharge process has ended after … a safe storage voltage of approximately less than 10 V being attained” based on “reference voltage Uref for the comparison device 14”; Thus, the “discharge process” is performed when “U1” > “safe storage voltage” of “10V”; see also ¶ [74, 81]) when the connector (“E1” and “E2” are part of “connection lines 6”; Figs. 2-3) is coupled to the electrical component (“E1” and “E2” connect to “Ea” and “Eb” per ¶ [42, 73]; Figs. 1-3).
Wied further discloses a discharge circuit (“control device 10” + “load device 11” + “switching device 12” + “driver 12a”; Figs. 2-3) comprising at least a first discharge path (path through “11” + “12”; Fig. 3)
Wied further discloses the discharge circuit (10, 11, 12, & 12a) is configured to, in response to the logic circuit (9, 14, 10, 12a, & 12) determining that the voltage (“storage voltage U1”) is higher than the threshold (the “discharge process” is performed when “U1” > “safe storage voltage” of “10V”; ¶ [71, 74, 81]), discharge the electrical component (1).
Wied further discloses closing the first discharge path (11 & 12) upon receipt of the clock signal having a first state (¶ [66]: “12” closes during “first time segment ON”; Fig. 4 shows conduction through “11” & “12” based on the on/off command of the clock signal from “10”) and opening the first discharge path (11 & 12) upon receipt of the clock signal having a second state (¶ [66]: “12” opens during “second time segment OFF”; Fig. 4 shows conduction through “11” & “12” based on the on/off command of the clock signal from “10”).
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As addressed supra, Wied discloses “a discharge circuit comprising at least a first discharge path”. However, Wied does not disclose “a discharge circuit comprising at least a first discharge path and a second discharge path”.
Wied further does not disclose “closing the second discharge path upon receipt of the clock signal having the second state and opening the second discharge path upon receipt of the clock signal having the first state”.
Dust teaches a discharge circuit (205) comprising at least a first discharge path (¶ [36]: “first conduction path between rails 155, 160”; includes “resistance 405” and “switch 415”; Fig. 4) and a second discharge path (¶ [36]: “second conduction path between rails 155, 160”; includes “resistance 410” and “switch 420”; Fig. 4).
Dust further teaches these two discharge paths conduct/open in an alternating manner (paths are commanded to conduct alternatively per ¶ [37]: “switches 415, 420 can be driven … so that they conduct alternatively”).
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Dust further teaches the discharge circuit (205) is configured to discharge the electrical component (“DC link capacitor 140”, coupled to “205” via “step down power converter 150”; Fig. 2) by doing the following.
Dust further teaches the discharge circuit (205) closing the first discharge path (405 & 415) upon receipt of the clock signal (“discharge drive signal DR1”; Figs. 2, 4; ¶ [35]: “DR1 can be a pulse train that drives switch 310 into and out of conduction repeatedly”) having a first state (when “DR1” is logic high state, the N-channel MOSFET “415” is configured to conduct/close the first discharge path).
Dust further teaches the discharge circuit (205) opening the first discharge path (405 & 415) upon receipt of the clock signal (DR1) having a second state (when “DR1” is logic low state, the N-channel MOSFET “415” is configured to open the first discharge path).
Dust further teaches the discharge circuit (205) closing the second discharge path (410 & 420) upon receipt of the clock signal (“DR1”, received by “205”) having the second state (when “DR1” is logic low state, “DR2” is alternatively in the logic high state per ¶ [37]; when “DR2” is logic high state, “420” conducts/closes the second discharge path).
Dust further teaches the discharge circuit (205) opening the second discharge path (410, 420) upon receipt of the clock signal (“DR1”, received by “205”) having the first state (when “DR1” is logic high state, “DR2” is alternatively in the logic low state per ¶ [37]; when “DR2” is logic low state, “420” opens the second discharge path).
Dust further teaches to discharge through only one of the first/second discharge paths at a single time to reduce heating of the resistors in the discharge paths (¶ [38]). This reduces risk of damage from excessive heating (¶ [35]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the discharge circuit disclosed by Wied to incorporate a second discharge path operating alternatively to the first discharge path based on the clock signal state, as taught by Dust, to reduce risk of damage to the resistors in the discharge paths from excessive heating.
Regarding Claim 2, the combo of Wied & Dust teaches the electronic device of claim 1.
Wied further discloses a voltage source (“voltage supply device 8”; Figs. 2-3; ¶ [43]: “serves for the electrical supply of the individual functional devices of the safety discharge apparatus 5”) configured to provide electric power to the timer circuit (“control device 10”; Fig. 3; ¶ [65]: “a clock generator circuit (not illustrated) having a variable clock ratio can be integrated for example in … the control device 10”), the logic circuit (“voltage detection device 9” + “comparison device 14”; Figs. 2-3), and the discharge circuit (“safety discharge apparatus 5”; Figs. 2-3).
Regarding Claim 4, the combo of Wied & Dust teaches the electronic device of claim 1.
Wied discloses the logic circuit (9, 14, 10, & 12a) is configured to provide a high voltage indication signal (clock signal output from “10” to “12a”) to the discharge circuit (“12a” is commanded to drive the switch to close the discharge path in response to a logic high pulse from “10”).
Wied further discloses this occurs in response to the voltage (U1) associated with the electrical component (1) being higher than the threshold (when “U1” > “safe storage voltage” of “10V”; ¶ [71, 74, 81]).
Regarding Claim 5, the combo of Wied & Dust teaches the electronic device of claim 4.
The combo of Wied & Dust (as set forth prior) teaches the discharge circuit (Wied: “10”, “11”, “12”, “12a” + incorporated from Dust: “410” & “420”) is configured to discharge the electrical component (Wied: “1”; Dust equivalent: “140”) by alternatively closing (modification from Dust to operate the two paths in an alternatively closing pattern) the first discharge path (Wied: “11” & “12”; Dust equivalent: “405” & “415”) and the second discharge path (incorporated from Dust: “410” & “420”).
The combo of Wied & Dust teaches the discharging continues until the high voltage indication signal (Wied: clock signal output from “10” to “12a”; Dust equivalent: “DR1”) is no longer provided (see note 5-1 on interpretation, included infra; in the relied-upon references, discharging is performed by the discharge circuit as long as the clock signal is received by the discharge circuit).
NOTE 5-1: The language “until … is no longer provided” is interpreted to only limit the behavior of the discharge circuit while the high voltage indication signal is provided. Thus, the claim language does not limit the operation of the discharge circuit after “the high voltage indication signal is no longer provided”. Thus, the language “until … is no longer provided” is interpreted to permit the discharging to either continue or discontinue after “the high voltage indication signal is no longer provided”.
Regarding Claim 10, the combination of Wied and Dust teaches the electronic device of claim 1.
The combination of Wied and Dust teaches the first state comprises a high voltage pulse of the clock signal (Wied: output from “10” to “12a”, with high voltage pulse turning on “12”; Dust equivalent: “DR1”, with high voltage pulse turning on “415” and turning off “420”).
The combination of Wied and Dust teaches the second state comprises a low voltage pulse of the clock signal (Wied: output from “10” to “12a”, with low voltage pulse turning off “12”; Dust equivalent: “DR1”, with low voltage pulse turning off “415” and turning on “420”).
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Wiederhold et al. (US 2012/0162839 A1; hereinafter “Wied”) in view of Dustert et al. (US 2023/0158896 A1; hereinafter “Dust”), and Lifschits et al. (US 2021/02023220 A1; hereinafter “Lif”).
Regarding Claim 3, the combo of Wied & Dust teaches the electronic device of claim 1.
Wied further discloses the electrical component (1) comprises a capacitor (¶ [37]: “1 … is at least one electrical capacitor having a capacitance of 5 mF”).
Wied implies (¶ [13]: “achieves a high degree of safety in the handling”; ¶ [81]: “process is carried out until the storage value falls below a value regarded as discharged or safe”), but does not explicitly disclose “the threshold corresponds to a sufficiently low discharged voltage to enable an operator associated with the capacitor to handle the capacitor”.
Lif teaches the threshold (“threshold” per ¶ [45, 54-55, 62, 69, 88, 106-107]) corresponds to a sufficiently low discharged voltage (¶ [55]: “a 30 volt safety threshold”) to enable an operator (“safety workers per ¶ [54]; “maintenance workers” per ¶ [55]) associated with the capacitor (“capacitor C” within “power system 100”; Figs. 1A-1H, 2-11) to handle the capacitor (¶ [54-55]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the electronic device disclosed by the combo of Wied & Dust for the threshold to correspond to a safe voltage level for handling, as taught by Lif, to protect workers from exposure to unsafe voltage levels (Lif ¶ [54-55]).
Regarding Claim 8, the combo of Wied & Dust teaches the electronic device of claim 1.
Wied does not disclose “the logic circuit is configured to provide a discharge complete indication signal to the discharge circuit in response to the voltage associated with the electrical component being equal to or below the threshold”.
Lif teaches the logic circuit (“controller 112”; Figs. 1A-1H, 2-11) is configured to provide a discharge complete indication signal (output from “112” to “108”; ¶ [64]: “indication/control of the discharge circuitry may be facilitated by one or more controllers 112”; ¶ [184]: “at least one indication related to ending discharge is obtained”; Fig. 17, step 1710) to the discharge circuit (“108”; Figs. 1A-1H, 2-11).
Lif further teaches this occurs in response to the voltage (¶ [184]: “certain voltage value”) associated with the electrical component (“capacitor C” within “system power device 104”; Figs. 1A-1H, 2-11) being below the threshold (¶ [184]: “the voltage value is less than … a certain threshold”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the logic circuit disclosed by the combo of Wied & Dust to provide a discharge complete indication signal to the discharge circuit, as taught by Lif, to protect workers from exposure to unsafe voltage levels (Lif ¶ [54-55]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Wiederhold et al. (US 2012/0162839 A1; hereinafter “Wied”) in view of Dustert et al. (US 2023/0158896 A1; hereinafter “Dust”), and Marzahn (US 2006/0038463 A1; hereinafter “Marz”).
Regarding Claim 6, the combo of Wied & Dust teaches the electronic device of claim 5.
Naka discloses the high voltage indication signal (clock signal output from “10” to “12a”) no longer being provided (i.e., output from “10” is logic low output) when the electrical component’s voltage (U1) is less than or below a threshold (when “U1” < “safe storage voltage” of “10V”; ¶ [71, 74, 81]).
Naka does not disclose that in this scenario, “the discharge circuit is configured to discharge the electrical component by directly connecting a positive lead of the electrical component to a negative lead of the electrical component”.
Marz teaches that when the electrical component’s voltage is less than or below a threshold (switch “PS” controlled by “control signals s1-3” from “control unit ST”; Figs. 1-2, 4; ¶ [22]: “safety short circuit” applied when “less than 30% of the corresponding voltage in the charge state of the piezoelectric actuator”), the discharge circuit (Figs. 1-2, 4) is configured to discharge the electrical component (“piezoelectric actuator Cp”; Figs. 1-2, 4) by directly connecting (via “additional first discharge switch PS” and “selection switch SS”; Figs. 1-2, 4; ¶ [22]: “safety short circuit” applied when “less than 30% of the corresponding voltage in the charge state of the piezoelectric actuator”) a positive lead (labeled “+” terminal of “Cp”; ¶ [39]: “piezo-connection Cp+”) of the electrical component (Cp) to a negative lead (labeled “-” terminal of “Cp” ; ¶ [39]: “piezo-connection Cp-”) of the electrical component (Cp).
Marz further teaches to directly connect the electrical component’s leads when the voltage is less than or below a threshold to improve operating safety and accelerate the discharge process (Marz ¶ [21]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the discharge circuit disclosed by the combo of Wied & Dust to directly connect the electrical component’s leads when the voltage is less than or below a threshold, as taught by Marz, to improve operating safety and accelerate the discharge process (Marz ¶ [21]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Wiederhold et al. (US 2012/0162839 A1; hereinafter “Wied”) in view of Dustert et al. (US 2023/0158896 A1; hereinafter “Dust”), Marzahn (US 2006/0038463 A1; hereinafter “Marz”), and Lifschits et al. (US 2021/02023220 A1; hereinafter “Lif”).
Regarding Claim 7, the combo of Wied, Dust, & Marz teaches the electronic device of claim 6.
Wied does not disclose “the logic circuit is configured to provide a discharge complete indication signal after electrical component has been discharged”.
Lif teaches the logic circuit (“controller 112”; Figs. 1A-1H, 2-11) is configured to provide a discharge complete indication signal (output from “112” to “108”; ¶ [64]: “indication/control of the discharge circuitry may be facilitated by one or more controllers 112”; ¶ [184]: “at least one indication related to ending discharge is obtained”; Fig. 17, step 1710) after the electrical component (“capacitor C” within “system power device 104”; Figs. 1A-1H, 2-11) has been discharged (¶ [184]: “the voltage value is less than … a certain threshold”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the logic circuit disclosed by the combo of Wied, Dust, & Marz to provide a discharge complete indication signal, as taught by Lif, to protect workers from exposure to unsafe voltage levels (Lif ¶ [54-55]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Wiederhold et al. (US 2012/0162839 A1; hereinafter “Wied”) in view of Dustert et al. (US 2023/0158896 A1; hereinafter “Dust”), Lifschits et al. (US 2021/02023220 A1; hereinafter “Lif”), and Marzahn (US 2006/0038463 A1; hereinafter “Marz”).
Regarding Claim 9, the combination of Wied, Dust, and Lif teaches the electronic device of claim 8.
Wied does not disclose “the discharge circuit is configured to short a positive lead and a negative lead of the electrical component in response to receiving the discharge complete indication signal.”
Marz teaches the discharge circuit (Figs. 1-2, 4) is configured to short (via “additional first discharge switch PS” and “selection switch SS”; Figs. 1-2, 4; ¶ [22]: “safety short circuit” applied when “less than 30% of the corresponding voltage in the charge state of the piezoelectric actuator”) a positive lead (labeled “+” terminal of “Cp”; ¶ [39]: “piezo-connection Cp+”) and a negative lead (labeled “-” terminal of “Cp” ; ¶ [39]: “piezo-connection Cp-”) of the electrical component (“piezoelectric actuator Cp”; Figs. 1-2, 4).
Marz further teaches this occurs in response to receiving the discharge complete indication signal (switch “PS” controlled by “control signals s1-3” from “control unit ST”; Figs. 1-2, 4; ¶ [22]: “safety short circuit” applied when “less than 30% of the corresponding voltage in the charge state of the piezoelectric actuator”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the discharge circuit disclosed by the combo of Wied, Dust, & Lif to incorporate the configuration to short the terminals of the electrical component, as taught by Marz, to improve operating safety and accelerate the discharge process (Marz ¶ [21]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Wiederhold et al. (US 2012/0162839 A1; hereinafter “Wied”) in view of Dustert et al. (US 2023/0158896 A1; hereinafter “Dust”), and Marxer (US 2022/0037992 A1).
Regarding Claim 11, the combination of Wied and Dust teaches the electronic device of claim 10.
The combo of Wied & Dust (as set forth prior) teaches closing the second discharge path (incorp. from Dust: “410” + “420”) in response to the low pulse of the clock signal (Wied: output from “10” to “12a”; Dust equivalent: “DR1”) is based on the second discharge path (Dust: “410” + “420”) receiving an inverted clock signal (incorp. from Dust: “DR2” is alternate/inverted logic from “DR1” per ¶ [37]).
Wied does not disclose “the logic circuit comprises inverter circuitry, and wherein closing the second discharge path in response to the low pulse of the clock signal is based on the second discharge path receiving an inverted clock signal from the inverter circuitry”.
Though Dust teaches the operation of alternating between the two discharge paths, Dust does not provide details as to the hardware implementation to provide the command signals to the two discharge paths. However, it is well-known in the art how to provide an inverted command signal to a second discharge path.
Marxer teaches the logic circuit (combo of “30” and “20”; Fig. 2) comprises inverter circuitry (“20” will invert the logic from the signals at inputs “25b-d” to the output at “15”; Fig. 2).
Marxer further teaches closing the second discharge path (10) in response to the low pulse of the clock signal (logic low pulse to “25b-d” results in “20” opening) is based on the second discharge path (10) receiving an inverted clock signal (logic low pulse to “25b-d” results in “20” opening, an inverted logic high pulse at “15”, and “10” conducting) from the inverter circuitry (20).
Marxer further teaches the inverter circuitry as a hardware implementation of inverter logic (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the logic circuit disclosed by the combo of Wied & Dust to incorporate inverter circuitry, as taught by Marxer, as a hardware implementation of the inverter logic, which reduces software complexity of the logic circuit and thus reduces the software engineering effort/cost to develop the electronic device.
Claims 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2013/0234510 A1; hereinafter “Naka”) in view of Dustert et al. (US 2023/0158896 A1; hereinafter “Dust”) and Marzahn (US 2006/0038463 A1; hereinafter “Marz”).
Regarding Claim 12, Naka discloses a method (¶ [34]: “method of controlling the discharge switch element SW2 by the fast discharge control device 60”) comprising the following.
Naka further discloses determining, by an active capacitor discharge tool (“fast discharge control device 60” + “discharge circuit 20”; Figs. 1-2, 6, 9) connected to a capacitor (“smoothing capacitor C”; Figs. 1-2, 6, 9), that a voltage (voltage “Vc” across “C”; Figs. 6, 9) associated with the capacitor is above a threshold (“predetermined target voltage”; ¶ [4, 39, 43, 56, 67]).
Naka further discloses discharging, by the active capacitor discharge tool (60 & 20), electrical charge (Fig. 3B shows reduction in voltage “Vc” over time; a reduction in electrical charge is inherent for a reduction in voltage of a capacitor with fixed capacitance) associated with the capacitor (C).
Naka further discloses determining, by the active capacitor discharge tool (using the “CPU 641” within “64A” or the “comparator CM2” within “64B”; Figs. 6, 9), that the voltage (voltage “Vc” across “C”; Figs. 6, 9) associated with the capacitor (C) is below the threshold (“predetermined target voltage”; ¶ [4, 39, 43, 56, 67]) based on discharging the capacitor using the at least two discharging paths (“C” is discharged through both the “fast discharge resistor R1” and “normal discharge resistor R2”; Figs. 1-2, 6, 9).
Naka does not disclose “discharging the capacitor using a first discharge path but not a second discharge path in response to receiving a high voltage pulse of a clock signal; and discharging the capacitor using the second discharge path but not the first discharge path in response to receiving a low voltage pulse of the clock signal”.
Though, as addressed supra, Nakamura discloses “discharging, by the active capacitor discharge tool, electrical charges associated with the capacitor”, Naka further does not disclose “by shorting a positive lead and a negative lead of the capacitor”.
Dust teaches discharging, by the active capacitor discharge tool (Fig. 2, including “discharge circuitry 205”), electrical charge associated with the capacitor (“DC link capacitor 140”, coupled to “205” via “step down power converter 150”; Fig. 2) based on the following.
Dust further teaches discharging the capacitor (140) using a first discharge path (¶ [36]: “first conduction path between rails 155, 160”; includes “resistance 405” and “switch 415”; Fig. 4) but not a second discharge path (¶ [36]: “second conduction path between rails 155, 160”; includes “resistance 410” and “switch 420”; Fig. 4) in response to receiving a high voltage pulse (when “DR1” is logic high state, the N-channel MOSFET “415” is configured to conduct/close the first discharge path; when “DR1” is logic high state, “DR2” is alternatively in the logic low state per ¶ [37]; when “DR2” is logic low state, “420” opens the second discharge path) of a clock signal (“discharge drive signal DR1”; Figs. 2, 4; ¶ [35]: “DR1 can be a pulse train that drives switch 310 into and out of conduction repeatedly”).
Dust further teaches discharging the capacitor (140) using the second discharge path (410 & 420) but not the first discharge path (405 & 415) in response to receiving a low voltage pulse (when “DR1” is logic low state, the N-channel MOSFET “415” is configured to open the first discharge path; when “DR1” is logic low state, “DR2” is alternatively in the logic high state per ¶ [37]; when “DR2” is logic high state, “420” conducts/closes the second discharge path) of the clock signal (DR1).
Dust further teaches to discharge through only one of the first/second discharge paths at a single time to reduce heating of the resistors in the discharge paths (¶ [38]). This reduces risk of damage from excessive heating (¶ [35]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the active capacitor discharge tool disclosed by Naka to incorporate a second discharge path operating alternatively to the first discharge path based on the clock signal state, as taught by Dust, to reduce risk of damage to the resistors in the discharge paths from excessive heating.
Marz teaches discharging by shorting (“additional first discharge switch PS”, also referred to as “safety switch”; Figs. 1-2, 4; ¶ [22]: “safety short circuit” applied when “less than 30% of the corresponding voltage in the charge state of the piezoelectric actuator”) a positive lead (labeled “+” terminal of “Cp”; ¶ [39]: “piezo-connection Cp+”) and a negative lead (labeled “-” terminal of “Cp” ; ¶ [39]: “piezo-connection Cp-”) of the charged element (“piezoelectric actuator CP”; Figs. 1-2, 4; ¶ [4]: “a virtually completely capacitive load”).
NOTE: Though it is not a capacitor, the piezoelectric actuator taught by Marz is still a charged element. One of ordinary skill in the art would understand that the circuits, signals, and control methodologies taught by Marz would work with any charged element (including a capacitor, battery, or piezoelectric actuator). This is evidenced by Marz ¶ [4], which refers to the charged element as “a virtually completely capacitive load”.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the active capacitor discharge tool, as taught by the combo of Naka & Dust, to incorporate the switch taught by Marz to short the positive lead and negative lead of the capacitor, to improve operating safety and accelerate the discharge process (Marz ¶ [21]).
Regarding Claim 16, the combo of Naka, Dust, & Marz teaches the method of claim 12.
The combo of Naka, Dust, & Marz teaches shorting (from Marz ¶ [22]: “safety short circuit” applied when “less than 30% of the corresponding voltage in the charge state”) the positive lead (Naka: positive terminal of “C” / Marz equivalent: “Cp+”) and the negative lead (Naka: negative terminal of “C” / Marz equivalent: “Cp-”) of the capacitor (Naka: “C” / Marz equivalent: “Cp”).
The combo of Naka, Marxer, and Marz (as set forth prior) does not explicitly teach that this “discharges the capacitor to a ground voltage level associated with the active capacitor discharge tool”. However, additional teachings from Marz are considered infra.
Marz further teaches that this discharges the charged element (CP) to a ground voltage level (¶ [13]: “potential prevailing on the first piezo-terminal (“high-side”) changed toward the second control potential (“ground”) by means of the first discharge path”; “GND” labelled in Figs. 1-2, 4; voltage graph in Fig. 3) associated with the active discharge tool (circuits, signals, and control methodologies of the combination of “S1”, “S2”, and “ST”; Figs. 1-2, 4).
Though it is not a capacitor, the piezoelectric actuator taught by Marz is still a charged element. One of ordinary skill in the art would understand that the circuits, signals, and control methodologies taught by Marz would work with any charged element (including a capacitor, battery, or piezoelectric actuator). This is evidenced by Marz ¶ [4], which refers to the charged element as “a virtually completely capacitive load”.
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the capacitor discharge tool disclosed by the combo of Naka, Dust, and Marz to discharge the capacitor to a ground voltage level, as further taught by Marz, to improve operating safety and accelerate the discharge process (Marz ¶ [21]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2013/0234510 A1; hereinafter “Naka”) in view of Dustert et al. (US 2023/0158896 A1; hereinafter “Dust”), Marzahn (US 2006/0038463 A1; hereinafter “Marz”), Marxer (US 2022/0037992 A1), and Ultra Librarian (Relays vs. Transistors: Which is the Correct Choice, 2021-02-09, Ultra Librarian).
Regarding Claim 13, the combo of Naka, Dust, & Marz teaches the method of claim 12.
Naka discloses turning on (via the “discharge command”; Figs. 1-2, 6, 9; ¶ [37]) the active capacitor discharge tool (“fast discharge control device 60” + “discharge circuit 20”; Figs. 1-2, 6, 9) to do the following.
Naka further discloses to actively determine that the voltage (voltage “Vc” across “C”; Figs. 6, 9) associated with the capacitor (C) is above the threshold (“predetermined target voltage”; ¶ [4, 39, 43, 56, 67]) based on using active comparator circuitry (“comparator CM2” within “64B”; Fig. 9).
The combo of Naka, Dust, & Marz (as set forth prior) teaches to actively discharge the electrical charges (Naka: Fig. 3B shows reduction in voltage “Vc” over time; a reduction in electrical charge is inherent for a reduction in voltage of a capacitor with fixed capacitance) associated with the capacitor (Naka: “C”) by electrically connecting the capacitor (Naka: “C” / Dust equivalent: “140”) to ground (Naka’s “C” connects to its ground reference through “R1” when “SW2” is closed; from Dust: “140” connects to its ground reference through “150” & “405” when “415” is closed or through “150” & “410” when “420” is closed; Figs. 2, 4; though Dust’s capacitor connects to ground through the converter “150”, this aligns with the instant application’s Fig. 3 wherein the capacitor connects to ground through “304”).
The combo of Naka, Dust, & Marz further teaches this is performed based on alternating between at least the first discharge path (from Dust: “405” & “415”) and the second discharge path (from Dust: “410” & “420”) using active switching components (from Dust: “415” & “420”).
The combo of Naka, Dust, & Marz further teaches to actively discharge the electrical charges (Naka: Fig. 3B shows reduction in voltage “Vc” over time; a reduction in electrical charge is inherent for a reduction in voltage of a capacitor with fixed capacitance) associated with the capacitor (Naka: “C”) by shorting (from Marz ¶ [22]: “safety short circuit” applied when “less than 30% of the corresponding voltage in the charge state”) the positive lead (Naka: positive terminal of “C” / Marz equivalent: “Cp+”) and the negative lead (Naka: negative terminal of “C” / Marz equivalent: “Cp-”) of the capacitor (Naka: “C” / Marz equivalent: “Cp”) using an active switch (from Marz: “additional first discharge switch PS”, also referred to as “safety switch”).
The combo of Naka, Dust, & Marz further discloses the shorting of the leads (via the switch “PS”, incorporated from Marz) occurs after the capacitor (Naka: “C” / Marz equivalent: “Cp”) has been discharged to equal to or below the threshold voltage (Naka: “predetermined target voltage”; Marz equivalent: ¶ [22]: “less than 30% of the corresponding voltage”) based on alternating between at least the first discharge path and the second discharge path (alternating between two paths incorporated from Dust).
As addressed supra, the combo of Naka, Dust, & Marz teaches “alternating between at least the first discharge path and the second discharge path using active components. However, Naka does not disclose using “active inverter circuitry”. Though Dust teaches the operation of alternating between the two discharge paths, Dust does not provide details as to the hardware implementation to provide the command signals to the two discharge paths. However, it is well-known in the art how to provide an inverted command signal to a second discharge path.
As addressed supra, the combo of Naka, Dust, & Marz teaches to “actively discharge the electrical charges associated with the capacitor by shorting the positive lead and the negative lead of the capacitor” using an active switch. However, the combo of Naka, Dust, & Marz further does not disclose “using an active relay switch”.
Marxer teaches actively discharge the electrical charges associated with the capacitor (4) by electrically connecting the capacitor (4) to ground based on alternating between at least the first discharge path (20) and the second discharge path (10) using active switching components (“14” & “24b-d”) and active inverter circuitry (“20” will invert the signal logic from inputs “25b-d” to the output at “15”; Fig. 2).
Marxer further teaches the active inverter circuitry as a hardware implementation of inverter logic (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the method disclosed by the combo of Naka, Dust, & Marz to incorporate active inverter circuitry, as taught by Marxer, as a hardware implementation of the inverter logic, which reduces software complexity of the logic circuit and thus reduces the software engineering effort/cost to develop the active capacitor discharge tool.
Ultra Librarian teaches the applications and advantages of an active relay switch (“relay”; images shown on pages 1-2) versus other types of switches (“transistors”). Ultra Librarian teaches that relay switches provide increased isolation of high voltages, which improves the safety to nearby users (page 3, paragraph “Isolation”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the active switch taught by the combo of Naka, Dust, Marz, & Marxer to be an active relay switch, as taught by Ultra Librarian, to improve safety for nearby users.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2013/0234510 A1; hereinafter “Naka”) in view of Dustert et al. (US 2023/0158896 A1; hereinafter “Dust”), Marzahn (US 2006/0038463 A1; hereinafter “Marz”), and Lifschits et al. (US 2021/02023220 A1; hereinafter “Lif”).
Regarding Claim 15, the combo of Naka, Dust, & Marz teaches the method of claim 12.
Naka further discloses the voltage (voltage “Vc” across “C”; Figs. 6, 9) associated with the capacitor (C) is determined based on sensing a voltage of an internal node (“CM2” senses the voltages at nodes “Vref” and “Vch”; Fig. 9) of the active capacitor discharge tool (60 & 20).
Naka does not disclose “the threshold corresponds to a sufficiently discharged voltage for an operator associated with the capacitor”.
Lif teaches the threshold (“threshold” per ¶ [45, 54-55, 62, 69, 88, 106-107]) corresponds to a sufficiently discharged voltage (¶ [55]: “a 30 volt safety threshold”) for an operator (“safety workers per ¶ [54]; “maintenance workers” per ¶ [55]) associated with the capacitor (“capacitor C” within “power system 100”; Figs. 1A-1H, 2-11).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the method and threshold disclosed by the combo of Naka, Dust, & Marz for the threshold to correspond to a safe voltage level, as taught by Lif, to protect workers from exposure to unsafe voltage levels (Lif ¶ [54-55]).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2013/0234510 A1; hereinafter “Naka”) in view of Dustert et al. (US 2023/0158896 A1; hereinafter “Dust”), Marzahn (US `2006/0038463 A1; hereinafter “Marz”), and Ultra Librarian (Relays vs. Transistors: Which is the Correct Choice, 2021-02-09, Ultra Librarian).
Regarding Claim 23, the combo of Naka, Dust, & Marz teaches the method of claim 12.
The combo of Naka, Dust, & Marz teaches shorting (incorporated from Marz ¶ [22]: “safety short circuit” applied when “less than 30% of the corresponding voltage in the charge state”) the positive lead (Naka: positive terminal of “C” / Marz equivalent: “Cp+”) and the negative lead (Naka: negative terminal of “C” / Marz equivalent: “Cp-”) of the capacitor (Naka: “C” / Marz equivalent: “Cp”)
The combo of Naka, Dust, & Marz teaches switching an active switch (incorporated from Marz: “additional first discharge switch PS”, also referred to as “safety switch”) based on a control signal (Marz: “control signals s1-3” from “control unit ST” are used to control the “safety switch PS”; Figs. 1-2, 4) corresponding to the threshold voltage (Marz ¶ [22]: “safety short circuit” applied when “the piezovoltage is already less than 30% of the corresponding charge state of the piezoelectric actuator”).
Though, as discussed supra, the combo of Naka, Dust, & Marz teaches an active switch, it does not teach “an active relay switch”.
Ultra Librarian teaches the applications and advantages of an active relay switch (“relay”; images shown on pages 1-2) versus other types of switches (“transistors”). Ultra Librarian teaches that relay switches provide increased isolation of high voltages, which improves the safety to nearby users (page 3, paragraph “Isolation”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the active switch disclosed by the combo of Naka, Dust, & Marz to be an active relay switch, as taught by Ultra Librarian, to improve safety for nearby users.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2013/0234510 A1; hereinafter “Naka”) in view of Marzahn (US 2006/0038463 A1; hereinafter “Marz”) and Dustert et al. (US 2023/0158896 A1; hereinafter “Dust”).
Regarding Claim 17, Naka discloses a capacitor discharge tool (“fast discharge control device 60” & “discharge circuit 20”; Figs. 1-2, 6, 9), comprising the following.
Naka further discloses a timer circuit (“variable duty generation circuit 64”; Figs. 1-2, 6, 9; ¶ [38]) configured to provide a clock signal ([38]: “64 generates an on/off signal (pulse signal)”).
Naka further discloses a voltage comparator (“comparator CM2” within “64B”; Fig. 9) configured to provide a high voltage indicator signal (“on/off signal” from “64”; Figs. 1-2, 6, 9; ¶ [38]) in response to determining that a voltage (voltage “Vc” across “C”; Figs. 6, 9) associated with a capacitor (“smoothing capacitor C”; Figs. 1-2, 6, 9) is higher than a threshold (“predetermined target voltage”; ¶ [4, 39, 43, 56, 67]).
Naka further discloses a first discharge path (combo of “fast discharge resistor R1” and “discharge switch element SW2”; Figs. 1-2, 6, 9) configured to close to enable the capacitor (C) to discharge (“C” is connected to ground through “R1” and on-state “SW2”) through the first discharge path (R1 & SW2).
Naka further discloses this occurs in response to the voltage comparator (“CM2” within “64B”) providing the high voltage indicator signal (“on/off signal” is output from “64” to turn on/off “switch element SW2”; Figs. 1-2, 6, 9).
Naka further discloses this occurs in response to the timer circuit (64) providing a high pulse (on-state commands “SW2” to close, resulting in discharge current conduction through “R1” + SW2”; Figs. 7A-7C; ¶ [38]) of the clock signal (“on/off signal” from “60” to “SW2”).
Naka further discloses the first discharge path (R1 & SW2) is further configured to open to disable the capacitor (C) from discharging through the first discharge path (R1 & SW2) in response to the timer circuit (64) providing a low pulse (off-state commands “SW2” to open, blocking the discharge current through “R1” & “SW2” Figs. 7A-7C; ¶ [38]) of the clock signal (“on/off signal” from “60” to “SW2”).
Naka does not disclose the voltage comparator is further configured to “provide a sufficiently discharged voltage indicator signal in response to determining that the voltage associated with the capacitor is equal to or below the threshold”.
Naka further does not disclose “a second discharge path configured to: close to enable the capacitor to discharge through the second discharge path in response to: the voltage comparator providing the high voltage indicator signal; and the timer circuit providing the low pulse of the clock signal; and open to disable the capacitor from discharging through the second discharge path in response to the timer circuit providing the high pulse of the clock signal”.
Marz teaches to provide a sufficiently discharged voltage indicator signal (“control signals s1-3” from “control unit ST” are used to control the “safety switch PS”; Figs. 1-2, 4) in response to determining that the voltage (¶ [22]: “piezovoltage”) associated with the charged element (“piezoelectric actuator CP”; Figs. 1-2, 4; ¶ [4]: “a virtually completely capacitive load”) is below the threshold (¶ [22]: “safety short circuit” applied when “the piezovoltage is already less than 30% of the corresponding charge state of the piezoelectric actuator”).
Though it is not a capacitor, the piezoelectric actuator taught by Marz is still a charged element. One of ordinary skill in the art would understand that the circuits, signals, and control methodologies taught by Marz would work with any charged element (including a capacitor, battery, or piezoelectric actuator). This is evidenced by Marz ¶ [4] which refers to the charged element as “a virtually completely capacitive load”.
It would have been obvious to one of ordinary skill in the art to modify the voltage comparator disclosed by Naka to incorporate a provision of a sufficiently discharged voltage indicator signal, as taught by Marz, based on the voltage of the capacitor disclosed by Naka, to improve operating safety and accelerate the discharge process (Marz ¶ [21]).
Dust teaches a second discharge path (¶ [36]: “second conduction path between rails 155, 160”; includes “resistance 410” and “switch 420”; Fig. 4) configured to: close to enable the capacitor (“DC link capacitor 140”, coupled to “205” via “step down power converter 150”; Fig. 2) to discharge through the second discharge path (410 & 420).
Dust further teaches this occurs in response to: the voltage comparator (145) providing the high voltage indicator signal (same as clock signal: “DR1”).
Dust further teaches this occurs in response to the timer circuit (145) providing the low pulse of the clock signal (when “DR1” is logic low state, “DR2” is alternatively in the logic high state per ¶ [37]; when “DR2” is logic high state, “420” conducts/closes the second discharge path).
Dust further teaches the second discharge path (410 & 420) is further configured to open to disable the capacitor (140) from discharging through the second discharge path (410 & 420) in response to the timer circuit (145) providing the high pulse of the clock signal (when “DR1” is logic high state, “DR2” is alternatively in the logic low state per ¶ [37]; when “DR2” is logic low state, “420” opens the second discharge path).
Dust further teaches to discharge through only one of the first/second discharge paths at a single time to reduce heating of the resistors in the discharge paths (¶ [38]). This reduces risk of damage from excessive heating (¶ [35]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the capacitor discharge tool disclosed by the combo of Naka & Marz to incorporate a second discharge path operating alternatively to the first discharge path based on the clock signal state, as taught by Dust, to reduce risk of damage to the resistors in the discharge paths from excessive heating.
Regarding Claim 18, the combo of Naka, Marz, & Dust teaches the capacitor discharge tool of claim 17.
Naka further discloses the first discharge path (R1 & SW2) comprises a first switch (“discharge switch element SW2”; Figs. 1-2, 6, 9).
Naka further discloses the first switch (SW2) is configured to close in response to the high pulse of the clock signal (on-state commands “SW2” to close, resulting in discharge current conduction through “R1” + SW2”; Figs. 7A-7C; ¶ [38]) and open in response to the low pulse of the clock signal (off-state commands “SW2” to open, blocking the discharge current through “R1” & “SW2” Figs. 7A-7C; ¶ [38]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2013/0234510 A1; hereinafter “Naka”) in view of Marzahn (US 2006/0038463 A1; hereinafter “Marz”), Dustert et al. (US 2023/0158896 A1; hereinafter “Dust”), and Marxer (US 2022/0037992 A1).
Regarding Claim 19, the combo of Naka, Marz, & Dust teaches the capacitor discharge tool of claim 18.
The combo of Naka, Marz, & Dust (as set forth prior) teaches the second discharge path (incorporated from Dust: “410” & “420”) comprises a second switch (Dust: “420”).
The combo of Naka, Marz, & Dust further teaches the second switch (Dust: “420”) is configured to close in response to the low pulse of the clock signal (Dust: when “DR1” is logic low state, “DR2” is alternatively in the logic high state per ¶ [37]; when “DR2” is logic high state, “420” conducts/closes the second discharge path) and open in response to the high pulse of the clock signal (Dust: when “DR1” is logic high state, “DR2” is alternatively in the logic low state per ¶ [37]; when “DR2” is logic low state, “420” opens the second discharge path).
Naka does not disclose the second discharge path further comprises “inverter circuitry coupled to a gate of the second switch”.
Though Dust teaches the operation of alternating between the two discharge paths, Dust does not provide details as to the hardware implementation to provide the command signals to the two switches. However, it is well-known in the art how to provide an inverted command signal to a second switch.
Marxer teaches the second discharge path (“10”, switched on/off by “14”, with additional control circuitry including “20”; Fig. 2) comprises a second switch (“first switching element 14”; Fig. 2) and inverter circuitry (any of “24b-d” will invert the logic from the signals at inputs “25b-d” to the output at “first control connection 15”; Fig. 2) coupled to a gate (“first control connection 15”) of the second switch (14).
Marxer further teaches the second switch (14) is configured to close in response to the low pulse of the control signal (analogous to a clock signal, per note 1-1, included infra; logic low signal at “25b” causes “24b” to open, causing increased voltage at “15”, causing “14” to conduct/close) and open in response to the high pulse of the control signal (logic high signal at “25b” causes “24b” to conduct/close, causing decreased voltage at “15”, causing “10” to open).
NOTE 19-1: Though Marxer’s control signal is not a clock signal as claimed, one of ordinary skill in the art understands that Marxer’s control signal is analogous to the clock signal of the prior set forth art. Each signal is used to control one or more switching transistors used to switch on/off discharge path(s) for a high voltage capacitor.
Marxer further teaches the inverter circuitry as a hardware implementation of inverter logic (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the capacitor discharge tool disclosed by the combo of Naka, Marz, & Dust to incorporate inverter circuitry, as taught by Marxer, as a hardware implementation of the inverter logic, which reduces software complexity of the logic circuit and thus reduces the software engineering effort/cost to develop the capacitor discharge tool.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2013/0234510 A1; hereinafter “Naka”) in view of Marzahn (US 2006/0038463 A1; hereinafter “Marz”), Dustert et al. (US 2023/0158896 A1; hereinafter “Dust”), and Macalanda (SLYY163: Fundamentals to automotive LED driver circuits, May 2019, Texas Instruments) (hereinafter “Mac”).
Regarding Claim 20, the combo of Naka, Marz, & Dust teaches the capacitor discharge tool of claim 17.
The combo of Naka, Marz, & Dust (as set forth prior) teaches the high voltage indicator signal (Naka: “on/off signal” output from “64”) and the sufficiently discharged voltage indicator signal (incorporated from Marzahn: “control signals s1-3” from “control unit ST” are used to control the “safety switch PS”; Figs. 1-2, 4).
Naka does not disclose “a discharge LED indicator configured to provide an indication of high capacitor voltage in response to receiving the high voltage indicator signal; and a sufficiently discharged LED indicator configured to provide an indication of sufficiently discharged capacitor voltage in response to receiving the sufficiently discharged voltage indicator signal”.
Mac teaches an LED indicator (“constant current LED drive”; Figure 5 depicts two possible embodiments) configured to provide an indication (“illumination” in one of the LED colors depicted in Figure 2) in response to receiving the input signal (input to the base or gate of the transistors in Figure 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the capacitor discharge tool disclosed by the combo of Naka, Marz, & Dust to incorporate the LED indicator circuits, as taught by Mac, to provide an illuminated status indication to the user and to optimize the efficiency of the visual indication circuitry (Mac page 2). As part of this incorporation, the high voltage indicator signal and the sufficiently discharged voltage indicator signal would each be input to LED indicator circuits as shown in the annotated Figure 5 of Mac, provided infra.
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The combo of Naka, Marz, Dust, & Mac teaches a discharge LED indicator (Mac: LED in left-side circuit of annotated Figure 5) configured to provide an indication of high capacitor voltage (Mac: colored light illuminated from LED) in response to receiving the high voltage indicator signal (per combo described supra: “on/off signal” from Naka’s “64” is input to the base of the transistor in the left-side circuit of annotated Figure 5).
The combo of Naka, Marz, Dust, & Mac teaches a sufficiently discharged LED indicator (Mac: LED in right-side circuit of annotated Figure 5) configured to provide an indication of sufficiently discharged capacitor voltage (Mac: colored light illuminated from LED) in response to receiving the sufficiently discharged voltage indicator signal (per combo described supra: “control signals s1-3” from Marz is/are input to the base of the transistor in the right-side circuit of annotated Figure 5).
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2013/0234510 A1; hereinafter “Naka”) in view of Marzahn (US 2006/0038463 A1; hereinafter “Marz”), Dustert et al. (US 2023/0158896 A1; hereinafter “Dust”), and Ultra Librarian (Relays vs. Transistors: Which is the Correct Choice, 2021-02-09, Ultra Librarian).
Regarding Claim 21, the combo of Naka, Marz, & Dust teaches the capacitor discharge tool of claim 17.
The combo of Naka, Marz, & Dust (as set forth prior) teaches the voltage comparator (Naka: “CM2” within “64B”) providing the sufficiently discharged voltage indicator signal (incorporated from Marz: “control signals s1-3” from “control unit ST” are used to control the “safety switch PS”; Figs. 1-2, 4).
Naka does not disclose “a relay switch configured to short a cathode and an anode of the capacitor in response” to the above condition. However, additional teachings from Marz are considered infra.
Marz further teaches a switch (“additional first discharge switch PS”, also referred to as “safety switch”; Figs. 1-2, 4) configured to short (¶ [22]: “safety short circuit” applied when “less than 30% of the corresponding voltage in the charge state of the piezoelectric actuator”) a cathode (labeled “+” terminal of “Cp”; ¶ [39]: “piezo-connection Cp+”) and an anode (labeled “-” terminal of “Cp” ; ¶ [39]: “piezo-connection Cp-”) of the charged element (“piezoelectric actuator CP”; Figs. 1-2, 4; ¶ [4]: “a virtually completely capacitive load”) in response to a signal (“control signals s1-3” from “control unit ST”; Figs. 1-2, 4).
Though it is not a capacitor, the piezoelectric actuator taught by Marz is still a charged element. One of ordinary skill in the art would understand that the circuits, signals, and control methodologies taught by Marz would work with any charged element (including a capacitor, battery, or piezoelectric actuator). This is evidenced by Marz ¶ [4], which refers to the charged element as “a virtually completely capacitive load”.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the capacitor discharge tool disclosed by the combo of Naka, Marz, & Dust to incorporate the switch taught by Marz to short the capacitor in response to the sufficiently discharged voltage indicator signal. This modification would have been obvious to improve operating safety and accelerating the discharge process (Marz ¶ [21]).
Though, as discussed supra, the combo of Naka, Marz, & Dust teaches a switch, it does not teach “a relay switch”.
Ultra Librarian teaches the applications and advantages of a relay switch (“relay”; images shown on pages 1-2) versus other types of switches (“transistors”). Ultra Librarian teaches that relay switches provide increased isolation of high voltages, which improves the safety to nearby users (page 3, paragraph “Isolation”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the switch disclosed by the combo of Naka, Marz, & Dust to be a relay switch, as taught by Ultra Librarian, to improve safety for nearby users.
Regarding Claim 22, the combo of Naka, Marz, Dust, & Ultra Librarian teaches the capacitor discharge tool of claim 21.
The combo of Naka, Marz, Dust, & Ultra Librarian teaches the cathode (Nak ¶ [48]: “positive electrode side of the smoothing capacitor C”) and the anode (Naka ¶ [28]: “C is connected … the negative electrode line”) of the capacitor (Naka: “C”), along with the capacitor discharge tool (Naka: “fast discharge control device 60”).
Naka does not disclose “shorting the cathode and the anode of the capacitor discharges the capacitor to a ground voltage level associated with the capacitor discharge tool”. However, additional teachings from Marz are considered infra.
Marz further teaches that shorting (¶ [22]: “safety short circuit”) the cathode (labeled “+” terminal of “Cp”; ¶ [39]: “piezo-connection Cp+”) and the anode (labeled “-” terminal of “Cp” ; ¶ [39]: “piezo-connection Cp-”) of the charged element (“piezoelectric actuator CP”; Figs. 1-2, 4; ¶ [4]: “a virtually completely capacitive load”) discharges the charged element (“CP”) to a ground voltage level (¶ [13]: “potential prevailing on the first piezo-terminal (“high-side”) changed toward the second control potential (“ground”) by means of the first discharge path”; “GND” labelled in Figs. 1-2, 4; voltage graph in Fig. 3) associated with the discharge tool (circuits, signals, and control methodologies of the combination of “S1”, “S2”, and “ST”; Figs. 1-2, 4)
Though it is not a capacitor, the piezoelectric actuator taught by Marz is still a charged element. One of ordinary skill in the art would understand that the discharge tool (circuits, signals, and control methodologies) taught by Marz would work with any charged element (including a capacitor, battery, or piezoelectric actuator). This is evidenced by Marz ¶ [4], which refers to the charged element as “a virtually completely capacitive load”.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the capacitor discharge tool disclosed by the combo of Naka, Marz, Dust, & Ultra Librarian to discharge the capacitor to a ground voltage level, as further taught by Marz, to improve operating safety and accelerate the discharge process (Marz ¶ [21]).
Conclusion
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/DANIEL P MCFARLAND/ Examiner, Art Unit 2859
/DREW A DUNN/ Supervisory Patent Examiner, Art Unit 2859