DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-15, in the reply filed on 11/25/24 is acknowledged.
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-16 are rejected under 35 U.S.C. 102a1 as being anticipated by Cadag (10079198).
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As to claim 1, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
1. a method of assembling a semiconductor package, comprising: providing a lead frame 85 having a plurality of die attach pads 43/74, wherein each die attach pad 43 has a top surface with a pre-installed layer of die attach material 71; adhering a semiconductor device to each die attach pad 43 using the pre-installed die attach material 71; attaching wire bonds 76from contacts on each semiconductor device to leads on the lead frame 85; and covering at least a portion of the semiconductor devices, die attach pads 43/74, die adhesive material, wire bonds 76, and leads 74 with a mold compound 84.
As to claim 2, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
2 the method of claim 1, wherein a cavity is etched into the top surface of each of the die attach pads 43/74 on the lead frame 85, and wherein the pre-installed layer of die attach material 71 is disposed within each of the cavities.
As to claim 3, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
3 The method of claim 2, wherein a top surface of the die attach material 71 is coplanar with the top surface of the die attach pad.
As to claim 4, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
4 The method of claim 2, wherein the top surfaces of the die attach pads 43/74 include a portion of the die attach material 71 surrounding the cavity.
As to claim 5, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
5 The method of claim 1, wherein the pre-installed layer of die attach material 71 is a die attach tape that has been cut to a size selected based upon the size of the semiconductor device.
As to claim 6, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
6 The method of claim 1, further comprising: activating the die attach material 71 using heat or UV energy prior to adhering the semiconductor devices.
As to claim 7, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
7 The method of claim 1, further comprising: removing a protective material from the lead frame 85 prior to adhering the semiconductor devices.
As to claim 8, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
8. A method for manufacturing a lead frame 85, comprising: providing a lead frame 85 material having a top surface and a bottom surface; etching the lead frame 85 material to create a lead frame 85 strip having a plurality of die attach pad regions and a plurality of conductive leads adjacent to each die attach pad region; etching the top surface of each die attach pad region to create a cavity; and depositing a die attach material 71 in the cavity of each die attach pad region, wherein a top surface of the die attach material 71 is coplanar with the top surface of the lead frame 85 material.
As to claim 9, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
9. The method of claim 8, wherein the die attach material 71 is a die attach film that is cut to fit within the cavity.
As to claim 10, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
10. The method of claim 8, wherein depositing the die attach material 71 in the cavity includes spraying the die attach material 71 into the cavity.
As to claim 11, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
11. The method of claim 8, wherein depositing the die attach material 71 in the cavity includes screen printing the die attach material 71 into the cavity.
As to claim 12, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
12. The method of claim 8, wherein the die attach material 71 is an ink residue printed into the cavity.
As to claim 13, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
13. The method of claim 8, wherein the die attach material 71 requires activation using heat or UV energy prior to adhering a semiconductor device to the die attach pad region.
As to claim 14, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
14. The method of claim 8, further comprising: applying a protective material to the lead frame 85 sheet, wherein the protective material is configured for removal prior to adhering semiconductor devices to the die attach pads 43/74.
As to claim 15, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
15. The method of claim 8, wherein depositing the die attach material 71 further comprises: depositing excess die attach material 71 on the top surface of each die attach pad, wherein the excess die attach material 71 forms a rim surrounding the cavity on each die attach pad.
As to claim 16, figure 4, col 6, lines 54-67, col 7, lines 1-35, Cadag discloses:
16. The method of claim 8, wherein an amount of die attach material 71 deposited in the cavity of each die attach pad is selected to prevent the die attach material 71 from overflowing the die attach pad when a semiconductor die is mounted on the die attach pad using the die attach material 71.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Rodriguez (10,109,563) discloses a leadframe.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to (Vikki) Hoa B. Trinh whose telephone number is (571) 272-1719 and email is vikki.trinh@uspto.gov. The Examiner can normally be reached from Monday-Friday, 7:00 AM - 3:30 PM Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the Examiner’s supervisor, Mr. Steven Gauthier, can be reached at (571) 270-0373. The office fax number is 571-273-8300.
To schedule an Examiner’s Interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice .
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Vikki Hoa Trinh /HOA B TRINH/Primary Examiner, Art Unit 2813
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