Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Pages 6-7, filed 03/23/2025, with respect to the rejection(s) of claim(s) 1-16 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made above.
DETAILED ACTION
This action is responsive to application No. 18642841 filed on 03/23/2025.
Information Disclosure Statement
The information disclosure statement filed on 07/28/2025 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 & 6 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Hata et al. (US 20120248592 A1)
Regarding claim 1, Hata et al. teach a method of assembling a semiconductor package, comprising: 8
providing a lead frame (fig. 10, element 30 [0090]) having a plurality of die attach pads (figs. 9A & 10, top surface of element 7 & element 23 [0091]),
wherein each die attach pad has a top surface (fig 9A, top surface of element 23) with a pre-installed layer [0091] of die attach material (fig. 9B, element 22 comprising 3, 5 & bottom and side surfaces of element 7 [0087] [0092]);
adhering a semiconductor device (fig. 11, element 12 [0061]) to each die attach pad using the pre-installed die attach material;
attaching wire bonds (fig. 12, element 15 [0093]) from contacts (fig. 12, element 13 [0093]) on each semiconductor device to leads (fig. 12, element 8 [0093]) on the lead frame; and
covering at least a portion of the semiconductor devices, die attach pads, die adhesive material, wire bonds, and leads with a mold compound (fig. 12, element 17 [0093]).
Regarding claim 6, Hata et al. teach a method of assembling a semiconductor package, further comprising:
activating the die attach material using heat or UV energy prior to adhering the semiconductor devices [0070].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 - 4 are rejected under 35 U.S.C. 103 as being unpatentable over Hata et al. (US 20120248592 A1) in view of Rodriguez et al. (US 20190043790 A1).
Regarding claim 2, Hata et al. teach a method of assembling a semiconductor package,
wherein a cavity (Fig. 9B, cavity containing 3, 5 & 7) is [formed in] the top surface of each of the die attach pads on the lead frame,
and wherein the pre-installed layer of die attach material is disposed within each of the cavities (figs. 9B & 10).
Hata et al. do not explicitly teach a method wherein the cavities are formed by etching.
However, Rodriguez et al. is a pertinent art which teaches forming a cavity (figs. 15-16, element 1506 [0048]) top surface (figs. 15 -16, top surface) of a die attach pad (fig. 15, element 1511 [0048]) of a lead frame (fig. 15, element 1501 [0048]) using etching (e.g. [0001] [0052]).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the method of assembling a semiconductor package of Hata et al. to utilize etching for forming the cavity as taught by Rodriguez et al. A person of ordinary skill in the art would have been motivated to employ Rodriguez’s etching process in Hata et al. since etching was a known technique for forming cavities in lead frames, and for any number of reasons such as design considerations, balancing manufacturing cost and time, and the like.
Regarding claim 3, Hata et al. teach a method of assembling a semiconductor package,
wherein a top surface of the die attach material is coplanar with the top surface of the die attach pad (fig. 9B).
Regarding claim 4, Hata et al. teach a method of assembling a semiconductor package,
wherein the top surfaces of the die attach pads include a portion of the die attach material surrounding the cavity (fig. 9B).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hata et al. (US 20120248592 A1) in view of Koduri et al. (US 20220208701 A1).
Regarding claim 5, Hata et al. do not explicitly teach a method of assembling a semiconductor package wherein the pre-installed layer of die attach material is a die attach tape that has been cut to a size selected based upon the size of the semiconductor device.
However, Koduri et al. is a pertinent art which teaches a die attach material is a die attach tape (figs. 23A, 23B, element 22 [0158]) that has been modified to a size [0158] selected based upon the size of the semiconductor device (figs. 24A, 24B, element 18 [0158]).
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing to cut the die attach tape to a desired size selected (through photolithography and etching) from the list of Koduri’s instead of one of the other methods listed such as screen-printing, inkjet printing, spray coating, micro dispensing, aerosol jet, etc.; if this leads to the anticipated success, in the instant case using a method that will provide an attachment material only in a desired area for bonding, it is likely the product not of innovation but of ordinary skill.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hata et al. (US 20120248592 A1) in view of Sakumoto et al. (US 5091251 A)
Regarding claim 7, Hata et al. do not explicitly teach a method of assembling a semiconductor package further comprising: removing a protective material from the lead frame prior to adhering the semiconductor devices.
However, Sakumoto et al. is a pertinent art which teaches removing a protective material from the lead frame prior to adhering the semiconductor device [column 9, Line 30 – 45]).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filling date of the claimed invention to modify the method of assembling a semiconductor package of Hata et al. by implementing the process of removing the protective film as taught by Sakumoto et al. A person of ordinary skill in the art would have been motivated to employ Sakumoto’s removing protective material process from the lead frame in Hata et al. prior to adhering the semiconductor devices in order establish electrical contact between semiconductor die and conductive lead and also to prevent damages to the bond pad site during etching process.
Claims 8, 13, 15 & 16 are rejected under 35 U.S.C. 103 as being unpatentable over Hata et al. (US 20120248592 A1) in view of Rodriguez (US 20190043790 A1) and further in view of Shinichi et al. (JP 2008124116 A).
Regarding claim 8, Hata et al. teach a method for manufacturing a lead frame, comprising:
providing a lead frame material (fig. 9B, element precursor to 4 [0087]) having a top surface (fig. 9B, top surface of element 4) and a bottom surface (fig. 9B, bottom surface of element 4);
a lead frame strip (fig. 10, element 30 [0090]) having a plurality of die attach pad regions (fig. 10, element 23 [0091]) and a plurality of conductive leads (fig. 10, elements 8, 9 & 10 [0084]) adjacent to each die attach pad region (fig. 10);
creating a cavity (fig. 9B, cavity containing 3, 5 & 7) in the top surface (fig. 9B, top surface of element 4) of each die attach pad region (figs. 9B and 10, element 23 [0091]);
and depositing a die attach material (fig. 9B, elements 3, 5 & 7 [0087]) in the cavity of each die attach pad region (figs. 10 & 11, element 23 [0087]),
wherein a top surface of the die attach material (fig. 9B, element 22 comprising 3, 5 & bottom and side surfaces of element 7 [0087] [0092]) is coplanar (fig. 9B) with the top surface (fig. 9B, top surface of 7) of the lead frame material.
Hata et al. do not explicitly teach a method for manufacturing a lead frame material is etched to create the lead frame strip and etching is used to form the cavity in the top surface of each die attach pad region.
However, Shinichi et al. is a pertinent art which teaches etching the lead frame material (fig. 2, specification discloses lead frame 200) to create a lead frame strip (fig. 2, specification discloses terminal portion 20 has a strip shape).
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filling date of the claimed invention to modify the method of assembling a semiconductor package to utilize etching as taught by Shinichi et al. and Rodriguez et al. A person of ordinary skill in the art would have been motivated to employ Shinichi’s and Rodriguez’s etching process in Hata et al. since etching is a known technique for altering the shape of metal used in lead frame, and for any number of reasons such as design considerations, balancing manufacturing cost and time, and the like.
Furthermore, Rodriguez et al. is another pertinent art which teaches etching the top surface (fig. 7, element 702 [0037]) of each die attach pad region (fig. 7, element 708 [0038]) to create cavity (fig. 7, element 704 [0037])
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filling date of the claimed invention to modify the method of assembling a semiconductor package to utilize etching as taught by Shinichi et al. and Rodriguez et al. A person of ordinary skill in the art would have been motivated to employ Shinichi’s and Rodriguez’s etching process in Hata et al. since etching is a known technique for altering the shape of metal used in die attach pad, and for any number of reasons such as design considerations, balancing manufacturing cost and time, and the like.
Regarding claim 13, Hata et al. teach a method for manufacturing a lead frame, wherein the die attach material requires activation using heat or UV energy [0070] prior to adhering a semiconductor device to the die attach pad region (fig. 11, element 22, [0092]).
Regarding claim 15, Hata et al. teach a method for manufacturing a lead frame, wherein depositing the die attach material further comprises:
depositing excess die attach material (fig. 9B, element 7 [outside of the cavity]) on the top surface of each die attach pad (fig. 9B),
wherein the excess die attach material forms a rim (fig. 9B, inner part of 7 outside of the cavity) surrounding the cavity on each die attach pad.
Regarding claim 16, Hata et al. teach a method for manufacturing a lead frame, wherein an amount of die attach material deposited in the cavity of each die attach pad is selected to prevent the die attach material from overflowing the die attach pad when a semiconductor die is mounted on the die attach pad using the die attach material (Hata et al. teaches an amount of die attach material (fig. 9B, elements 3 & 5 [0087]) deposited in the cavity of each die attach pad when a semiconductor die is mounted on the die attach pad using the die attach material (fig.11). It would have been obvious to one of the ordinary skill in the art before the effective filling date of the claimed invention not to have any die attach material overflowing with the motivation to prevent short circuiting with different element surrounding the pad).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hata et al. (US 20120248592 A1) in view of Rodriguez et al. (US 20190043790 A1) and further in view of Koduri et al. (US 20220208701 A1).
Regarding claim 9, Hata et al. do not explicitly teach a method for manufacturing a lead frame, wherein the die attach material is a die attach film that is cut to fit within the cavity.
However, Koduri et al. is a pertinent art which teaches a die attach material is a die attach tape (figs. 23A, 23B, element 22, [00158]) that has been [modified] to a size selected based upon the size of the semiconductor device (figs. 24A, 24B, element 18 [00158]).
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing to cut the die attach tape to a desired size selected (through photolithography and etching) from the list of Koduri’s instead of one of the other methods listed such as screen-printing, inkjet printing, spray coating, micro dispensing, aerosol jet, etc.; if this leads to the anticipated success, in the instant case using a method that will provide an attachment material only in a desired area for bonding, it is likely the product not of innovation but of ordinary skill.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Hata et al. (US 20120248592 A1) in view of Rodriguez et al. (US 20190043790 A1)further in view of Koduri et al. (US 20220208701 A1).
Regarding claim 10, Hata et al. as modified by Rodriguez et al. do not explicitly teach a method of manufacturing a lead frame, wherein depositing the die attach material in the cavity includes spraying the die attach material into the cavity.
However, Koduri et al. is a pertinent art which teaches depositing the die attach material includes spraying [00157] the die attach material in to the cavity (fig. 23 A, element 22 [0158]).
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant choosing spraying die attach material in to the cavity from the list of Koduri’s instead of one of the other methods listed such as screen-printing, inkjet printing, micro dispensing, aerosol jet, etc.; if this leads to the anticipated success, in the instant case using a method that will provide an attachment material only in a desired area for bonding, it is likely the product not of innovation but of ordinary skill.
Regarding claim 11, Hata et al. as modified by Rodriguez et al. do not explicitly teach a method for manufacturing a lead frame, wherein depositing the die attach material in the cavity includes screen printing the die attach material into the cavity.
However, Koduri et al. is a pertinent art which teaches the die attach material includes screen-printing [0158] the die attach material (fig. 23A, element 22 [0158]).
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing screen printing die attach material from the list of Koduri’s instead of one of the other methods listed such as inkjet printing, spray coating, micro dispensing, aerosol jet, etc.; if this leads to the anticipated success, in the instant case using a method that will provide an attachment material only in a desired area for bonding, it is likely the product not of innovation but of ordinary skill.
Regarding claim 12, Hata et al. as modified by Rodriguez et al. do not explicitly teach a method for manufacturing a lead frame, wherein the die attach material is an ink residue printed into the cavity.
However, Koduri et al. is a pertinent art which teaches the die attach material (fig. 23A, element 22, [0158]) is an ink residue printed ((fig. 23A, element 22, [0158]).
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing ink residue printed die attach material in to the cavity from the list of Koduri’s instead of one of the other methods listed such as screen printing, spray coating, micro dispensing, aerosol jet, etc.; if this leads to the anticipated success, in the instant case using a method that will provide an attachment material only in a desired area for bonding, it is likely the product not of innovation but of ordinary skill.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hata et al. (US 20120248592 A1) in view of Rodriguez et al. (US 20190043790 A1) and further in view of Sakumoto et al. (US 5091251 A).
Regarding claim 14, Hata et al. as modified by Rodriguez et al. do not explicitly teach a method for manufacturing a lead frame, further comprising: applying a protective material to the lead frame sheet, wherein the protective material is configured for removal prior to adhering semiconductor devices to the die attach pads.
However, Sakumoto et al. is a pertinent art which teaches applying a protective material (fig. 3, element 5 [col. 4, line 25-30]) to the lead frame (fig. 6 element 9b [col. 7, Line 50 – 65]), wherein the protective material is configured for removal prior to adhering the semiconductor devices (fig. 6 element 7, [col. 7, Line 50 – 65]) to the die attach pad (fig. 6 element 9a, [col. 7, Line 50 – 65], [col. 9, Line 10 – 55]).
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filling date of the claimed invention to modify the method of manufacturing a lead frame of Hata et al. implementing the process of removing the protective film as taught by Sakumoto et al. A person of ordinary skill in the art would have been motivated to employ Sakumoto’s removing protective material process from the lead frame of Hata et al. and Rodriguez et al. prior to adhering the semiconductor devices in order establish electrical contact between semiconductor die and conductive lead and also to prevent damages to the bond pad site during etching process.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIFUR RAHMAN whose telephone number is (571) 895-1534. The examiner can normally be reached on Monday-Friday, 9:00 AM - 5:00 PM (Eastern Time). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/ARIFUR RAHMAN/
Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813
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