DETAILED ACTION
A summary of this action:
Claims 1-25 have been presented for examination.
This action is Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Following Applicants amendments to the Claims, the objections of the Claims are Withdrawn.
Following Applicants arguments and amendments, and in light of the 2019 Patent Eligibility guidance, the 101 rejection of the Claims is Maintained.
Applicant’s Argument: Applicant argues that "claims directed to clear improvements to computer-related technology do not need the full eligibility analysis" since "their eligibility [is] self-evident based on the clear improvement." MPEP §2106.06(b) (citing Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1335-36, 118 USPQ2d 1684, 1689 (Fed. Cir. 2016)). Applicant’s arguments directed to 101 rejection are based on newly amended subject matter as Applicant amends the claim 13 limitation to include initialize, respective computer nodes of a distributed simulation system and to be simulated by the computing node. Accordingly, Applicant argues that the present claims are directed to parallel memory simulation models that improve the simulation nodes (e.g., graph processing cores) within a large graph processing system.
Examiner’s Response: Examiner respectfully disagrees because the present claims do not provide an analogous improvement to the computer to that of Enfish, specifically because the present claims do not improve the computer itself. The improvements of a self-referential table provide a specific benefit to the functioning of the computer, which is not the case in the claims of the instant application. The present claims are directed to initialize, respective computer nodes of a distributed simulation system and to be simulated by the computing node and to be simulated on a computing node, which are not an improvement to the computer itself. Rather, this is an improvement to the abstract idea associated with “Mental Processes.” MPEP 2106.05(a): “It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements...” Additionally, as discussed in 2106.05(a)(II) improvements to technology or technical fields, “an improvement in the abstract idea itself … is not an improvement in technology”. All arguments are addressed in the 101 rejection of the claims below.
Therefore, the 101 rejection of the claims is Maintained.
Following Applicants arguments and amendments, the 103 rejection of the claims is Maintained.
Applicant’s Argument: Applicant asserts that the ASAAD prior art reference fails to at least teach or suggest the features in Applicant’s claim limitations of wherein each computing node is to simulate execution of instructions on hardware logic of a graph processing system and to simulate a respective system memory portion of the graph processing system. Applicant amends claim 13 to include initialize, respective computer nodes of a distributed simulation system and to be simulated by the computing node and to be simulated on a computing node. Applicant’s arguments directed the 103 rejection are based on newly amended subject matter.
Examiner’s Response: Examiner respectfully disagrees with Applicant’s argument because the ASAAD prior art reference anticipates Applicant’s newly amended claim limitations of initialize, respective computer nodes of a distributed simulation system and to be simulated by the computing node and to be simulated on a computing node ASAAD ([0025-0027] “At least three modes of operation are supported. In the full virtual node mode, each of the processing cores will perform its own MPI (message passing interface) process independently. Each core is running four thread/process, and it uses a sixteenth of the memory (L2 and SD RAM) of the node, while coherence among the 64 processes within the node and across the nodes is maintained by MPI. In the full SMP, one MPI task with 64 threads ( 4 threads per core) is running, using the whole node memory capacity. The third mode called the mixed mode. Here 2,4,8, 16, and 32 processes are running 32,16,8,4, and 2 threads, respectively. Because of the torus' DMA feature, internode communications can overlap with computations running concurrently on the nodes. With respect to the Torus network, it is configured, in one embodiment, as a 5-dimensional design supporting hyper-cube communication and partitioning. A 4-Dimensional design allows a direct mapping of computational simulations of many physical phenomena to the Torus network.”) All arguments are addressed in the 103 rejection of the claims below.
Therefore, the 103 rejection is Maintained.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-25 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea of a mental process or mathematical concept without significantly more.
Step 1: Claims 1-12 and 20-23 are directed to a system, which is a system and is a statutory category invention. Claim 13-19 and 24-25 are directed to a non-transitory computer-readable media, which is a manufacture and is a statutory category invention. Therefore, claims 1-25 are directed to patent eligible categories of invention.
Claim 1
Step 2A, Prong 1: Independent claims 1, 13, 20, and 24 recite an abstract idea because the claims are derived from Mental Processes based on concepts performed in the human mind or with the aid of pencil and paper or in the alternative Mathematical Concepts using mathematical relationships, mathematical formulas or equations, or mathematical calculations.
Claims 1 recites plurality of computing nodes interconnected via a network implementing a Message Passing Interface (MPI) protocol, wherein each computing node is to simulate execution of instructions on hardware logic of a graph processing system and to simulate a respective system memory portion of the graph processing system, covers mental processes of assessing Example 1’s distributed simulation system and observing how a plurality of computing nodes interconnected via a Message Passing Interface protocol simulates hardware logic for each computing node as described in [00162] of the specification.
Claims 13 recites perform a functional simulation of a core of the graph processing system, the functional simulation comprising one or more memory operations, wherein the instructions are to simulate a memory operation, covers mental processes of assessing Example 17 including the non-transitory computer-readable media in executing instructions for one or more of the processors to perform a functional simulation as described in [00178] of the specification.
Claims 13, 20, and 24 similarly recite determining a target computing node of the system based on a system memory address indicated in the memory operation, covers mental processes of assessing Example 30 including the instructions associated with the non-transitory computer-readable media as described in [00191] of the specification.
Claims 20 and 24 similarly recite a plurality of computing nodes, each node comprising a system memory portion representing a subset of a system memory of a graph processing system, wherein the system memory portion is initialized, covers mental processes of assessing Example 26 and its plurality of computing nodes and the associated system memory portions as described in [00187] of the specification.
Thus, the claims recite the abstract idea of a mental process performed in the human mind, or with the aid of pencil and paper.
Dependent claims 2-12, 14-19, 21-23 and 25 further narrow the abstract ideas, identified in the independent claims. See analysis below.
Step 2A, Prong 2: The judicial exception is not integrated into a practical application. Claim 1 recites the additional limitation “network” as in dependent claim 9, “graph processing system” as in independent claims 1, 13, 20, and 24 and dependent claim 2, “memory, respective system memory, system memory, simulated system memory, or target system memory” as in independent claims 1, 20, 13, and 24 and dependent claim 2-8, 10, 11, 14-19, 21-23, and 25, “computing node(s) or target computing node(s)” as in independent claim 1, 13, 20 and 24, and dependent claims 2-12, 14, 16, 17, 21, 23, and 25,“memory controller” as in dependent claims 3 and 19, “distributed computing system,” as in dependent claim 4, “non-transitory computer-readable media” as in independent claims 13 and 24, “processors or one or more processors” as in independent claim 13 and 24, “computer-readable media” as in dependent claims 14-19, this limitation does not integrate the judicial exception into a practical application because it is nothing more than generally linking the use of the judicial exception to a particular technological environment. See MPEP 2106.05(h). Alternatively, this additional element merely uses a computer device as a tool to perform the abstract idea. (MPEP 2106.05(f)).
The limitation accessing an input file representing an initial state of the system memory, similarly recited in independent claims 13 , 20, and 24 and dependent claim 5 , only amounts to mere instructions to apply as it only recites the idea of a solution or outcome and fails to recite details of how a solution to a problem is accomplished MPEP 2106.05(f).
The limitation copying, to the computing node, portions of the input file corresponding to a respective system memory portion to be simulated by the computing node, similarly recited in independent claims 13 , 20, and 24 and dependent claim 5 , only amounts to mere instructions to apply as it only recites the idea of a solution or outcome and fails to recite details of how a solution to a problem is accomplished MPEP 2106.05(f).
The limitation copying the system memory data to the computing node based on a determination that the system memory portion corresponds to the computing node, similarly recited in dependent claims 6 , 14, and 21, only amounts to mere instructions to apply as it only recites the idea of a solution or outcome and fails to recite details of how a solution to a problem is accomplished MPEP 2106.05(f).
The limitation of “storing the system memory portion at the virtual address of the simulated system memory portion.,” similarly recited in claims 7, 15, and 22 are mere instructions to implement an abstract idea and can be viewed as merely use a computer as a tool to perform the abstract idea. (MPEP 2106.05(f)). Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a mental process) does not integrate a judicial exception into a practical application. (MPEP 2106.05(f)(2)). Thus, these limitations fail to provide a practical application of the abstract idea.
The limitation routing the memory operation to the target computing node, similarly recited in independent claims 20 and 24 and dependent claims 8 and 13, only amounts to mere instructions to apply as it only recites the idea of a solution or outcome and fails to recite details of how a solution to a problem is accomplished MPEP 2106.05(f).
The limitation initialize, on respective computing nodes of a distributed simulation system, a system memory portion representing a subset of a system memory of a graph processing system, wherein the instructions are to initialize the system memory portion, similarly recited in independent claims 13, 20, and 24, only amounts to mere instructions to apply as it only recites the idea of a solution or outcome and fails to recite details of how a solution to a problem is accomplished MPEP 2106.05(f).
The limitation executing memory operation instructions on cores of the graph processing system comprising, wherein execution of the memory operation instructions, similarly recited in independent claims 13 and 20, only amounts to mere instructions to apply as it only recites the idea of a solution or outcome and fails to recite details of how a solution to a problem is accomplished MPEP 2106.05(f).
Dependent claims 2-12, 14-19, 21-23 and 25 further narrow the abstract ideas, identified in the independent claims, and do not introduce further additional elements for consideration beyond those addressed above. The additional elements have been considered both individually and as an ordered combination in to determine whether they integrate the exception into a practical application. Therefore, the dependent claims do not integrate the claimed invention into a practical application.
Step 2B: The claims do not amount to significantly more. The judicial exception does not amount to significantly more. Claim 1 recites the additional limitation “network” as in dependent claim 9, “graph processing system” as in independent claims 1, 13, 20, and 24 and dependent claim 2, “memory, respective system memory, system memory, simulated system memory, or target system memory” as in independent claims 1, 20, 13, and 24 and dependent claim 2-8, 10, 11, 14-19, 21-23, and 25, “computing node(s) or target computing node(s)” as in independent claim 1, 13, 20 and 24, and dependent claims 2-12, 14, 16, 17, 21, 23, and 25,“memory controller” as in dependent claims 3 and 19, “distributed computing system,” as in dependent claim 4, “non-transitory computer-readable media” as in independent claims 13 and 24, “processors or one or more processors” as in independent claim 13 and 24, “computer-readable media” as in dependent claims 14-19, this limitation does not amount to significantly more because it is nothing more than generally linking the use of the judicial exception to a particular technological environment. See MPEP 2106.05(h). Alternatively, this additional element merely uses a computer device as a tool to perform the abstract idea. (MPEP 2106.05(f)).
The limitation accessing an input file representing an initial state of the system memory, similarly recited in independent claims 13 , 20, and 24 and dependent claim 5 , only amounts to mere instructions to apply as it only recites the idea of a solution or outcome and fails to recite details of how a solution to a problem is accomplished MPEP 2106.05(f) and does not amount to significantly more.
The limitation copying, to the computing node, portions of the input file corresponding to the respective system memory portion, similarly recited in independent claims 13 , 20, and 24 and dependent claim 5 , only amounts to mere instructions to apply as it only recites the idea of a solution or outcome and fails to recite details of how a solution to a problem is accomplished MPEP 2106.05(f) and does not amount to significantly more.
The limitation copying the system memory data to the computing node based on a determination that the system memory portion corresponds to the computing node, similarly recited in dependent claims 6 , 14, and 21, only amounts to mere instructions to apply as it only recites the idea of a solution or outcome and fails to recite details of how a solution to a problem is accomplished MPEP 2106.05(f) and does not amount to significantly more.
The limitation of “storing the system memory portion at the virtual address of the simulated system memory portion.,” similarly recited in claims 7, 15, and 22 are mere instructions to implement an abstract idea and can be viewed as merely use a computer as a tool to perform the abstract idea. (MPEP 2106.05(f)). Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a mental process) does not amount to significantly more. (MPEP 2106.05(f)(2)). Thus, these limitations fail to amount to significantly more.
The limitation routing the memory operation to the target computing node, similarly recited in independent claims 20 and 24 and dependent claims 8 and 13, only amounts to mere instructions to apply as it only recites the idea of a solution or outcome and fails to recite details of how a solution to a problem is accomplished MPEP 2106.05(f) and does not amount to significantly more.
The limitation initialize a system memory portion representing a subset of a system memory of a graph processing system, wherein the instructions are to initialize the system memory portion, similarly recited in independent claims 13, 20, and 24, only amounts to mere instructions to apply as it only recites the idea of a solution or outcome and fails to recite details of how a solution to a problem is accomplished MPEP 2106.05(f) and does not amount to significantly more.
The limitation executing memory operation instructions on cores of the graph processing system comprising, wherein execution of the memory operation instructions, similarly recited in independent claims 13 and 20, only amounts to mere instructions to apply as it only recites the idea of a solution or outcome and fails to recite details of how a solution to a problem is accomplished MPEP 2106.05(f) and does not amount to significantly more.
Dependent claims 2-12, 14-19, 21-23 and 25 further narrow the abstract ideas, identified in the independent claims, and do not introduce further additional elements for consideration beyond those addressed above. The additional elements have been considered both individually and as an ordered combination in to determine whether they amount to significantly more. Therefore, the dependent claims do not amount to significantly more.
Therefore, the claims as a whole does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements, when considered alone or in combination, do not amount to significantly more than the judicial exception.
As stated in Section I.B. of the December 16, 2014 101 Examination Guidelines, “[t]o be patent-eligible, a claim that is directed to a judicial exception must include additional features to ensure that the claim describes a process or product that applies the exception in a meaningful way, such that it is more than a drafting effort designed to monopolize the exception.”
The dependent claims include the same abstract ideas recited as recited in the independent claims, and merely incorporate additional details that narrow the abstract ideas and fail to add significantly more to the claims.
Dependent claim 2 recites “wherein each computing node is to simulate the hardware logic of a core of the graph processing system as a process and to simulate the system memory portion as a thread within the process,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 3 recites “wherein each computing node is to simulate a memory controller corresponding to its respective system memory portion,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 4 recites wherein the distributed computing system includes N computing nodes and is to simulate M bytes of data, and each computing node is to simulate a system memory portion equal to MIN,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 6 recites “wherein the input file comprises a plurality of lines, each line mapping a system memory address to corresponding system memory data, and each computing node is to copy the portions of the input file by: determining, for each line of the input file, a target system memory portion based on the system memory address,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 6 recites “determine whether the target system memory portion corresponds to the computing node,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 7 recites “determining a virtual address of the simulated system memory portion that corresponds to the system memory address,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 8 recites “determining a target computing node of the system based on a system memory address indicated in the memory operation,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 9 recites “wherein the target computing node is different from the computing node simulating the memory operation, and the memory operation is routed over the network via a packet formatted according to the MPI protocol,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 10 recites “determining a target system memory portion for the memory operation based on the system memory address indicated in the memory operation,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 10 recites “determining the target computing node based on a lookup table mapping each simulated system memory portion to a respective computing node of the system,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 11 recites “determining a target virtual address of the simulated system memory portion of the target computing node based on the system memory address of indicated in the memory operation,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 11 recites “performing the memory operation at the virtual address of the target computing node,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 12 recites “wherein the target computing node is different from the computing node simulating the memory operation, ,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 14 recites “determining, for each line of the input file, a target system memory portion based on the system memory address,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 14 recites “determine whether the target system memory portion corresponds to the computing node,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 15 recites “determining a virtual address of the simulated system memory portion that corresponds to the system memory address,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 16 recites “determining a target system memory portion for the memory operation based on the system memory address indicated in the memory operation,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 16 recites “determining the target computing node based on a lookup table mapping each simulated system memory portion to a respective computing node of the system,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 17 recites “determining a target virtual address of the simulated system memory portion of the target computing node based on the system memory address of indicated in the memory operation,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 17 recites “performing the memory operation at the virtual address of the target computing node,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 18 recites “wherein the instructions are to perform the functional simulation of the core by simulating hardware logic of the core as a process and simulating the system memory portion as a thread within the process,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 19 recites “wherein the instructions are further to simulate a memory controller with the system memory portion, the memory controller to process the memory operations,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 21 recites “wherein the input file comprises a plurality of lines, each line mapping a system memory address to corresponding system memory data, and each computing node is to copy the portions of the input file by determining, for each line of the input file, a target system memory portion based on the system memory address,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 21 recites “the target system memory portion corresponds to the computing node,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 22 recites “determining a virtual address of a simulated system memory portion that corresponds to the system memory address,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 23 recites “determining a target system memory portion for the memory operation based on the system memory address indicated in the memory operation,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 23 recites “determining the target computing node based on a lookup table mapping each simulated system memory portion to a respective computing node of the system,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 25 recites “determining a target system memory portion for the memory operation based on the system memory address indicated in the memory operation,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Dependent claim 25 recites “determining the target computing node based on a lookup table mapping each simulated system memory portion to a respective computing node of the system,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Processes.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20160011996 A1), herein, ASAAD.
Claim 1
Claims 1 is rejected because ASAAD anticipates plurality of computing nodes interconnected via a network implementing a Message Passing Interface (MPI) protocol ASAAD ([0388] “The parallel computing system includes a plurality of computing nodes (plurality of computing nodes). A computing node includes at least one processor and at least one memory device.”) See also ASAAD ([0025] “At least three modes of operation are supported. In the full virtual node mode, each of the processing cores will perform its own MPI (message passing interface) process independently. Each core is running four thread/process, and it uses a sixteenth of the memory (L2 and SD RAM) of the node, while coherence among the 64 processes (interconnected via a network implementing a Message Passing Interface (MPI) protocol)within the node and across the nodes (plurality of computing nodes) is maintained by MPI. In the full SMP, one MPI task with 64 threads (4 threads per core) is running, using the whole node memory capacity. The third mode called the mixed mode. Here 2,4,8, 16, and 32 processes are running 32,16,8,4, and 2 threads, respectively.”)
ASAAD also anticipates wherein each computing node is to simulate execution of instructions on hardware logic of a graph processing system and to simulate a respective system memory portion of the graph processing system ASAAD ([0403] FIG. 3-3-1 illustrates a flow chart for responding to commands issued by a processor when prefetched data may be available because of an operation of one or more different prefetch engines in one embodiment. A parallel computing system may include a plurality of computing nodes. A computing node may include, without limitation, at least one processor and/or at least one memory device. At step 21100, a processor (e.g., IBM® PowerPC®, A2 core 21200 in FIG. 3-3-2, etc.) in a computing node in the parallel computing system issues a command (each computing node is to simulate execution of instructions). A command includes, without limitation, an instruction (e.g., Load from and/or Store to a memory device, etc.) and/or a prefetching request (i.e., a request for prefetching of data or instruction(s) from a memory device ) (hardware logic of a graph processing system). A command also refers to a request, vice versa. A command and a request are interchangeably used in this disclosure. A command or request includes, without limitation, instruction codes, addresses, pointers, bits, flags, etc.”)
See also ASAAD ([1910] “In analyzing and enhancing performance of a data processing system (graph processing system) and the applications executing (simulate execution of instructions) within the data processing system, it is helpful to know which software modules (each computing node) within a data processing system (graph processing system) are using system resources. Effective management and enhancement of data processing systems requires knowing how and when various system resources are being used. Performance tools (hardware logic) are used to monitor and examine a data processing system to determine resource consumption as various software applications are executing within the data processing system. For example, a performance tool may identify the most frequently executed modules (each computing node) and instructions (simulate execution of instructions) in a data processing system, or may identify those modules (each computing node) which allocate the largest amount of memory or perform the most I/O requests (simulate a respective system memory portion of the graph processing system). Hardware performance tools (hardware logic) may be built into the system (graph processing system) or added at a later point in time.”)
Claim 2
Claim 2 is rejected because ASAAD anticipates claim 1. ASAAD also anticipates wherein each computing node is to simulate the hardware logic of a core of the graph processing system as a process and to simulate the system memory portion as a thread within the process ASAAD ([0078] and [Figure 4-2-9] “FIG. 4-2-9 is a conceptual diagram showing operation of a memory synchronization interface unit.”) See also ASAAD ([0577] “Each FPU 53 (each computing node) associated with a core 52 has a data path to the LI-data cache 55. Each core 52 is directly connected to a supplementary processing agglomeration 58 (core of the graph processing system), which includes a private prefetch unit (computing node). For convenience, this agglomeration 58 will be referred to herein as "UP"-meaning level 1 prefetch----or "prefetch unit;" but many additional functions (simulate the hardware logic of a core of the graph processing system) are lumped together in this so-called prefetch unit, such as write combining (hardware logic). These additional functions could be illustrated as separate modules, but as a matter of drawing and nomenclature convenience the additional functions (hardware logic) and the prefetch unit (computing node) will be illustrated herein as being part of the agglomeration (simulate the hardware logic of a core of the graph processing system) labeled "UP." This is a matter of drawing organization, not of substance. Some of the additional processing power of this LIP group is shown in FIGS. 4-2-9 and 4-2-15. The LIP group also accepts, decodes and dispatches all requests sent out by the core 52.”)
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ASAAD Figure 4-2-9 Reference
Claim 3
Claim 3 is rejected because ASAAD anticipates claim 1. ASAAD also anticipates wherein each computing node is to simulate a memory controller corresponding to its respective system memory portion ASAAD ([0578] “In this embodiment, the L2 Cache units (each computing node) provide the bulk of the memory system caching (corresponding to its respective system memory portion). Main memory may be accessed through two on-chip DDR-3 SDRAM memory controllers 78, each of which services eight L2 slices.”) See also ASAAD ([0851] “A functional unit (FU) 35120 (computing node) fetches these instructions from the instruction queue 35115, and runs these instructions. To run one or more of these instructions, the FU 35120 may retrieve data stored (corresponding to its respective system memory portion) in a cache memory 35125 or in a main memory (not shown) via a main memory controller 35130 (simulate a memory controller).”)
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ASAAD Figure 7-4-5 Reference
Claim 4
Claim 4 is rejected because ASAAD anticipates claim 1. ASAAD also anticipates wherein the distributed computing system includes N computing nodes and is to simulate M bytes of data, and each computing node is to simulate a system memory portion equal to M/N ASAAD ([0160]“ FIG. 5-1-13 depicts a flowchart showing implementation of byte alignment according to one embodiment.”) See also ASAAD ([0032] “FIG. 1-0 illustrates a hardware configuration of a basic node of this present massively parallel supercomputer architecture.”) See also ASAAD ([Figure 1-0] and [Figure 5-1-13].) Examiner’s Note: Figure 1-0 anticipates the claim limitation because the figure illustrates N computing nodes. Figure 5-1-16 anticipates the claim limitation because the figure illustrates M bytes of data where each computing node simulates a system memory portion equal to M/N or bytes over nodes.
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ASAAD Figure 5-1-13 Reference
Claim 5
Claim 5 is rejected because ASAAD anticipates claim 1. ASAAD also anticipates wherein each computing nodes is to initialize its respective simulated system memory portion by accessing an input file representing an initial state of the system memory ASAAD ([0558] “At step 3430, the MU 3220 looks at the flag bit (representing an initial state of the system memory) based on a memory location or address specified in the store instruction, validates the updated data if determined that the flag bit on the updated data is set, and sends the updated data to other processor cores or other computing nodes (copying, to the computing node, portions of the input file corresponding to the respective simulated system memory portion) that the MU does not belong to. In one embodiment, the MU 3220 monitors load instructions and store instructions issued by processor cores, e.g., by accessing an instruction queue (accessing an input file representing an initial state of the system memory).”)
Claim 6
Claim 6 is rejected because ASAAD anticipates claim 5. ASAD also anticipates wherein the input file comprises a plurality of lines, each line mapping a system memory address to corresponding system memory data, and each computing node is to copy the portions of the input file ASAAD ([0302] “A list describes an arbitrary sequence (i.e., a sequence not necessarily arranged in an increasing, consecutive order) of prior cache miss addresses (i.e., addresses that caused cache misses before). In one embodiment, address lists which are recorded from L1 (level one) cache misses and later loaded and used to drive the list prefetch engine may include, for example, 29-bit, 128-byte addresses (system memory address) identifying (line mapping) L2 (level-two) cache lines (a plurality of lines) in which an L1 cache miss occurred (to corresponding system memory data). Two additional bits (corresponding system memory data) are used to identify (line mapping), for example, the 64-byte (system memory address), L1 cache lines (plurality of lines) which were missed. In this embodiment, these 31 bits plus an unused bit compose the basic 4-byte record out of which these lists are composed (each line mapping a system memory address to corresponding system memory data). [0303] FIG. 3-1-1 illustrates a system diagram of a list prefetch engine 2100 in one embodiment.”) See also ASAAD ([0579] “To reduce main memory accesses, the L2 advantageously serves as the point of coherence for all processors within a nodechip. This function includes generating L1 invalidations when necessary. Because the L2 cache is inclusive of the L1s, it can remember which processors (each computing node) could possibly have a valid copy of every line (copy the portions of the input file), and can multicast selective invalidations to such processors.”)
ASAAD also anticipates determining, for each line of the input file, a target system memory portion based on the system memory address and determine whether the target system memory portion corresponds to the computing node ASAAD ([0305-0309] “In one embodiment, a directive called start_list (input file) causes a processor core (computing node) to issue a memory mapped command (e.g., input/output command) (target system memory portion) to the parallel computing system. The command may include, but not limited to: A pointer to a location (system memory address) of a list in a memory device. A maximum length of the list. An address range described in the list. The address range pertains to appropriate memory accesses. The number of a thread issuing the start_list directive. (For example, each thread can have its own list prefetch engine. Thus, the thread number can determine which list prefetch engine is being started (determining, for each line of the input file). Each cache miss may also come with a thread number so the parallel computing system (computing node) can tell which list prefetch engine is supposed to respond (determine whether the target system memory portion corresponds to the computing node).”)
ASAAD also anticipates copying the system memory data to the computing node based on a determination that the system memory portion corresponds to the computing node ASAAD ([1530] “Dynamic routing, where the proper routing path is determined at every node, is enabled by setting the 'dynamic routing' bit in the data packet header 67514 to 1. To improve performance on asymmetric tori, 'zone' routing can be used to force dynamic packets down certain dimensions before others… In one embodiment, there is one corresponding mask bit (based on a determination that the system memory portion corresponds to the computing node) for each hint bit. In another embodiment, there is half the number of mask bits as there are hint bits, but the mask bits are logically expanded so there is a one-to-one correlation between the mask bits and the hint bits (based on a determination that the system memory portion corresponds to the computing node). For example, in a five-dimensional torus (computing node) if the mask bits are set to 10100 (system memory data), where 1 represents the 'a' dimension, 0 represents the 'b' dimension, 1 represents the 'c' dimension, 0 represents the 'd' dimension, and O represents the 'e' dimension, the bits (system memory data) for each dimension are duplicated (copying the system memory data) so that 11 represents the 'a' dimension, 00 represents the 'b' dimension, 11 represents the 'c' dimension, 00 represents the 'd' dimension, and 00 represents the 'e' dimension. The duplication of bits (copying the system memory data) logically expands 10100 to 1100110000 so there are ten corresponding mask bits for each of the ten hint bits.”)
Claim 7
Claim 7 is rejected because ASAAD anticipates claim 6. ASAD also anticipates determining a virtual address of the simulated system memory portion that corresponds to the system memory address and storing the system memory portion at the virtual address of the simulated system memory portion ASAAD ([1877] “Thus each WakeUp WAC snoops all addressed stored to by the local processor. The unit also snoops all invalidate addresses given by the crossbar to the local processor. These invalidates and local stores are physical addresses. Thus software must translate the desired virtual address to a physical address to configure the WakeUp unit. The number of instructions taken for such address translation is typically much lower than the alternative of having the thread in a polling loop.”) See also ASAAD ([0502] “Page identification begins with the expansion of the effective address into a virtual address. The effective address is a 64-bit address calculated by a load, store, or cache management instruction, or as part of an instruction fetch. In one embodiment of a system employing the A2 processor, the virtual address is formed by prepending the effective address with a 1-bit 'guest space identifier', an 8-bit 'logical partition identifier', a 1-bit 'address space identifier' and a 14-bit'process identifier'. The resulting 88-bit value forms the virtual address, which is then compared to the virtual addresses contained in the TLB page table entries.”) See also ASAAD ([Fig. 2-1-2].)
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Claim 8
Claim 8 is rejected because ASAAD anticipates claim 1. ASAD also anticipates wherein each computing node is to simulate a memory operation performed by the simulated hardware logic by: determining a target computing node of the system based on a system memory address indicated in the memory operation; and routing the memory operation to the target computing node ASAAD ([0286] “FIG. 1-0 depicts a schematic of a single network compute node 50 in a parallel computing system having a plurality of like nodes each node employing a Messaging Unit 100 according to one embodiment (each computing node is to simulate a memory operation). The computing node 50 for example may be one node in a parallel computing system architecture such as a BluGene®/Q massively parallel computing system comprising 1024 compute nodes 50(1), ... 50(n ), each node including multiple processor cores and each node connectable to a network such as a torus network, or a collective.”) See also ASAAD ([Figure 1-0].) See also ASAAD ([0388] “FIG. 3-2-1 illustrates a flow chart illustrating method steps performed by a stream prefetch engine (performed by the simulated hardware logic) (e.g., a stream prefetch engine 20200 in FIG. 3-2-2) in a parallel computing system in one embodiment. A stream prefetch engine refers (determining a target computing node of the system) to a hardware or software module for performing fetching of data (performed by the simulated hardware logic) in a plurality of streams before the data is needed. The parallel computing system includes a plurality of computing nodes. A computing node (target computing node) includes at least one processor and at least one memory device. At step 20100, a processor issues a load request (e.g., a load instruction) (memory operation). The stream prefetch engine 20200 receives the issued load request. At step 20105, the stream prefetch engine searches the PFD 20240 (indicated in the memory operation) to find a cache line address corresponding to a first memory address (based on a system memory address) in the issued load request. In one embodiment, the PFD 20240 stores a plurality of memory addresses whose data have been prefetched (routing the memory operation to the target computing node), or requested to be prefetched, by the stream prefetch engine 20200. In this embodiment, the stream prefetch engine 20200 evaluates whether the first address (memory address) in the issued load request (memory operation) is present and valid in the PFD 20240. To determine whether a memory address in the PFD 20240 is valid or not (determines a target computing node of the system based on the address), the stream prefetch engine 20200 may check an address valid bit of that memory address.”)
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Claim 9
Claim 9 is rejected because ASAAD anticipates claim 8. ASAD also anticipates wherein the target computing node is different from the computing node simulating the memory operation ASAAD ([0388] “FIG. 3-2-1 illustrates a flow chart illustrating method steps performed by a stream prefetch engine (e.g., a stream prefetch engine 20200 in FIG. 3-2-2) in a parallel computing system (different from the computing node) in one embodiment. A stream prefetch engine refers to a hardware or software module for performing fetching of data (simulating the memory operation) in a plurality of streams before the data is needed. The parallel computing system includes a plurality of computing nodes. A computing node (target computing node) includes at least one processor and at least one memory device. At step 20100, a processor issues a load request (e.g., a load instruction) (simulating the memory operation). The stream prefetch engine 20200 (different from the computing node) receives the issued load request.”) See also ASAAD ([Figure 5-4-1A].)
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ASAAD also anticipates the memory operation is routed over the network via a packet formatted according to the MPI protocol ASAAD ([2048] “The torus network supports both point to point operations and collective communication operations. The collective communication operations supported are barrier, broadcast, reduce and all reduce. For example, a broadcast put descriptor will place the broadcast payload on all the nodes in the class route (a predetermined route set up for a group of nodes in the MPI communicator) (according to the MPI protocol). Similarly there are collective put reduce and broadcast operations. A remote get (with a reduce put payload can be broadcast) to all the nodes from where data will be reduced via the put descriptor.”) See also ASAAD ([2087] “To embed a collective network over the 5-D torus, a new collective DATA packet type is supported by the network logic. The collective DATA packet format shown in FIG. 6 is similar in structure to the point-to-point DATA packet format shown in FIG. 6-8-7. The packet type x"55" in byte 0 of the point-to-point DATA packet format (via a packet formatted) is replaced (memory operation) by a new collective DATA packet type x"5A". The point-to-point routing bits in byte 1, 2 and 3 (routed over the network) are replaced by collective operation code, collective word length and collective class route, respectively. The collective operation code field indicates one of the supported collective operations, such as binary AND, OR, XOR, unsigned integer ADD, MIN, MAX, signed integer ADD, MIN, MAX, as well as floating point ADD, MIN and MAX.”) See also ASAAD ([Figure 6-8-7] and [Figure 6-8-6].)
Claim 10
Claim 10 is rejected because ASAAD anticipates claim 8. ASAAD also anticipates determining a target system memory portion for the memory operation based on the system memory address indicated in the memory operation and determining the target computing node based on a lookup table mapping each simulated system memory portion to a respective computing node of the system ASAAD ([2195] “Each column within history table 94500 represents a type of data collected (memory operation) from a core or a logic block (target computing node) that is being monitored (determining a target system memory portion). Within history table 94500, 'Block name' column (system memory address) stores (memory operation) the identification data (indicated in the memory operation) related to the monitored item (target system memory portion) of interest such as a core (target computing node), a circuit or a logic block. 'Voltage' and 'Frequency' columns (system memory addresses) store (memory operation) values collected at runtime that describe the supplied voltage (VDD) and clock frequency of the measured item, respectively. 'Time stamp' column (system memory address) stores (memory operation) values of the time and date of when the time stamp value was measured. 'Switch factors' column stores probability values, which are measured from corresponding hardware counters (target computing nodes) of how often the bits switch (determine a target system memory portion) in the measured item. 'Aging sensor reading' column (system memory address) stores (memory operation) values obtained from aging sensors and/or age-analyzers (see FIG. 7-3-4), which may be a number of trips made by the ring oscillator (a respective computing node of the system) in a fixed period of time. This number may be translated (mapping) to VT using a lookup table (based on a lookup table) provided by simulations (simulated system memory portion) of the ring oscillator at the design stage. 'Thermal sensor reading' column stores values obtained from thermal sensors.
Claim 11
Claim 11 is rejected because ASAAD anticipates claim 8. ASAAD also anticipates determining a target virtual address of the simulated system memory portion of the target computing node based on the system memory address of indicated in the memory operation and performing the memory operation at the virtual address of the target computing node ASAAD ([1877] “Thus each WakeUp WAC (target computing node) snoops all addressed (determining a target virtual address) stored (simulated system memory portion) to by the local processor (target computing node). The unit also snoops (target computing node process the memory operation) all invalidate addresses given by the crossbar to the local processor. These invalidates and local stores are physical addresses. Thus software must translate (performing the memory operation) the desired virtual address (at the target virtual address) to a physical address (system memory address) to configure (in the memory operation) the WakeUp unit (target computing node). The number of instructions taken for such address translation is typically much lower than the alternative of having the thread in a polling loop.”) See also ASAAD ([0502] “Page identification begins with the expansion of the effective address into a virtual address. The effective address is a 64-bit address calculated by a load, store, or cache management instruction, or as part of an instruction fetch. In one embodiment of a system employing the A2 processor, the virtual address is formed by prepending the effective address with a 1-bit 'guest space identifier', an 8-bit 'logical partition identifier', a 1-bit 'address space identifier' and a 14-bit'process identifier'. The resulting 88-bit value forms the virtual address, which is then compared to the virtual addresses contained in the TLB page table entries.”) See also ASAAD ([Fig. 2-1-2].)
Claim 12
Claim 12 is rejected because ASAAD anticipates claim 11. ASAAD also anticipates wherein the target computing node is different from the computing node simulating the memory operation ASAAD ([0388] “FIG. 3-2-1 illustrates a flow chart illustrating method steps performed by a stream prefetch engine (e.g., a stream prefetch engine 20200 in FIG. 3-2-2) in a parallel computing system (different from the computing node) in one embodiment. A stream prefetch engine refers to a hardware or software module for performing fetching of data (simulating the memory operation) in a plurality of streams before the data is needed. The parallel computing system includes a plurality of computing nodes. A computing node (target computing node) includes at least one processor and at least one memory device. At step 20100, a processor issues a load request (e.g., a load instruction) (simulating the memory operation). The stream prefetch engine 20200 (different from the computing node) receives the issued load request.”) See also ASAAD ([Figure 5-4-1A].)
ASAAD also anticipates the target computing node is further to send a response to the computing node simulating the memory operation via a packet formatted according to the MPI protocol ASAAD ([2043] “Parallel computer applications often use message passing to communicate between processors. Message passing utilities such as the Message Passing Interface (MPI) (according to the MPI protocol) support two types of communication: point-to-point and collective. In point-to-point messaging, a processor (target computing node) sends a message (simulating the memory operation via a packet formatted) to another processor (to send a response to the computing node) that is ready to receive it. In a collective communication operation, however, many processors participate together in the communication operation.”) See also ASAAD ([1965], ([Figure 6-3-3], ([Figure 6-8-7] and [Figure 6-8-6].)
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Claim 13
Claim 13 is rejected because it is the non-transitory computer-readable media embodiment of claims 1, 5, and 8 with similar limitations to claims 1, 5, and 8 and is such rejected using the same reasoning found in claims 1, 5, and 8.
ASAAD also anticipates initialize, on respective computing nodes of a distributed simulation system, a system memory portion representing a subset of a system memory of a graph processing system wherein each instructions are to initialize the system memory portion initialize, respective computer nodes of a distributed simulation system and to be simulated by the computing node and to be simulated on a computing node ASAAD ([0025-0027] “At least three modes of operation are supported. In the full virtual node mode, each of the processing cores will perform its own MPI (message passing interface) process independently. Each core is running four thread/process, and it uses a sixteenth of the memory (L2 and SD RAM) of the node, while coherence among the 64 processes within the node and across the nodes is maintained by MPI. In the full SMP, one MPI task with 64 threads ( 4 threads per core) is running, using the whole node memory capacity. The third mode called the mixed mode. Here 2,4,8, 16, and 32 processes are running 32,16,8,4, and 2 threads, respectively. Because of the torus' DMA feature, internode communications can overlap with computations running concurrently on the nodes. With respect to the Torus network, it is configured, in one embodiment, as a 5-dimensional design supporting hyper-cube communication and partitioning. A 4-Dimensional design allows a direct mapping of computational simulations of many physical phenomena to the Torus network. See also ASAAD ([2218] “In step 96302, a static processor analysis is conducted and its analysis results may be output via a signal (initialize). This analysis is conducted by simulating on a computer the operation of the processor running a particular workload. Using the results of the simulation, the computer determines the optimal core or set of cores (respective computing nodes of a distributed simulation system) to turn off given the particular workload.”) See also ASAAD ([0287] A compute node of this present massively parallel supercomputer architecture and in which the present invention may be employed is illustrated in FIG. 1-0. The compute nodechip 50 is a single chip ASIC ("Nodechip") based on low power processing core architecture, though the architecture can use any low power cores, and may comprise one or more semiconductor chips (respective computing nodes of a distributed simulation system). See also ASAAD ([0917] “The PowerPC architecture has an instruction type known as larx/stcx (instructions). This instruction type can be implemented (to initialize the system memory portion) as a special case of TM (transactional memory). The larx/stcx pair (instructions) will delimit a memory access request (initialize the system memory portion) to a single address (representing a subset of a system memory) and set up a program section that ends with a request to check whether the memory access request was successful or not. More about a special implementation of larx/stcx instructions using reservation registers is to be found in copending application Ser. No. 12/697,799 filed Jan. 29, 2010, which is incorporated herein by reference. This special implementation uses an alternative approach to TM to implement these instructions. In any case, TM is a broader concept than larx/stcx. A TM section can delimit multiple loads and stores to multiple memory locations in any sequence, requesting a check on their success or failure and a reversal of their effects upon failure. TM is generally used for only a subset of an application program (graph processing system), with program sections before and after executing in speculative mode.”) See also ASAAD ([Figure 4-7-1A].)
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ASAAD also anticipates accessing an input file representing an initial state of the system memory and copying, to the computing node, portions of the input file corresponding to a respective system memory portion to be simulated by the computing node ASAAD ([0558] “At step 3430, the MU 3220 looks at the flag bit (representing an initial state of the system memory) based on a memory location or address specified in the store instruction, validates the updated data if determined that the flag bit on the updated data is set, and sends the updated data to other processor cores or other computing nodes (copying, to the computing node, portions of the input file corresponding to the respective simulated system memory portion) that the MU does not belong to. In one embodiment, the MU 3220 monitors load instructions and store instructions issued by processor cores, e.g., by accessing an instruction queue (accessing an input file representing an initial state of the system memory).”)
ASAAD also anticipates perform a functional simulation of a core of the graph processing system ASAAD ([0689] “The flowchart and block diagrams in the Figures illustrate the architecture, functionality (perform a functional simulation), and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention (core of the graph processing system). In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s).”
ASAAD also anticipates the functional simulation comprising one or more memory operations, wherein the instructions are to simulate a memory operation ASAAD ([0682] “In implementing the various levels of synchronization (one or more memory operations) herein, sub-sets of this set of sub-tasks (functional simulation) can be viewed as partial synchronization tasks to be allocated between threads in an effort to improve throughput of the system. Therefore address formats of instructions specifying a synchronization level effectively (instructions are to simulate a memory operation) act as parameters to offload sub-tasks from or to the thread containing the synchronization instruction. If a particular sub-task (functional simulation) implicated by the memory synchronization instruction (instructions are to simulate a memory operation) is not performed by the thread containing the memory synchronization instruction, then the implication is that some other thread will pick up that part of the memory synchronization function. While particular levels of synchronization are specified herein, the general concept of distributing synchronization sub-tasks between threads is not limited to any particular instruction type or set of levels.”)
ASAAD also anticipates determining a target computing node of the system based on a system memory address indicated in the memory operation ASAAD ([1486] “Interrupts and, in one embodiment, interrupt masking (determine) for the MU 65100 (target computing node of the system) provide additional functional flexibility. In one embodiment, interrupts may be grouped to target a particular processor on the chip (indicated in the memory operation), so that each processor can handle its own interrupt. Alternately, all interrupts can be configured to be directed to a single processor (indicated in the memory operation) which acts as a "monitor" of the processors on the chip. The exact configuration can be programmed by software at the node (target computing node) in the way that it writes values into the configuration registers (based on a system memory address).”)
ASAAD also anticipates routing the memory operation to the target computing node ASAAD ([1520] “As an example, assume node 671021 is a sending node and node 671026 is a receiving node. Nodes 671021 and 671026 are indirectly connected. There exists between these nodes a 'best' path for communicating data packets. In an asymmetrical torus, experiments conducted on the IBM BLUEGENE™ parallel computer system have revealed that the 'best' path is generally found by routing the data packets along the longest dimension first, then continually routing the data across the next longest path, until the data is finally routed across the shortest path to the destination node.”)
Claim 14
Claim 14 is rejected because it is the non-transitory computer-readable media embodiment of claim 6, with similar limitations to claim 6, and is such rejected using the same reasoning found in claim 6.
Claim 15
Claim 15 is rejected because it is the non-transitory computer-readable media embodiment of claim 7, with similar limitations claim 7, and is such rejected using the same reasoning found in claim 7.
Claim 16
Claim 16 is rejected because it is the non-transitory computer-readable media embodiment of claim 10, with similar limitations to claim 10, and is such rejected using the same reasoning found in claim 10.
Claim 17
Claim 17 is rejected because it is the non-transitory computer-readable media embodiment of claim 11 with similar limitations to claim 11 and is such rejected using the same reasoning found in claim 11.
Claim 18
Claim 18 is rejected because it is the non-transitory computer-readable media embodiment of claim 2 with similar limitations to claim 2 and is such rejected using the same reasoning found in claim 2.
Claim 19
Claim 19 is rejected because it is the non-transitory computer-readable media embodiment of claim 3 with similar limitations to claim 3 and is such rejected using the same reasoning found in claim 3. ASAAD also anticipates the memory controller to process the memory operations ASAAD ([0834] “The read return buffer 4304 buffers read data from eDRAM or the memory controller 78 (memory controller) and is responsible for scheduling the data return (process the memory operations) using the switch 60.”)
Claim 20
Claim 20 is rejected because it is the system embodiment of claims 1, 5, 8, and 13, with similar limitations to claims 1, 5, 8, and 13 and is such rejected using the same reasoning found in claims 1, 5, 8, and 13.
ASAAD also anticipates executing memory operation instructions on cores of the graph processing system comprising, wherein execution of the memory operation instructions ASAAD ([0589] “In accordance with the embodiment disclosed herein, to support concurrent memory synchronization instructions (executing memory operation instructions), requests are tagged with a global "generation" number. The generation number is provided by a central generation counter. A core (on cores of the graph processing system) executing a memory synchronization requests (wherein execution of the memory operation instructions) the central unit to increment the generation counter and then waits until all memory operations of the previously current generation and all earlier generations have completed.”) See also ASAAD ([1891] “The method of the present invention is generally implemented by a computer executing a sequence of program instructions (executing memory operation instructions) for carrying out the steps of the method (wherein execution of the memory operation instructions) and may be embodied in a computer program product (on cores of the graph processing system) comprising media storing the program instructions. Although not required, the invention can be implemented via an application-programming interface (API), for use by a developer, and/or included within the network browsing software, which will be described in the general context of computer-executable instructions, such as program modules, being executed by one or more computers, such as client workstations, servers, or other devices.”)
Claim 21
Claim 21 is rejected because it is system embodiment of claims 6 and 14, with similar limitations to claims 6 and 14, and is such rejected using the same reasoning found in claims 6 and 14.
Claim 22
Claim 22 is rejected because it is the system embodiment of claims 7 and 15, with similar limitations to claims 7 and 15, and is such rejected using the same reasoning found in claims 7 and 15.
Claim 23
Claim 23 is rejected because it is the non-transitory computer-readable media embodiment of claims 10 and 16 with similar limitations to claims 10 and 16, and is such rejected using the same reasoning found in claims 10 and 16.
Claim 24
Claim 24 is rejected because it is the non-transitory computer-readable media embodiment of claim 20, with similar limitations to claim 20 and is such rejected using the same reasoning found in claims 20.
ASAAD also anticipates initialize a computing node of a distributed graph processing system, the node comprising a system memory portion representing a subset of a system memory of a graph processing system ASAAD ([2176-2177] “FIG. 7-3-4 graphically illustrates a functional block diagram of an exemplary embodiment of a structure of a system (distributed graph processing system) configured to implement the process of FIG. 7-3-1. [2177] FIG. 7-3-4 shows a structure of a processor 94400 (initialize a computing node), which includes four processor cores 94403a-d (the node comprising a system memory portion representing a subset of a system memory of a graph processing system). Each of the processor cores 94403a-d is operably coupled to a memory bus or interconnect 94407, in order to exchange data among the cores and with main memory or other input/output units.”) See also ASAAD ([Figure 7-3-4].)
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Claim 25
Claim 25 is rejected because it is the non-transitory computer-readable media embodiment of claims 10, 16, and 23 with similar limitations to claims 10, 16, and 23, and is such rejected using the same reasoning found in claims 10, 16, and 23. ASAAD also anticipates wherein the instructions are to determine the target computing node ASAAD ([Fig. 4-2-4] and [0071]“ FIG. 4-2-4 shows what happens in the system in response to the instructions of FIG. 4-2-3A.”) Examiner Note: Here Fig. 4-2-3A instructions determine the α and β target computing nodes or threads shown in Fig. 4-2-4.
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Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARTIN K VU whose telephone number is (703)756-5944. The examiner can normally be reached 7:30 am to 4:30 pm M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Renee Chavez can be reached on 571-270-1104. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.K.V./Examiner, Art Unit 2186
/RENEE D CHAVEZ/Supervisory Patent Examiner, Art Unit 2186