DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Remarks/Arguments
This Office Action is in response to the communications for the present US application number 17/711,742 last filed on September 18th, 2025.
Claims 1-31 were previously cancelled.
Claims 32-56 remain pending and have been examined, directed to DYNAMIC LATENCY-RESPONSIVE CACHE MANAGEMENT.
Upon further review of the latest filed claims with no amendments along with the applicant’s representative’s response, the examiner reviewed the applied references and respectfully remain unpersuaded at this time.
With respect to the 35 U.S.C. § 102 rejection, using Eckert, and with respect to independent claim 32 for discussion purposes, the applicant’s representative argued in general terms, without specifying which limitation features were not specifically taught. The representative ended up summarizing Eckert’s teachings by using synonymous terms and phrases that ended up generally describing the same claimed concepts.
In response, the current claim language was directed to a system carrying out a process involving determining (or identifying or evaluating or measuring or monitoring) a cost associated with a fetching process for data, depending on where the data was stored, between say at least two locations. The cost is also further defined as based upon fetch latency. And when the fetch cost/latency exceeds some (arbitrarily unknown or currently undefined) threshold level, then that data can be moved (or transferred or sent or relocated or evicted) from location one to location two.
In comparison, the representative’s summary of what Eckert disclosed, based on the Examiner’s summary, also highlighted on the very same elements, that is, there were different latency cost from different cache locations that were identified and the system could transfer the data from a cache with longer latencies to a cache with shorter latencies, and thus improve on performance. The representative’s argument that Eckert was performing these steps in response to a cache miss, but the current claim language does not have limitations or restriction on any underlying reasonings of when this process can occur. Only the fetch cost or fetch latency is considered, before triggering a move to move the data between two locations. Under broadest reasonable interpretations, the current claim language describes a process that can happen at any time/cycle and with every fetch or fetch related request. The emphasis on other sections like what causes an “eviction” decision, was also not found to be persuasive, because there are again other synonymous terms that can be used to describe this same process of moving the data from one location to another with better “costs” involved. The representative further argued via summarizing other Eckert sections like from ¶¶ 8-10, which were not found persuasive either because when Eckert refers to “conventional” approaches or solutions as previous works, and Eckert’s teachings are an improvement or builds upon or at the very least, is different from those “conventional” approaches. In other words, Eckert is not performing in a fixed manner, and Eckert’s improvement as the representative cited, is based upon having the lowest access latency under changing or variable operation conditions, which is what the current claim language is directed to.
With respect to dependent claim 34 for discussion purposes, rejected under 35 U.S.C. § 103, using Eckert and Dey, the representative further argued that the combined teachings from the applied references did not teach of the claimed features with respect to evaluating fetch costs from a number of delayed hits (on accessing data) and determining a fetch cost based on mean weighted average on the time associated from the delayed hits. The representative acknowledged that Dey taught about the delayed hits and about the weighted averages, but argued Dey didn’t not address fetching costs. The representative appeared to have argued Dey’s relied upon teachings like a single 102 reference, without considering the combination of how Dey’s teachings could be combined and incorporated within Eckert’s teachings.
In response, the Examiner again respectfully disagree because following what was already established in the independent claim 32, it’s been already established that Eckert already addressed the aspect about fetch costs and fetch latencies. The new aspects in this dependent claim directed to delays and the weighted averaged are what is needed and supplemented from the secondary reference Dey. By combining and incorporating these missing features from Dey into Eckert, it would have been obvious to one of ordinary skill in the art, before the effective filing date, that all of these average weighted delay hits, would have an impact on the fetch cost/latency, as already taught by Eckert. And by considering all of these delays and additional times to be, the system would be making decisions to adjust and/or adapt to the changing conditions of the system, and possibly move data around between locations/caches. Additionally, some of the other comments about the differences in the underlying reasoning on why these claimed steps are taken is unfortunately not persuasive because those reasons are not in the current claim language, at this time. Under, broadest reasonable interpretations, the steps and processes taken by this system can again occur iteratively at any time and/or after each fetch request.
The Examiner has reviewed and further expounded by re-emphasized these points within the rejection portion itself. For at least these reasons, the Examiner remains unpersuaded at this time.
The remaining dependent claims were not further specifically argued at this time.
Applicant's arguments were considered but they were not found persuasive. See the following claim rejections for further clarifications with added emphasis on the points previously disclosed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 32, 33, 40, 44, 45, and 49 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Publication No. US 2019/0324906 A1 to Eckert, Yasuko (referred to hereafter as “Eckert”).
As to claim 32, Eckert further discloses an apparatus employed as an object management system (OMS) in a multi-tiered caching system including a plurality of storage tiers, the apparatus comprising:
memory circuitry to store program code of the OMS (e.g., Eckert: ¶ 32); and
processor circuitry connected to the memory circuitry (e.g., Eckert: ¶ 32), wherein the processor circuitry is to execute the program code to:
measure a fetch cost for accessing an object from a first cache of a first storage tier of the plurality of storage tiers in which the object is currently stored, wherein the fetch cost is based on a fetch latency, and the fetch latency is an amount of latency of the object being delivered to a requestor of the object (Eckert discloses of an overall system that can evaluate and make the decision, iteratively, on where to retrieve a piece of data, from with two memory locations, based on a cost associated measured in terms of latency, e.g., Eckert: Figs. 2-4 examples and related ¶¶ 24-30);
determine a second storage tier of the plurality of storage tiers in which to evict the object when the fetch cost exceeds a threshold (This condition or scenario of when the cost/latency is too high, exceeding some threshold level, would have to mean (or interpreted such that) the data/object is not at the closest possible storage, in terms of latency costs.
Eckert discloses that a manager (component) can determine or identify different latencies to different caching locations (e.g., L1 cache, L2 cache, etc.) and then also transfer the data to a particular cache, aiming to reducing latency and improve performance (e.g., Eckert: abstract, ¶¶ 8-9). In Figs. 2 and 3’s examples, at any given time, a request for some data can result in the system finding it at different cache/memory locations with different latencies. The system can choose to transfer the data from a (lower) cache with long latencies to a closer cache with shorter latencies. Even though Figs. 2 and 3 illustrate the point with at least two different sources, only one is needed, as Eckert discloses that the data would be transferred to the closer cache (e.g., cache 105) which can be readily handle requests for that same data from then onwards (e.g., Eckert: ¶¶ 25-29). Also, the flowchart in Fig. 4 uses the latency of the last level cache (LLC) has a threshold setting for the determination/evaluation, which is understood to be variable and can change over time, similar to how Fig. 3 illustrates two different time instances with different latencies);
cause eviction of the object from the first cache (Following the same conceptual examples as described above, a first cache can be referring to a low level cache and Eckert’s system can find the data within that cache and decide to transfer it to another cache with a lower latency (e.g., to cache 105), e.g., Eckert: Figs. 2-4 and ¶¶ 25-29); and
store the evicted object in the second cache (Following the same conceptual examples as described above, the data is moved from a cache with longer latencies to a second cache with shorter latencies, and in the example, the second cache is cache 105).
As to claim 33, Eckert further discloses the apparatus of claim 32, wherein the processor circuitry is to execute the program code to:
determine the fetch cost based on a fetch latency, wherein the fetch latency is based on a fetch time, and the fetch time is an amount of time between issuing a fetch command to access the object from the first cache and delivery of the object to the requestor (The fetch cost as defined in terms of latency or time appears to be a standard definition. Eckert describes of latencies associated with fetches at different cache locations, which taken at face value would account for the time for the data to be delivered to the requestor or their respective devices, e.g., Eckert: ¶ 11).
As to claim 40, Eckert further discloses the apparatus of claim 32, wherein the processor circuitry is to execute the program code to:
determine a latency requirement for delivery of the object from the first cache to the requestor, a current latency of delivery of data from the first cache to the requestor, and a current network route between the first cache and the requestor (Following claim 32, Eckert discloses of several variations from Figs. 2-4, which covers the concept of determining the latency along two possible routes, which means the system can select the source/route with the lower latency costs, e.g., Eckert: Figs. 2-4 and ¶¶ 25-29); and
route the object to be delivered to the requestor over a new network route to the requestor when the current latency and an estimated remaining latency is larger than the latency requirement (Once again, the system would pick whichever has the lowest latencies and associated costs, e.g., Eckert: Figs. 2-4 and ¶¶ 25-29).
As to claim 44, Eckert further discloses the apparatus of claim 32, wherein the apparatus is one of a router, a switch, a smart edge switch, a gateway device, a network appliance, a load balancing server, a firewall appliance, a data processing unit (DPU), an infrastructure processing unit (IPU), a network interface controller (NIC), a smart NIC, a storage controller, a cache controller or caching agent of interconnect interface circuitry, a memory controller, an in-memory caching engine, a server host processor platform, a hardware accelerator, and a cloud computing service (Following claim 32, the system (or apparatus) as a whole as Eckert disclosed can be implemented by physical components or as a system processing software, which would still read upon several of these listed options like any processing unit(s), controllers, platform or service, e.g., Eckert: ¶ 32).
As to claim 45, Eckert further discloses the apparatus of claim 32, wherein the OMS is implemented as, or part of, a protocol stack layer of a communication protocol, a network storage stack software element on a DPU, a Software-Defined Networking switch, virtualized network function, an in-server library, a caching agent of a message broker framework, a user agent caching mechanism, or a web caching system (Following claim 32, the overall system can be interpreted as a web caching system, e.g., Eckert: ¶ 32).
As to claim 49, see the similar corresponding rejections of claim 40.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 34, 47, 51 and 52 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. US 2019/0324906 A1 to Eckert in view of U.S. Patent Publication No. US 2014/0280679 A1 to Dey et al. (referred to hereafter as “Dey”).
As to claim 34, Eckert further discloses the apparatus of claim 33, wherein the processor circuitry is to execute the program code to:
determine a number of delayed hits of accessing the object (see below that covers all three factors);
determine the fetch cost based on the fetch time and the number of delayed hits (see below that covers all three factors); and
determine the fetch cost based on a mean weighted average (MWA) of the fetch time compounded with the number of delayed hits (Following after claims 32 and 33, while Eckert does not expressly disclose of these three limitation factors, with respect to determining the fetch cost associated with each delayed hit(s) and also having the cost based upon a mean weighted average of time, Dey was found to more expressly disclose about of weighted averages, impacted from delayed hits, all of which can be associated with some cost value, that’s also similarly tied to delays or latencies in those fetches (e.g., Dey: ¶¶ 76 and 65).
Based on Dey’s teachings, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the present application, to combine and incorporate these considerations or factors within Eckert’s overall system, such that in a resulting combined system, all of these calculated average weighted delay hits, would have some impact on the fetch cost or fetch latencies, as already taught from Eckert. And by considering these additional average weighted delays or additional times, the system as a whole would need to be re-calculating and making the determinations constantly to adjust and/or adapt to the changing costs/latencies/delays of the system, and possibly move the data around between different caches or memory locations, while trying to improve on the overall cost and performance of the system).
As to claim 47, see the similar corresponding rejections of claims 33 and 34 combined, and wherein in the last limitation step, Eckert in view of Dey’s incorporated teachings of weighted averages would teach and/or suggest of:
… determine the fetch cost as a mean weighted average (MWA) of the fetch time compounded with the number of delayed hits, wherein the MWA includes one or more of a simple moving average (SMA), a cumulative average (CA), a weighted moving average (WMA), an exponential moving average (EMA), an exponentially weighted moving average (EWMA), a modified moving average (MMA), a running moving average (RMA), a smoothed moving average (SMMA), or a moving average regression model (Similar to claim 34, Dey’s ¶ 76 describes weighted averages, which would read upon at the very least WMA listed here. See the similar stated reasons as previously mentioned for combining and incorporating Dey’s teachings within Eckert’s overall system).
As to claim 51, see the similar corresponding rejections of claim 34.
As to claim 52, see the similar corresponding rejections of claim 47.
Claims 35, 36, 48, and 53 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. US 2019/0324906 A1 to Eckert in view of U.S. Patent Publication No. US 2014/0280679 A1 to Dey and further in view of U.S. Patent No. US 9,600,200 B1 to Wallace et al. (referred to hereafter as “Wallace”).
As to claim 35, Eckert further discloses the apparatus of claim 34, wherein the processor circuitry is to execute the program code to:
determine a mean time to reuse (MTR) of the object based on a time-series aggregation of a reuse time, wherein the reuse time is a time between a previous access of the object and a current access of the object (Following after claims 32-34, while Eckert and Dey both do not expressly disclose of the MTR feature, Wallace more expressly discloses of this MTR value which is an average of the time interval, with respect to some data, to determine its reuse frequency (e.g., Wallace: col. 8, ll. 15-27).
Based on Wallace’s teachings, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the present application, to combine and incorporate this technique with determining the MTR value within Eckert’s overall system, which can be utilized and analyzed over time to improve on costs and performance for the future).
As to claim 36, Eckert further discloses the apparatus of claim 35, wherein the processor circuitry is to execute the program code to:
aggregate cache space among caches of the storage tiers of the plurality of storage tiers (see below as the allocation encompasses this step/feature); and
allocate an amount of the aggregated cache space to the object based on the fetch cost, MTR, and an access density of the object (Following claims 32-34, while Eckert and Dey both do not expressly disclose of this step, Wallace once again more expressly discloses of the overall concept with respect to grouping and caching similar/related data contents, which covers the new density factor (e.g., Wallace: col. 3, ll. 4-22). The other two factors are already covered as “fetch cost” is something that Eckert considers overall, and the MTR value was also covered in claim 35.
Once again, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the present application, to combine and incorporate Wallace’s teachings regarding this grouping of similar contents to achieve some efficient level of density, all within Eckert’s overall system, all of which is to improve on costs and performance).
As to claim 48, see the similar corresponding rejections of claim 35.
As to claim 53, see the similar corresponding rejections of claim 35.
Claims 37, 38, 54 and 55 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. US 2019/0324906 A1 to Eckert in view of U.S. Patent Publication No. US 2014/0280679 A1 to Dey and further in view of U.S. Patent No. US 9,600,200 B1 to Wallace and further in view of U.S. Patent No. US 11,537,627 B1 to Baskaran et al. (referred to hereafter as “Baskaran”).
As to claim 37, Eckert further discloses the apparatus of claim 36, wherein the processor circuitry is to execute the program code to:
increase a replication factor of the object when the object has a higher fetch cost than other objects stored in the first cache or other caches of other storage tiers of the plurality of storage tiers (Following claims 32-36, while Eckert, Dey, and Wallace all do not expressly disclose of this feature, Baskaran more expressly discloses of considering a replication factor and performing replication when needed, (e.g., Baskaran: col. 16, ll. 57-64 and col. 51, ll. 32-40).
Based on Baskaran’s teachings, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the present application, to combine and incorporate this technique with replicating as needed, which can be analyzed and evaluated over time to improve on costs and performance for the future).
As to claim 38, Eckert further discloses the apparatus of claim 37, wherein the processor circuitry is to execute the program code to:
increase a compression factor for the object when the object has a higher fetch cost than other objects stored in the first cache or other caches of other storage tiers of the plurality of storage tiers (Following claims 32-37, while Eckert and Dey do not expressly disclose about compression, Wallace does more expressly discloses of about different compression techniques (e.g., Wallace: col. 4, ll. 48-54 and col. 14, ll. 9-12).
When combined and incorporated within Eckert’s overall system and teachings, which is already balanced against costs, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the present application, that compression can be applied variably to directly impact the fetch cost values within the overall combined system); and
distribute, by the OMS, the object with consistent hashing across the aggregated cache space (While Eckert, Dey, and Wallace all do not expressly disclose of this feature, Baskaran once again more expressly discloses of consistent hashing (e.g., Baskaran: col. 44, ll. 59 – col. 45. ll. 4).
Once again, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the present application, to combine and incorporate teachings from both Wallace and also Baskaran’s teachings of the two different features, all within Eckert’s overall system to improve on costs and performance for the future).
As to claim 54, see the similar corresponding rejections of claims 36, 37, and 38 combined.
As to claim 55, see the similar corresponding rejections of claim 40.
Claims 39, 46 and 50 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. US 2019/0324906 A1 to Eckert in view of U.S. Patent Publication No. US 2014/0289473 A1 to Hirao, Taichi (referred to hereafter as “Hirao”).
As to claim 39, Eckert further discloses the apparatus of claim 32, wherein the processor circuitry is to execute the program code to:
detect a request for the object issued by the requestor (see below for all of these steps combined); and
cause issuance of the fetch command to access the object from the first cache when there is no outstanding fetch command for the object (see below for all of these steps combined);
wait until the object is fetched from the first cache when there is an outstanding fetch command for the object (see below for all of these steps combined); and
cause delivery of the object to the requestor when the object is fetched from the first cache (Following claim 32, these steps outline a concept of waiting in the case of an outstanding fetch on the same object. While Eckert does not expressly disclose of this scenario or condition, Hirao more expressly discloses of a similar system that takes into account of indicating and waiting if there’s any outstanding read/write the same cached data (e.g., Hirao: ¶¶ 66 and 140-141).
Based upon Hirao’s teachings, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the present application, to combine and incorporate Hirao’s specific teachings, all within Eckert’s overall system, all of which would avoid problems like faults, and all with the goal of improving on costs and/or performance).
As to claim 46, see the similar corresponding rejections of claims 32 and 39 combined.
As to claim 50, see the similar corresponding rejections of claims 32 and 39 combined.
Claims 41-43 and 56 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. US 2019/0324906 A1 to Eckert in view of U.S. Patent No. US 9,678,981 B1 to Taylor et al. (referred to hereafter as “Taylor”).
As to claim 41, Eckert further discloses the apparatus of claim 32, wherein the second storage tier is a best-effort storage tier in comparison with other storage tiers of the plurality of storage tiers when:
the fetch cost is less than or equal to the threshold (see below), and
the first storage tier is an outer-most storage tier among the plurality of storage tiers (Following claim 32, while Eckert does not expressly disclose in details about the type of storage between two memory/cache locations, Taylor more expressly discloses of the concept of utilizing a “best effort” approach with caches (e.g., Taylor: col. 53, ll. 44-54). Taylor also more expressly covers the idea of outer edge on a disk platter (e.g., Taylor: col. 19, ll. 42-43).
Therefore, it would be entirely possible to implement one or more caches like the second storage tier to be a best effort cache, in comparison to the first cache (from claim 32), such that it meets the two criteria here, with respect to fetch costs and also having the first cache assigned or allocated to the outer edge of a platter for example.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the present application, to combine and incorporate Taylor’s teachings within Eckert’s overall system and teachings, all in order to improve on costs and performance).
As to claim 42, Eckert further discloses the apparatus of claim 32, wherein the second storage tier is a nearest available storage tier with respect to the first storage tier when:
the fetch cost is greater the threshold (see below again), and
the first storage tier is an outer-most storage tier among the plurality of storage tiers (Similar to claim 41, once again while Eckert does not expressly disclose in details about a nearest cache or storage means, Taylor once again more expressly discloses of the concept of having data storage as close together as possible for example (e.g., Taylor: col. 19, ll. 33-35).
Therefore, it would be entirely possible to implement one or more caches like the second storage tier to be as close as possible to the first cache (from claim 32), such that it meets the two criteria here which were already covered in claim 41.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the present application, to combine and incorporate Taylor’s teachings within Eckert’s overall system and teachings, all in order to improve on costs and performance).
As to claim 43, Eckert further discloses the apparatus of claim 32, wherein the second storage tier is a storage tier of the plurality of storage tiers further from the requestor than the first storage tier when:
the first storage tier is not an outer-most storage tier among the plurality of storage tiers (Similar to claims 41 and 42, once again while Eckert does not expressly disclose in details about the positioning as nearest or furthest caches, Taylor once again more expressly discloses of the concept of placement (e.g., Taylor: col. 19, ll. 33-35 and ll. 42-43). Therefore, it would have been obvious that the first and second caches can be selected or determined based upon any given condition, such as not the outer-most or etc.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the present application, to combine and incorporate Taylor’s teachings within Eckert’s overall system and teachings, all in order to improve on costs and performance).
As to claim 56, see the similar corresponding rejections of claims 41, 42, and 43 combined.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Xiang Yu whose telephone number is (571)270-5695. The examiner can normally be reached M-F 9:30-3:00 (PST/PDT).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Emmanuel Moise can be reached at (571)272-3865. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/X.Y./Examiner, Art Unit 2455
/EMMANUEL L MOISE/Supervisory Patent Examiner, Art Unit 2455
Prosecution Insights