DETAILED ACTION
This Office action is in response to the amendment submitted on January 16, 2026.
Claims 1-21 are pending.
Claims 19 and 21 are currently amended.
The objection to Claim 19 is withdrawn in view of the Applicant’s amendments to the claim.
The 35 U.S.C. § 112(b) rejections of Claims 19-21 are withdrawn in view of the Applicant’s amendments to the claims.
The 35 U.S.C. § 101 rejections of Claims 1-21 are maintained in view of the Applicant’s arguments and further explained hereinafter.
For clarity of the prosecution history record, Claims 6 and 19 recite the limitation “executed/run more efficiently.” It is noted that the Applicant’s specification states that “[…] when that number is four, the translation 310 may unroll the loop four times into iterations 312, 314, 316, and 318 of the instructions 302, 304, 306, and 308. When the iteration 318 is completed, a loop instruction 309 is used to return to the instruction 302 of the iteration 312. Thus, by moving between the addresses of the iterations 312, 314, 316, and 318 without looping, the translated code may be completed more efficiently” (page 29, paragraph [0084]). Thus, the term “more efficiently” appears to be described by the specification which provides a standard for ascertaining the requisite degree and one of ordinary skill in the art would be able to reasonably determine the scope of the claimed invention. Therefore, Claims 6 and 19 meet the requirements of § 112(b).
In the interest of facilitating compact prosecution, the Examiner kindly asks the Applicant’s representative to authorize Internet communications with the Examiner by submitting Form PTO/SB/439 using Patent Center.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Claim Interpretation: Under the broadest reasonable interpretation (BRI), the limitations of Claim 1 are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. See MPEP § 2111.
Claim 1 recites:
The step of “receive the stored instructions.” The claim does not impose any limits on how the stored instructions are received; and
The step of “translate the stored instructions into translated code that includes one or more numbered instructions that include a field indicating a number of branches in the stored instructions that are taken in the translated code.” The claim does not impose any limits on how the stored instructions are translated.
In addition, these steps are recited as being performed by a system comprising memory and a processor. The memory and processor are recited at a high level of generality, i.e., as generic computer components performing generic computer functions.
Step 1: Claim 1 is directed to a system, which is a machine and/or manufacture, and falls within one of the statutory categories of invention.
Step 2A, Prong One: Claim 1 recites the limitation:
(a) translate the stored instructions into translated code that includes one or more numbered instructions that include a field indicating a number of branches in the stored instructions that are taken in the translated code.
The recited step, under the broadest reasonable interpretation (BRI), covers performance of the step in the human mind alone or with the aid of pen and paper. That is, other than reciting:
(1) memory to store instructions; and
(2) a processor comprising an instruction converter to.
Nothing in the claim precludes the step from practically being performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper. For example, the limitation (a) in the context of the claim encompasses a human evaluating the stored instructions using observation, evaluation, judgment, and opinion to translate the stored instructions into translated code. See MPEP § 2106.04(a)(2)(III).
If a claim limitation, under its broadest reasonable interpretation (BRI), covers performance of the limitation in the human mind alone or with the aid of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A, Prong Two: This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements:
(1) memory to store instructions; and
(2) a processor comprising an instruction converter to.
The additional elements (1) and (2) are recited at a high-level of generality such that they amount to no more than mere instructions to apply the judicial exception using generic computer components. The memory and processor are used as tools to perform the receiving and translating steps of the claim. See MPEP § 2106.05(f).
Also, the claim recites the additional element:
(3) receive the stored instructions.
The additional element (3) is mere data gathering recited at a high level of generality, and thus is an insignificant extra-solution activity. See MPEP § 2106.05(g). Furthermore, all uses of the recited judicial exception require such data gathering, and, as such, the additional element does not impose any meaningful limits on the claim. The additional element amounts to necessary data gathering. See MPEP § 2106.05.
Accordingly, even when viewed in combination, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as a combination do not amount to significantly more than the abstract idea. As discussed hereinabove with respect to integration of the abstract idea into a practical application, the claim recites the additional elements:
(1) memory to store instructions; and
(2) a processor comprising an instruction converter to.
The additional elements (1) and (2) amount to no more than mere instructions to apply the judicial exception using generic computer components. Mere instructions to apply a judicial exception using generic computer components cannot provide an inventive concept.
Also, the claim recites the additional element:
(3) receive the stored instructions.
The additional element (3) simply appends a well-understood, routine, and conventional activity previously known to the industry, specified at a high level of generality, to the judicial exception is not indicative of an inventive concept. MPEP § 2106.05(d)(II) expressly states that the courts have recognized the computer functions of storing and retrieving information in memory and receiving or transmitting data over a network, e.g., using the Internet to gather data as well‐understood, routine, and conventional computer functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as an insignificant extra-solution activity. Thus, a person of ordinary skill in the art would readily comprehend that it is well-understood, routine, and conventional in the computing art to receive portions of computer program code. Therefore, the additional element remains an insignificant extra-solution activity even upon reconsideration and does not amount to significantly more.
Thus, taken alone, the additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the additional elements as a combination adds nothing that is not already present when looking at the additional elements taken individually. Even when considered in combination, the additional elements represent mere instructions to apply a judicial exception using generic computer components and an insignificant extra-solution activity, and therefore do not provide an inventive concept. The claim is not patent eligible.
Claims 2-15 are rejected under 35 U.S.C. 101 as directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more for at least the reasons stated hereinabove.
Claim 2 recites the limitation:
(a) a binary translation processor to execute the translated code.
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Claim 3 recites the limitation:
(a) a just-in-time compiler to compile the translated code.
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Claim 4 recites the limitation:
(a) wherein the instruction converter is implemented using software executed by an execution unit of the processor.
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Claim 5 recites the limitation:
(a) wherein the processor further comprises hardware circuitry that implements the instruction converter.
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Claim 6 recites the limitation:
(a) wherein translating the stored instructions into the translated code comprises optimizing the translated code to be executed more efficiently by the processor than without optimization.
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Claim 7 recites the limitation:
(a) wherein the optimization comprises loop unrolling looped instructions a number of times equal to the number of branches indicated in the field.
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Claim 8 recites the limitation:
(a) wherein the unrolled looped instructions comprise a plurality of iterations each having a backward loop branch of a loop that are combined and replaced with an indexed instruction of one or more indexed instructions.
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Claim 9 recites the limitation:
(a) wherein a number of iterations in the plurality of iterations is equal to a number of taken branches in the field.
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Claim 10 recites the limitation:
(a) wherein the one or more indexed instructions comprise a branch type field that indicates a type of branch taken as indicated by the number of branches in the translated code.
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Claim 11 recites the limitation:
(a) wherein the branch type field indicates a backward loop branch when the optimization comprises loop unrolling.
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Claim 12 recites the limitation:
(a) wherein the one or more indexed instructions comprise an original taken branch that indicates an emulated real instruction pointer of the original taken branch from the stored instructions in the translated code.
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Claim 13 recites the limitation:
(a) wherein the one or more indexed instructions comprise a branches not taken field indicating a number of branches in the stored instructions that are not taken in the translated code.
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Claim 14 recites the limitation:
(a) wherein the one or more indexed instructions comprise a history field that indicates an order of branches both taken and not taken from the stored instructions when translated into the translated code.
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Claim 15 recites the limitation:
(a) wherein the optimization comprises translating a conditional branch to an assertion.
These claims are dependent on Claim 1, but do not add any feature or subject matter that would solve the judicial exception deficiencies of Claim 1. For instance, Claims 6-15 recite further mental steps which can be practically performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper and thus, fail to make the claim any less abstract. See MPEP § 2106.04(a)(2)(III). And Claims 2-5 recite further additional elements that do not integrate the judicial exception into a practical application of the judicial exception and thus are not significantly more than the abstract idea. Specifically, the additional elements (a) recited in Claims 2-5 are recited at a high-level of generality such that they amount to no more than mere instructions to apply the judicial exception using generic computer components. See MPEP § 2106.05(f). Therefore, Claims 2-15 do not add any steps or additional elements, when considered both individually and as a combination, that would convert Claim 1 into patent-eligible subject matter.
Claims 1-15 are therefore not drawn to patent-eligible subject matter as they are directed to an abstract idea without significantly more.
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Claim Interpretation: Under the broadest reasonable interpretation (BRI), the limitations of Claim 16 are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. See MPEP § 2111.
Claim 16 recites:
The step of “receive the original code.” The claim does not impose any limits on how the original code is received;
The step of “translate the original code into translated code that includes an instruction including a first field indicating a first number of branches in the original code that are to be taken in the translated code when executed and including a second field indicating a second number of branches in the original code that are not to be taken in the translated code when executed.” The claim does not impose any limits on how the original code is translated; and
The step of “[…] execute instructions of the translated code.” The claim does not impose any limits on how the original code is translated.
In addition, these steps are recited as being performed by a system comprising memory and a processing system comprising an instruction converter and an execution unit. The memory, processing system, instruction converter, and execution unit are recited at a high level of generality, i.e., as generic computer components performing generic computer functions.
Step 1: Claim 16 is directed to a system, which is a machine and/or manufacture, and falls within one of the statutory categories of invention.
Step 2A, Prong One: Claim 16 recites the limitation:
(a) translate the original code into translated code that includes an instruction including a first field indicating a first number of branches in the original code that are to be taken in the translated code when executed and including a second field indicating a second number of branches in the original code that are not to be taken in the translated code when executed.
The recited step, under the broadest reasonable interpretation (BRI), covers performance of the step in the human mind alone or with the aid of pen and paper. That is, other than reciting:
(1) memory to store original code; and
(2) a processing system comprising:
(3) an instruction converter to; and
(4) an execution unit to […].
Nothing in the claim precludes the step from practically being performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper. For example, the limitation (a) in the context of the claim encompasses a human evaluating the original code using observation, evaluation, judgment, and opinion to translate the original code into translated code. See MPEP § 2106.04(a)(2)(III).
If a claim limitation, under its broadest reasonable interpretation (BRI), covers performance of the limitation in the human mind alone or with the aid of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A, Prong Two: This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements:
(1) memory to store original code; and
(2) a processing system comprising:
(3) an instruction converter to; and
(4) an execution unit to […].
The additional elements (1) to (4) are recited at a high-level of generality such that they amount to no more than mere instructions to apply the judicial exception using generic computer components. The memory, processing system, instruction converter, and execution unit are used as tools to perform the receiving and translating steps of the claim. See MPEP § 2106.05(f).
Also, the claim recites the additional element:
(5) receive the original code.
The additional element (5) is mere data gathering recited at a high level of generality, and thus is an insignificant extra-solution activity. See MPEP § 2106.05(g). Furthermore, all uses of the recited judicial exception require such data gathering, and, as such, the additional element does not impose any meaningful limits on the claim. The additional element amounts to necessary data gathering. See MPEP § 2106.05.
Also, the claim recites the additional element:
(6) […] execute instructions of the translated code.
The additional element (6) fails to meaningfully limit the claim because it does not require any particular application of the judicial exception and is, at best, the equivalent of merely adding the words “apply it” (or an equivalent) to the judicial exception. See MPEP § 2106.05(f). The additional element recites only the idea of executing the instructions of the translated code without details on how this is accomplished. The claim omits any details as to how the execution of the instructions of the translated code solves a technical problem, and instead recites only the idea of a solution or outcome. Therefore, the additional element attempts to cover any solution to the identified problem of executing the instructions of the translated code with no restriction on how the execution is accomplished and no description of the mechanism for accomplishing the execution, and does not integrate a judicial exception into a practical application because this type of recitation is equivalent to the words “apply it.”
Accordingly, even when viewed in combination, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as a combination do not amount to significantly more than the abstract idea. As discussed hereinabove with respect to integration of the abstract idea into a practical application, the claim recites the additional elements:
(1) memory to store original code; and
(2) a processing system comprising:
(3) an instruction converter to; and
(4) an execution unit to […].
The additional elements (1) to (4) amount to no more than mere instructions to apply the judicial exception using generic computer components. Mere instructions to apply a judicial exception using generic computer components cannot provide an inventive concept.
Also, the claim recites the additional element:
(5) receive the original code.
The additional element (5) simply appends a well-understood, routine, and conventional activity previously known to the industry, specified at a high level of generality, to the judicial exception is not indicative of an inventive concept. MPEP § 2106.05(d)(II) expressly states that the courts have recognized the computer functions of storing and retrieving information in memory and receiving or transmitting data over a network, e.g., using the Internet to gather data as well‐understood, routine, and conventional computer functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as an insignificant extra-solution activity. Thus, a person of ordinary skill in the art would readily comprehend that it is well-understood, routine, and conventional in the computing art to receive portions of computer program code. Therefore, the additional element remains an insignificant extra-solution activity even upon reconsideration and does not amount to significantly more.
Also, the claim recites the additional element:
(6) […] execute instructions of the translated code.
The additional element (6) does not require any particular application of the judicial exception and is, at best, the equivalent of merely adding the words “apply it” (or an equivalent) to the judicial exception. The analysis under Step 2A, Prong Two is carried through to Step 2B. Therefore, the additional element attempts to cover any solution to the identified problem of executing the instructions of the translated code with no restriction on how the execution is accomplished and no description of the mechanism for accomplishing the execution, and does not provide significantly more because this type of recitation is equivalent to the words “apply it.”
Thus, taken alone, the additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the additional elements as a combination adds nothing that is not already present when looking at the additional elements taken individually. Even when considered in combination, the additional elements represent mere instructions to apply a judicial exception using generic computer components, an insignificant extra-solution activity, and only the idea of a solution or outcome, and therefore do not provide an inventive concept. The claim is not patent eligible.
Claims 17 and 18 are rejected under 35 U.S.C. 101 as directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more for at least the reasons stated hereinabove.
Claim 17 recites the limitation:
(a) wherein the second field comprises a history field that indicates an order of taken and untaken branches in the translated code.
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Claim 18 recites the limitation:
(a) wherein the history field comprises a bit vector where each bit of the bit vector corresponds to a respective branch, and a value of the bit indicates whether the respective branch is to be taken or is not to be taken in the translated code.
These claims are dependent on Claim 16, but do not add any feature or subject matter that would solve the judicial exception deficiencies of Claim 16. For instance, Claims 17 and 18 recite further mental steps which can be practically performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper and thus, fail to make the claim any less abstract. See MPEP § 2106.04(a)(2)(III). Therefore, Claims 17 and 18 do not add any steps or additional elements, when considered both individually and as a combination, that would convert Claim 16 into patent-eligible subject matter.
Claims 16-18 are therefore not drawn to patent-eligible subject matter as they are directed to an abstract idea without significantly more.
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Claim Interpretation: Under the broadest reasonable interpretation (BRI), the limitations of Claim 19 are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. See MPEP § 2111.
Claim 19 recites:
The step of “receiving, at an instruction converter of a processor, original code comprising a plurality of instructions.” The claim does not impose any limits on how the original code is received;
The step of “translating, using the instruction converter of the processor, the original code into translated code including an instruction that includes a first field indicating a number of branches in the original code taken in the translated code and a second field indicating a number of branches in the original code not taken in the translated code, wherein translating comprises optimizing the translated code to run more efficiently by the processor than when not optimized.” Regarding the limitation “optimizing the translated code,” the claim does not limit the plain meaning of “optimizing,” which, as disclosed in the specification, includes removing or altering the original code to generate the translated code (paragraph [0002]). Furthermore, the claim does not impose any limits on how the original code is translated; and
The step of “executing or compiling the translated code […].” The claim does not impose any limits on how the translated code is executed or compiled.
In addition, these steps are recited as being performed by a system comprising memory and a processing system comprising an instruction converter and an execution unit. The memory, processing system, instruction converter, and execution unit are recited at a high level of generality, i.e., as generic computer components performing generic computer functions.
Step 1: Claim 19 is directed to a method, which is a process (a series of steps or acts), and falls within one of the statutory categories of invention.
Step 2A, Prong One: Claim 19 recites the limitations:
(a) translating […] the original code into translated code including an instruction that includes a first field indicating a number of branches in the original code taken in the translated code and a second field indicating a number of branches in the original code not taken in the translated code,
(b) wherein the translating comprises optimizing the translated code to run more efficiently […] than when not optimized.
The recited steps, under the broadest reasonable interpretation (BRI), cover performance of the steps in the human mind alone or with the aid of pen and paper. That is, other than reciting:
(1) at an instruction converter of a processor;
(2) using the instruction converter of the processor; and
(3) […] by the processor or a compiler, respectively.
Nothing in the claim precludes the steps from practically being performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper. For example, the limitation (a) in the context of the claim encompasses a human evaluating the original code using observation, evaluation, judgment, and opinion to translate the original code into translated code. And the limitation (b) in the context of the claim encompasses a human evaluating the translated code using observation, evaluation, judgment, and opinion to optimize (or remove/alter) the original code to generate the translated code. See MPEP § 2106.04(a)(2)(III).
If a claim limitation, under its broadest reasonable interpretation (BRI), covers performance of the limitation in the human mind alone or with the aid of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A, Prong Two: This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements:
(1) at an instruction converter of a processor;
(2) using the instruction converter of the processor; and
(3) […] by the processor or a compiler, respectively.
The additional elements (1) to (3) are recited at a high-level of generality such that they amount to no more than mere instructions to apply the judicial exception using generic computer components. The processor and the instruction converter of the processor are used as tools to perform the receiving, translating, and executing or compiling steps of the claim. See MPEP § 2106.05(f).
Also, the claim recites the additional element:
(4) receiving […] original code comprising a plurality of instructions.
The additional element (4) is mere data gathering recited at a high level of generality, and thus is an insignificant extra-solution activity. See MPEP § 2106.05(g). Furthermore, all uses of the recited judicial exception require such data gathering, and, as such, the additional element does not impose any meaningful limits on the claim. The additional element amounts to necessary data gathering. See MPEP § 2106.05.
Also, the claim recites the additional element:
(5) executing or compiling the translated code […].
The additional element (5) fails to meaningfully limit the claim because it does not require any particular application of the judicial exception and is, at best, the equivalent of merely adding the words “apply it” (or an equivalent) to the judicial exception. See MPEP § 2106.05(f). The additional element recites only the idea of executing or compiling the translated code without details on how this is accomplished. The claim omits any details as to how the execution or compilation of the translated code solves a technical problem, and instead recites only the idea of a solution or outcome. Therefore, the additional element attempts to cover any solution to the identified problem of executing or compiling the translated code with no restriction on how the execution or compilation is accomplished and no description of the mechanism for accomplishing the execution or compilation, and does not integrate a judicial exception into a practical application because this type of recitation is equivalent to the words “apply it.”
Accordingly, even when viewed in combination, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as a combination do not amount to significantly more than the abstract idea. As discussed hereinabove with respect to integration of the abstract idea into a practical application, the claim recites the additional elements:
(1) at an instruction converter of a processor;
(2) using the instruction converter of the processor; and
(3) […] by the processor or a compiler, respectively.
The additional elements (1) to (3) amount to no more than mere instructions to apply the judicial exception using generic computer components. Mere instructions to apply a judicial exception using generic computer components cannot provide an inventive concept.
Also, the claim recites the additional element:
(4) receiving […] original code comprising a plurality of instructions.
The additional element (4) simply appends a well-understood, routine, and conventional activity previously known to the industry, specified at a high level of generality, to the judicial exception is not indicative of an inventive concept. MPEP § 2106.05(d)(II) expressly states that the courts have recognized the computer functions of storing and retrieving information in memory and receiving or transmitting data over a network, e.g., using the Internet to gather data as well‐understood, routine, and conventional computer functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as an insignificant extra-solution activity. Thus, a person of ordinary skill in the art would readily comprehend that it is well-understood, routine, and conventional in the computing art to receive portions of computer program code. Therefore, the additional element remains an insignificant extra-solution activity even upon reconsideration and does not amount to significantly more.
Also, the claim recites the additional element:
(5) executing or compiling the translated code […].
The additional element (5) does not require any particular application of the judicial exception and is, at best, the equivalent of merely adding the words “apply it” (or an equivalent) to the judicial exception. The analysis under Step 2A, Prong Two is carried through to Step 2B. Therefore, the additional element attempts to cover any solution to the identified problem of executing or compiling the translated code with no restriction on how the execution or compilation is accomplished and no description of the mechanism for accomplishing the execution or compilation, and does not provide significantly more because this type of recitation is equivalent to the words “apply it.”
Thus, taken alone, the additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the additional elements as a combination adds nothing that is not already present when looking at the additional elements taken individually. Even when considered in combination, the additional elements represent mere instructions to apply a judicial exception using generic computer components, an insignificant extra-solution activity, and only the idea of a solution or outcome, and therefore do not provide an inventive concept. The claim is not patent eligible.
Claims 20 and 21 are rejected under 35 U.S.C. 101 as directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more for at least the reasons stated hereinabove.
Claim 20 recites the limitation:
(a) utilizing a performance monitor to monitor performance of execution of the translated code using an instruction to emulate execution of the original code rather than the translated code.
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Claim 21 recites the limitation:
(a) wherein the performance monitor comprises one of performance monitoring (perfmon), processor trace (PT), or last branch record (LBR) performance monitoring.
These claims are dependent on Claim 19, but do not add any feature or subject matter that would solve the judicial exception deficiencies of Claim 19. For instance, Claims 20 and 21 fail to meaningfully limit the claim because it does not require any particular application of the judicial exception and is, at best, the equivalent of merely adding the words “apply it” (or an equivalent) to the judicial exception. See MPEP § 2106.05(f). Therefore, Claims 20 and 21 do not add any steps or additional elements, when considered both individually and as a combination, that would convert Claim 19 into patent-eligible subject matter.
Claims 19-21 are therefore not drawn to patent-eligible subject matter as they are directed to an abstract idea without significantly more.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, and 5 are rejected under 35 U.S.C. 103 as being unpatentable over US 2006/0070050 (hereinafter “Chen01”) in view of US 2002/0032718 (hereinafter “Yates”).
As per Claim 1, Chen01 discloses:
A system (Figure 3) comprising:
memory (Figure 3: 152) to store instructions; and
a processor (Figure 3: 150) comprising an instruction converter to:
receive the stored instructions (paragraph [0018], “The method requires the use of a worklist that points to a first plurality of stored instructions in the extended SSA form (emphasis added).”; paragraph [0063], “The method begins, as illustrated in block 700, where an initial plurality of instructions in the extended SSA form are received by the compiler, block 702 (emphasis added).”); and
translate the stored instructions into translated code that includes one or more numbered instructions that include a field (Figures 4, 9A, and 9B; paragraph [0034], “FIG. 4 illustrates a graphical representation of an instruction 170, in accordance with one embodiment. The instruction includes the two elements of the instruction, S1 172 and S2 174. Although the previous link field 176 is added, as well as the write mask 178 [one or more numbered instructions that include a field].”; paragraph [0069], “Returning to block 714 of FIG. 7A, the method translates the first plurality of instructions into a second plurality of instructions in the extended SSA form by updating sources and previous links (emphasis added).”; paragraph [0077], “FIG. 9A illustrates a graphical representation of a series of instructions 902-914 representing, in one embodiment, a first plurality of instructions in the extended SSA form. Each instruction is numbered ‘0’ through ‘6’ using the nomenclature ‘I0’ through ‘I6.’ Similarly, FIG. 9B illustrates a graphical representation of a series of instruction 902-904, 908, 916-924 representing, in one embodiment, a second plurality of instructions in the extended SSA form as translated from the instructions of FIG. 9A (emphasis added).”).
Chen01 discloses “one or more numbered instructions that include a field,” but Chen01 does not explicitly disclose:
a field indicating a number of branches in the stored instructions that are taken in the translated code.
However, Yates discloses:
a field indicating a number of branches in stored instructions that are taken in translated code (Figure 6; paragraph [0120], “After generation of native image code such as by the binary translator, the image translated code is stored on logical disk drive 17' in logical segment 17c' with the profile statistics being stored in logical segment 17d'. These locations correspond to segments 17c and 17d in FIG. 2 (emphasis added).”; paragraph [0141], “There are additional optional fields 70 which comprise the record. One field is a count field 70a which corresponds to either the number of times a control transfer occurred to the address contained in field 66a or a count branch taken field counter which keeps track of the number of times a branch was taken by the instruction corresponding to the address contained in field 66a (emphasis added).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Yates into the teaching of Chen01 to include “a field indicating a number of branches in the stored instructions that are taken in the translated code.” The modification would be obvious because one of ordinary skill in the art would be motivated to keep track or maintain a count of the number of times a conditional control transfer of a branch instruction was taken (Yates, paragraph [0142]).
As per Claim 2, the rejection of Claim 1 is incorporated; and Chen01 does not explicitly disclose:
a binary translation processor to execute the translated code.
However, Yates discloses:
a binary translation processor to execute translated code (paragraph [0117], “[…] the background system can make translated code available to the run-time system 32 during execution to permit substitution of translated code for a subsequent occurrence of the non-native image during the current execution of the application program.”; paragraph [0118], “A preferred arrangement is to have the background system implemented as a binary translator to produce translated code.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Yates into the teaching of Chen01 to include “a binary translation processor to execute the translated code.” The modification would be obvious because one of ordinary skill in the art would be motivated to perform dynamic translation and optimization of machine code or bytecode.
As per Claim 4, the rejection of Claim 1 is incorporated; and Chen01 further discloses:
wherein the instruction converter is implemented using software executed by an execution unit of the processor (paragraph [0031], “[…] the processor 150 performs compiler operations to convert programming language instructions into machine language instructions.”).
As per Claim 5, the rejection of Claim 1 is incorporated; and Chen01 further discloses:
wherein the processor further comprises hardware circuitry that implements the instruction converter (paragraph [0030], “The processor 150 may be, but not limited to, a single processor, a plurality of processors, a DSP, a microprocessor, an ASIC, a state machine, or any implementation capable of processing and executing software.”).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen01 in view of Yates as applied to Claim 1 above, and further in view of US 2015/0007153 (hereinafter “Martinez”).
As per Claim 3, the rejection of Claim 1 is incorporated; and Chen01 discloses “translated code,” but the combination of Chen01 and Yates does not explicitly disclose:
a just-in-time compiler to compile the translated code.
However, Martinez discloses:
a just-in-time compiler to compile code (paragraph [0002], “[…] a dynamic binary translator, Just In Time (JIT) compiler or virtual machine can perform dynamic translation and optimization of machine code or bytecode (a type of machine code intended to be recompiled by a JIT), which can be cached for later use.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Martinez into the combined teachings of Chen01 and Yates to include “a just-in-time compiler to compile the translated code.” The modification would be obvious because one of ordinary skill in the art would be motivated to perform dynamic translation and optimization of machine code or bytecode.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen01 in view of Yates as applied to Claim 1 above, and further in view of US 2004/0034777 (hereinafter “Murray”).
As per Claim 6, the rejection of Claim 1 is incorporated; and Chen01 discloses “translated code,” but the combination of Chen01 and Yates does not explicitly disclose:
wherein translating the stored instructions into the translated code comprises optimizing the translated code to be execute more efficiently by the processor than without optimization.
However, Murray discloses:
wherein translating stored instructions into translated code comprises optimizing code to be execute more efficiently by a processor than without optimization (paragraph [0016], “Generally, compilers optimize code by using techniques such as constant propagation (replacing expressions that evaluate to a constant with a constant value), copy propagation (replacing assignment by the assigned value) strength reduction (replacing operations by more efficient operations), loop unrolling (replace loop with code), and so on.”; paragraph [0017], “Modern compliers make many choices of methods to optimize code as they are compiling it. A method of watermarking code can be executed by changing the choice of optimizations that the compiler makes.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Murray into the combined teachings of Chen01 and Yates to include “wherein translating the stored instructions into the translated code comprises optimizing the translated code to be execute more efficiently by the processor than without optimization.” The modification would be obvious because one of ordinary skill in the art would be motivated to generate more efficient and often smaller machine code, resulting in better performance, code size, and debugging.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen01 in view of Yates and Murray as applied to Claim 6 above, and further in view of US 2022/0206768 (hereinafter “Chen02”).
As per Claim 7, the rejection of Claim 6 is incorporated; and Chen01 discloses “a number of branches indicated in a field,” but the combination of Chen01, Yates, and Murray does not explicitly disclose:
wherein the optimization comprises loop unrolling looped instructions a number of times equal to the number of branches indicated in the field.
However, Chen02 discloses:
wherein an optimization comprises loop unrolling looped instructions a number of times equal to a number of branches (paragraph [0048], “[…] the optimization module 320 can perform the optimization processing on the loop instruction to translate it into the corresponding machine code to perform the following operations: analyzing the number of the loops for the loop instruction; and unrolling all the instructions executed in the loop instruction according to the number of the loops.” and “In order to reduce the number of the instructions required by the branch instructions, the loop unrolling method is used in the present embodiment to unroll all instructions in the loop instruction by the number of the loops thereof on the condition of available resources, so as to reduce the proportion of the branch instructions in the loop instruction during execution.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Chen02 into the combined teachings of Chen01, Yates, and Murray to include “wherein the optimization comprises loop unrolling looped instructions a number of times equal to the number of branches indicated in the field.” The modification would be obvious because one of ordinary skill in the art would be motivated to reduce a number of instructions required by branch instructions (Chen02, paragraph [0048]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over US 2006/0070050 (hereinafter “Chen01”) in view of US 2002/0032718 (hereinafter “Yates”) and US 2018/0341504 (hereinafter “Kissell”).
As per Claim 16, Chen01 discloses:
A system (Figure 3) comprising:
memory (Figure 3: 152) to store original code; and
a processing system (Figure 3: 150) comprising:
an instruction converter to:
receive the original code (paragraph [0063], “The method begins, as illustrated in block 700, where an initial plurality of instructions in the extended SSA form are received by the compiler, block 702 (emphasis added).”); and
translate the original code into translated code that includes an instruction including a first field and including a second field (Figure 4; paragraph [0034], “FIG. 4 illustrates a graphical representation of an instruction 170, in accordance with one embodiment. The instruction includes the two elements of the instruction, S1 172 and S2 174. Although the previous link field 176 is added, as well as the write mask 178 [an instruction including a first field and including a second field].”; paragraph [0069], “Returning to block 714 of FIG. 7A, the method translates the first plurality of instructions into a second plurality of instructions in the extended SSA form by updating sources and previous links (emphasis added).”); and
an execution unit to execute instructions of the translated code (paragraph [0031], “The executable instructions 154 are provided to the processor 150 such that the processor 150 performs operations in response thereto.”).
Chen01 discloses “an instruction including a first field and including a second field,” but Chen01 does not explicitly disclose:
a first field indicating a first number of branches in the original code that are to be taken in the translated code when executed.
However, Yates discloses:
a first field indicating a first number of branches in original code that are to be taken in translated code when executed (Figure 6; paragraph [0120], “After generation of native image code such as by the binary translator, the image translated code is stored on logical disk drive 17' in logical segment 17c' with the profile statistics being stored in logical segment 17d'. These locations correspond to segments 17c and 17d in FIG. 2 (emphasis added).”; paragraph [0141], “There are additional optional fields 70 which comprise the record. One field is a count field 70a which corresponds to either the number of times a control transfer occurred to the address contained in field 66a or a count branch taken field counter which keeps track of the number of times a branch was taken by the instruction corresponding to the address contained in field 66a (emphasis added).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Yates into the teaching of Chen01 to include “a first field indicating a first number of branches in the original code that are to be taken in the translated code when executed.” The modification would be obvious because one of ordinary skill in the art would be motivated to keep track or maintain a count of the number of times a conditional control transfer of a branch instruction was taken (Yates, paragraph [0142]).
The combination of Chen01 and Yates discloses “a second field,” but the combination of Chen01 and Yates does not explicitly disclose:
a second field indicating a second number of branches in the original code that are not to be taken in the translated code when executed.
However, Kissell discloses:
a second field indicating a second number of branches in original code that are not to be taken in translated code when executed (paragraph [0046], “Referring to FIG. 4, the virtual machine coprocessor 130 translates abstract machine instructions 110 to native machine instructions that may be fetched and executed by processor 120 (emphasis added).”; page 11, Claim 27: “[…] a branch taken field indicating a successive basic block if a branch is taken; a branch not taken field indicating a successive basic block if a branch is not taken; and a branch counter field indicating either the number of times a branch is taken or the number of times a branch is not taken (emphasis added).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kissell into the combined teachings of Chen01 and Yates to include “a second field indicating a second number of branches in the original code that are not to be taken in the translated code when executed.” The modification would be obvious because one of ordinary skill in the art would be motivated to keep track or maintain a count of the number of times a conditional control transfer of a branch instruction was not taken (Yates, paragraph [0142]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chen01 in view of Yates and Kissell as applied to Claim 16 above, and further in view of US 2003/0041230 (hereinafter “Rappoport”).
As per Claim 17, the rejection of Claim 16 is incorporated; and Chen01 discloses “translated code,” but the combination of Chen01, Yates, and Kissell does not explicitly disclose:
wherein the second field comprises a history field that indicates an order of taken and untaken branches in the translated code.
However, Rappoport discloses:
wherein a second field comprises a history field that indicates an order of taken and untaken branches in code (paragraph [0046], “[…] a two bit history field 171-174, for predicting whether or not a conditional branch will be taken. BTB line 111 has a 5 bit LRU counter 176 (similar to LRU counter 125 used with ITB 120, FIG. 3) for recording the order in which each of the four ways 151-154 has been accessed and for evicting entries.”; paragraph [0047], “[…] the history field is a two bit saturated counter which is incremented each time the corresponding branch is taken and decremented each time the corresponding branch is not taken.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Rappoport into the combined teachings of Chen01, Yates, and Kissell to include “wherein the second field comprises a history field that indicates an order of taken and untaken branches in the translated code.” The modification would be obvious because one of ordinary skill in the art would be motivated to record a history for all branches in code (Rappoport, paragraph [0009]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Chen01 in view of Yates, Kissell, and Rappoport as applied to Claim 17 above, and further in view of US 2016/0139932 (hereinafter “Carlson”).
As per Claim 18, the rejection of Claim 17 is incorporated; and Chen01 discloses “translated code,” but the combination of Chen01, Yates, Kissell, and Rappoport does not explicitly disclose:
wherein the history field comprises a bit vector where each bit of the bit vector corresponds to a respective branch, and a value of the bit indicates whether the respective branch is to be taken or is not to be taken in the translated code.
However, Carlson discloses:
wherein a history field comprises a bit vector where each bit of the bit vector corresponds to a respective branch, and a value of the bit indicates whether the respective branch is to be taken or is not to be taken in code (paragraph [0059], “Global history storage 300 (e.g., shift registers) stores branch history information in the form of two versions of a global history (GH) bit vector representing a past history of branch results from the most recent series of branch instructions.”; paragraph [0061], “[…] the branch prediction state information may include a 2-bit value of a bimodal predictor, such as the 2-bit saturating counter described below with reference to FIG. 4. States ‘10’ or ‘11’ indicate the branch should be predicted taken, and states ‘00’ or ‘01’ indicate the branch should be predicted not taken.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Carlson into the combined teachings of Chen01, Yates, Kissell, and Rappoport to include “wherein the history field comprises a bit vector where each bit of the bit vector corresponds to a respective branch, and a value of the bit indicates whether the respective branch is to be taken or is not to be taken in the translated code.” The modification would be obvious because one of ordinary skill in the art would be motivated to represent a past history of branch results from the most recent series of branch instructions (Carlson, paragraph [0059]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over US 2006/0070050 (hereinafter “Chen01”) in view of US 2002/0032718 (hereinafter “Yates”), US 2018/0341504 (hereinafter “Kissell”), and US 2004/0034777 (hereinafter “Murray”).
As per Claim 19, Chen01 discloses:
A method (paragraph [0018], “[…] a method is disclosed for reducing instruction dependencies in the extended static single assignment (SSA) form in which the instructions are converted from instructions that utilize superword registers.”) comprising:
receiving, at an instruction converter of a processor (Figure 3: 150), original code comprising a plurality of instructions (paragraph [0063], “The method begins, as illustrated in block 700, where an initial plurality of instructions in the extended SSA form are received by the compiler, block 702 (emphasis added).”);
translating, using the instruction converter of the processor (Figure 3: 150), the original code into translated code including an instruction that includes a first field and a second field (Figure 4; paragraph [0034], “FIG. 4 illustrates a graphical representation of an instruction 170, in accordance with one embodiment. The instruction includes the two elements of the instruction, S1 172 and S2 174. Although the previous link field 176 is added, as well as the write mask 178 [an instruction that includes a first field and a second field].”; paragraph [0069], “Returning to block 714 of FIG. 7A, the method translates the first plurality of instructions into a second plurality of instructions in the extended SSA form by updating sources and previous links (emphasis added).”); and
executing or compiling the translated code by the processor or a compiler, respectively (paragraph [0031], “The executable instructions 154 are provided to the processor 150 such that the processor 150 performs operations in response thereto.”).
Chen01 discloses “an instruction that includes a first field and a second field,” but Chen01 does not explicitly disclose:
a first field indicating a number of branches in the original code taken in the translated code.
However, Yates discloses:
a first field indicating a number of branches in original code taken in translated code (Figure 6; paragraph [0120], “After generation of native image code such as by the binary translator, the image translated code is stored on logical disk drive 17' in logical segment 17c' with the profile statistics being stored in logical segment 17d'. These locations correspond to segments 17c and 17d in FIG. 2 (emphasis added).”; paragraph [0141], “There are additional optional fields 70 which comprise the record. One field is a count field 70a which corresponds to either the number of times a control transfer occurred to the address contained in field 66a or a count branch taken field counter which keeps track of the number of times a branch was taken by the instruction corresponding to the address contained in field 66a (emphasis added).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Yates into the teaching of Chen01 to include “a first field indicating a number of branches in the original code taken in the translated code.” The modification would be obvious because one of ordinary skill in the art would be motivated to keep track or maintain a count of the number of times a conditional control transfer of a branch instruction was taken (Yates, paragraph [0142]).
The combination of Chen01 and Yates discloses “a second field,” but the combination of Chen01 and Yates does not explicitly disclose:
a second field indicating a number of branches in the original code not taken in the translated code.
However, Kissell discloses:
a second field indicating a number of branches in original code not taken in translated code (paragraph [0046], “Referring to FIG. 4, the virtual machine coprocessor 130 translates abstract machine instructions 110 to native machine instructions that may be fetched and executed by processor 120 (emphasis added).”; page 11, Claim 27: “[…] a branch taken field indicating a successive basic block if a branch is taken; a branch not taken field indicating a successive basic block if a branch is not taken; and a branch counter field indicating either the number of times a branch is taken or the number of times a branch is not taken (emphasis added).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kissell into the combined teachings of Chen01 and Yates to include “a second field indicating a number of branches in the original code not taken in the translated code.” The modification would be obvious because one of ordinary skill in the art would be motivated to keep track or maintain a count of the number of times a conditional control transfer of a branch instruction was not taken (Yates, paragraph [0142]).
Chen01 discloses “translated code,” but the combination of Chen01, Yates, and Kissell does not explicitly disclose:
wherein the translating comprises optimizing the translated code to run more efficiently by the processor than when not optimized.
However, Murray discloses:
optimizing code to run more efficiently by a processor than when not optimized (paragraph [0016], “Generally, compilers optimize code by using techniques such as constant propagation (replacing expressions that evaluate to a constant with a constant value), copy propagation (replacing assignment by the assigned value) strength reduction (replacing operations by more efficient operations), loop unrolling (replace loop with code), and so on [optimizing code to run more efficiently by a processor than when not optimized].”; paragraph [0017], “Modern compliers make many choices of methods to optimize code as they are compiling it. A method of watermarking code can be executed by changing the choice of optimizations that the compiler makes (emphasis added).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Murray into the combined teachings of Chen01, Yates, and Kissell to include “wherein the translating comprises optimizing the translated code to run more efficiently by the processor than when not optimized.” The modification would be obvious because one of ordinary skill in the art would be motivated to generate more efficient and often smaller machine code, resulting in better performance, code size, and debugging.
Claims 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Chen01 in view of Yates, Kissell, and Murray as applied to Claim 19 above, and further in view of US 2017/0192791 (hereinafter “Ould-Ahmed-Vall”).
As per Claim 20, the rejection of Claim 19 is incorporated; and Chen01 discloses “translated code,” but the combination of Chen01, Yates, Kissell, and Murray does not explicitly disclose:
utilizing a performance monitor to monitor performance of execution of the translated code using an instruction to emulate execution of the original code rather than the translated code.
However, Ould-Ahmed-Vall discloses:
utilizing a performance monitor to monitor performance of execution of code using an instruction to emulate execution of original code rather than the code (paragraph [0026], “Performance monitoring circuitry 103 (sometimes called ‘perfmon’) monitors functions of the core such as execution cycles, power state, etc. Embodiments of performance monitoring circuitry 103 include an address conflict counter 105 to count instances of address conflicts between instructions in a grouping of instructions.”; paragraph [0098], “In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Ould-Ahmed-Vall into the combined teachings of Chen01, Yates, Kissell, and Murray to include “utilizing a performance monitor to monitor performance of execution of the translated code using an instruction to emulate execution of the original code rather than the translated code.” The modification would be obvious because one of ordinary skill in the art would be motivated to monitor functions of a core such as execution cycles, power state, etc. (Ould-Ahmed-Vall, paragraph [0026]).
As per Claim 21, the rejection of Claim 20 is incorporated; and the combination of Chen01, Yates, Kissell, and Murray does not explicitly disclose:
wherein the performance monitor comprises one of performance monitoring (perfmon), processor trace (PT), or last branch record (LBR) performance monitoring.
However, Ould-Ahmed-Vall discloses:
wherein a performance monitor comprises one of performance monitoring (perfmon), processor trace (PT), or last branch record (LBR) performance monitoring (paragraph [0026], “Performance monitoring circuitry 103 (sometimes called ‘perfmon’) monitors functions of the core such as execution cycles, power state, etc. Embodiments of performance monitoring circuitry 103 include an address conflict counter 105 to count instances of address conflicts between instructions in a grouping of instructions.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Ould-Ahmed-Vall into the combined teachings of Chen01, Yates, Kissell, and Murray to include “wherein the performance monitor comprises one of performance monitoring (perfmon), processor trace (PT), or last branch record (LBR) performance monitoring.” The modification would be obvious because one of ordinary skill in the art would be motivated to monitor functions of a core such as execution cycles, power state, etc. (Ould-Ahmed-Vall, paragraph [0026]).
Allowable Subject Matter
Claims 8-15 are objected to as being dependent upon a rejected base claim under 35 U.S.C. § 103, but would be allowable over the cited prior art if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and overcome any corresponding objections and/or rejections set forth hereinabove.
Response to Arguments
Applicant’s arguments submitted on January 16, 2026 have been fully considered, but they are not persuasive.
In the Remarks, the Applicant argues:
Mr. Kim noted that “[i]n computer-related technologies, examiners can conclude that claims are eligible in Step 2A Prong Two by finding that a claim reflects an improvement to the functioning of a computer or to another technology or technical field, integrating a recited judicial exception into a practical application of the exception.” He further noted that “[t]he examiner is reminded to consult the specification to determine whether the disclosed invention improves technology or a technical field, and evaluate the claim to ensure it reflects the disclosed improvement. The specification does not need to explicitly set forth the improvement, but it must describe the invention such that the improvement would be apparent to one of ordinary skill in the art. The claim itself does not need to explicitly recite the improvement described in the specification.”
This aligns with MPEP 2106.04(d)(1) that “[a] claim reciting a judicial exception is not directed to the judicial exception if it also recites additional elements demonstrating that the claim as a whole integrates the exception into a practical application. One way to demonstrate such integration is when the claimed invention improves the functioning of a computer or improves another technology or technical field.”
[…]
At least paragraphs [0025]-[0027] describe aspects of previous support for translation and potential issues. These issues are addressed, for example, using the new instructions BRNOP or ASSERT (see, e.g., paragraphs [0029]-[0031]). As such, the claims are clearly directed toward “an improvement in the functioning of a computer.”
(See Remarks – pages 5 and 6.)
Examiner’s response:
Examiner disagrees. With respect to the Applicant’s assertion that “Mr. Kim noted that ‘[i]n computer-related technologies, examiners can conclude that claims are eligible in Step 2A Prong Two by finding that a claim reflects an improvement to the functioning of a computer or to another technology or technical field, integrating a recited judicial exception into a practical application of the exception.’ He further noted that ‘[t]he examiner is reminded to consult the specification to determine whether the disclosed invention improves technology or a technical field, and evaluate the claim to ensure it reflects the disclosed improvement. The specification does not need to explicitly set forth the improvement, but it must describe the invention such that the improvement would be apparent to one of ordinary skill in the art. The claim itself does not need to explicitly recite the improvement described in the specification,’” the Examiner respectfully submits that the Examiner assessed the claims in accordance with Deputy Commissioner for Patents Charles Kim’s memorandum dated August 4, 2025. Specifically, Mr. Kim noted that “[t]he examiner is reminded to consult the specification to determine whether the disclosed invention improves technology or a technical field, and evaluate the claim to ensure it reflects the disclosed improvement” (emphasis added). Examiner concluded that the claims do not reflect the disclosed improvement. As pointed out in the Examiner’s response (a) in the Non-Final Rejection (sent on 10/16/2025), in accordance with MPEP § 2106.05(a), “[a]fter the examiner has consulted the specification and determined that the disclosed invention improves technology, the claim must be evaluated to ensure the claim itself reflects the disclosed improvement in technology. Intellectual Ventures I LLC v. Symantec Corp., 838 F.3d 1307, 1316, 120 USPQ2d 1353, 1359 (Fed. Cir. 2016) (patent owner argued that the claimed email filtering system improved technology by shrinking the protection gap and mooting the volume problem, but the court disagreed because the claims themselves did not have any limitations that addressed these issues). That is, the claim must include the components or steps of the invention that provide the improvement described in the specification (emphasis added).” And “[d]uring examination, the examiner should analyze the ‘improvements’ consideration by evaluating the specification and the claims to ensure that a technical explanation of the asserted improvement is present in the specification, and that the claim reflects the asserted improvement (emphasis added).” An as example, Claim 1, in its present form, does not recite any components nor steps that provide the improvement described in the specification. In particular, Claim 1 does not recite limitations pertaining to the asserted improvement of “new instructions may be used to combine several BRNOP or ASSERT instructions into a single instruction. These new instructions may meet the monitoring requirements while reducing the use of the pipeline resources. For instance, a Branch Not-an-Operation N (BRNOPN) instruction may combine multiple BRNOPs into a single instruction where ‘N’ is the number of BRNOPs combined.” Claim 1 only broadly recites translating stored instructions into translated code without any recitations of the asserted improvement.
Therefore, for at least the reason set forth above, the rejections made under 35 U.S.C. § 101 with respect to Claims 1-21 are proper and therefore, maintained.
In the Remarks, the Applicant argues:
Applicant further notes that in Ex parte Desjardins et al., Director Squires noted that “claims directed to an improvement in the functioning of a computer, or an improvement to other technology or technical field are patent eligible.” He further noted that “the Federal Circuit held that the eligibility determination should turn on whether “[sic] the claims are directed to an improvement to computer functionality versus being directed to an abstract idea.”
Ex parte Desjardins also noted that the Office tends to “evaluate claims at … a high level of generality” which this Office Action does by saying that everything is simply a mental process or mathematical concept without doing the evaluation required by the MPEP (such as the evaluation described in MPEP 2106.04(d)(1)).
(See Remarks – page 6, emphasis in original.)
Examiner’s response:
Examiner disagrees. With respect to the Applicant’s assertion that “[…] in Ex parte Desjardins et al., Director Squires noted that ‘claims directed to an improvement in the functioning of a computer, or an improvement to other technology or technical field are patent eligible.’ He further noted that ‘the Federal Circuit held that the eligibility determination should turn on whether ‘[sic] the claims are directed to an improvement to computer functionality versus being directed to an abstract idea,’” the Examiner respectfully submits that, regarding Ex Parte Desjardins, Director Squires’ decision contained more of a general guidance for the examination of artificial intelligence (AI)-related patent applications based on § 101 subject matter eligibility. The decision pointed to disclosures in the patent application at issue indicating memory savings and “reduced system complexity” related to the claimed subject matter. The decision analogized to Enfish, which held that claims directed to “an improvement to computer functionality” could be patent eligible. In contrast, to the best of the Examiner’s understanding of the disclosed invention, no AI or machine learning technology of any kind is involved in the Applicant’s invention. Thus, Director Squires’ decision in Ex Parte Desjardins should have no precedential effect on the claims of the instant application because it is not an AI-related invention.
Therefore, for at least the reason set forth above, the rejections made under 35 U.S.C. § 101 with respect to Claims 1-21 are proper and therefore, maintained.
In the Remarks, the Applicant argues:
For example, the combination does not at least describe “a processor comprising an instruction converter to: translate the stored instructions into translated code that includes one or more numbered instructions that include a field indicating a number of branches in the stored instructions that are taken in the translated code.” The combination does not describe an instruction converter to translate code that includes numbered instructions. The Office Action cites Chen01 for this aspect and points to FIG. 9. As noted in the quote from the Office Action for this figure, “FIG. 9A illustrates a graphical representation of a series of instructions 902-914 representing, in one embodiment, a first plurality of instructions in the extended SSA form.” There is no discussion in Chen01 that those numbers (which include the letter I which clearly is not something required, but used to distinguish a number from an instruction in the figure, and not [sic] also not a number) are generated by an instruction converter. They appear to merely be there for the graphical representation. Compare that with the discussion of Chen01 where a number is generated. Specifically, FIG. 7 describes the generation of “group ID numbers” which do not number instructions individually.
The combination does not describe an instruction converter to translate code that includes numbered instructions wherein one or more of the numbered instructions “include a field indicating a number of branches in the stored instructions that are taken in the translated code.” The Office Action admits that Chen01 does not describe instructions having a field that indicates the number of branches that are taken. Yates is cited for this aspect. The Office Action points to fields 70a and 66a which come from a “profile record structure” which is illustrated in FIG. 6. Obviously, a profile record is not an instruction, but rather a structure that “maintains information about run-time execution of control transfer instructions in the non-native image” that is not at all tied to an instruction. Further, Yates actually describes an instruction in FIG. 7 and Yates does not describe an instruction with information from the profile record structure. As such, Yates does not describe an instruction field to indicate a number of branches taken. While Chen01 describes instructions with fields there is no reason for one to combine Yates’ profile record with Chen01’s instructions.
(See Remarks – pages 7 and 8, emphasis in original.)
Examiner’s response:
Examiner disagrees. Applicant’s arguments are not persuasive for at least the following reasons:
First, with respect to the Applicant’s assertion that “[t]here is no discussion in Chen01 that those numbers (which include the letter I which clearly is not something required, but used to distinguish a number from an instruction in the figure, and not [sic] also not a number) are generated by an instruction converter,” the Examiner respectfully submits that Chen01 discloses “translate the stored instructions into translated code that includes one or more numbered instructions that include a field” (Figures 4, 9A, and 9B; paragraph [0034], “FIG. 4 illustrates a graphical representation of an instruction 170, in accordance with one embodiment. The instruction includes the two elements of the instruction, S1 172 and S2 174. Although the previous link field 176 is added, as well as the write mask 178 [one or more numbered instructions that include a field].”; paragraph [0069], “Returning to block 714 of FIG. 7A, the method translates the first plurality of instructions into a second plurality of instructions in the extended SSA form by updating sources and previous links (emphasis added).”; paragraph [0077], “FIG. 9A illustrates a graphical representation of a series of instructions 902-914 representing, in one embodiment, a first plurality of instructions in the extended SSA form. Each instruction is numbered ‘0’ through ‘6’ using the nomenclature ‘I0’ through ‘I6.’ Similarly, FIG. 9B illustrates a graphical representation of a series of instruction 902-904, 908, 916-924 representing, in one embodiment, a second plurality of instructions in the extended SSA form as translated from the instructions of FIG. 9A (emphasis added).”). Note that Figures 9A and 9B of Chen01 depict a first plurality of instructions in the extended SSA form that are translated into a second plurality of instructions in the extended SSA. Each instruction is numbered “0” through “6” using the nomenclature “I0” through “I6.” Thus, one of ordinary skill in the art would readily comprehend that the first and second plurality of instructions in the extended SSA are numbered instructions.
Second, with respect to the Applicant’s assertion that “[t]he combination does not describe an instruction converter to translate code that includes numbered instructions wherein one or more of the numbered instructions ‘include a field indicating a number of branches in the stored instructions that are taken in the translated code,’” the Examiner respectfully submits that Chen01 discloses “one or more numbered instructions that include a field,” but Chen01 does not explicitly disclose “a field indicating a number of branches in the stored instructions that are taken in the translated code.” Examiner relies upon Yates for its explicit teaching of “a field indicating a number of branches in stored instructions that are taken in translated code.” Examiner is not relying on Yates for teaching an instruction that includes a field. In response to the Applicant’s arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Third, with respect to the Applicant’s assertion that “[w]hile Chen01 describes instructions with fields there is no reason for one to combine Yates’ profile record with Chen01’s instructions,” the Examiner respectfully submits that, in response to the Applicant’s argument, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Furthermore, it is well-established that a determination of obviousness based on teachings from multiple references does not require an actual, physical substitution of elements. See In re Mouttet, 686 F.3d 1322, 1332, 103 USPQ2d 1219, 1226 (Fed. Cir. 2012) (citing In re Etter, 756 F.2d 852, 859, 225 USPQ 1, 6 (Fed. Cir. 1985) (en banc)). Chen01 discloses an instruction that includes various fields. And Yates discloses a profile record structure (i.e., a data structure) that includes various fields. The proposed modification or combination of the prior art does not involve modifying or substituting Chen01’s instruction with Yates’ profile record structure. Instead, in view of Chen01’s and Yates’ teachings, one of ordinary skill in the art would readily recognize that Chen01’s instruction could be modified to include an additional field for indicating a number of branches in stored instructions that are taken in translated code. Such proposed modification would still render Chen01’s instruction to operate as intended because including an additional instruction field would not change the principle of operation of Chen01’s instruction.
Therefore, for at least the reasons set forth above, the rejections made under 35 U.S.C. § 103 with respect to Claims 1-7 and 16-21 are proper and therefore, maintained.
In the Remarks, the Applicant argues:
For example, the combination does not at least describe “an instruction converter to translate the original code into translated code that includes an instruction including a first field indicating a first number of branches in the original code that are to be taken in the translated code when executed and including a second field indicating a second number of branches in the original code that are not to be taken in the translated code when executed.” As noted above, Chen01 and Yates doe [sic] not describe instructions that include a number of branches taken. Kissell does not changes this calculus. Kissell is cited as allegedly describing the second field. The claim from Kissell that the Office Action cites is for a “data record” (see dependency on claim 26) which is not an instruction.
(See Remarks – pages 8 and 9.)
Examiner’s response:
Examiner disagrees. With respect to the Applicant’s assertion that “Chen01 and Yates doe [sic] not describe instructions that include a number of branches taken. Kissell does not changes this calculus. Kissell is cited as allegedly describing the second field. The claim from Kissell that the Office Action cites is for a ‘data record’ (see dependency on claim 26) which is not an instruction,” the Examiner respectfully submits that the Examiner has addressed the Applicant’s arguments with respect to Chen01 and Yates in the Examiner’s response (c) hereinabove. Furthermore, Kissell discloses a data record (i.e., a data structure) that includes various fields. The proposed modification or combination of the prior art does not involve modifying or substituting Chen01’s instruction with Kissell’s data record. Instead, in view of Chen01’s and Kissell’s teachings, one of ordinary skill in the art would readily recognize that Chen01’s instruction could be modified to include an additional field for indicating a second number of branches in original code that are not to be taken in translated code when executed. Such proposed modification would still render Chen01’s instruction to operate as intended because including an additional instruction field would not change the principle of operation of Chen01’s instruction.
Therefore, for at least the reason set forth above, the rejections made under 35 U.S.C. § 103 with respect to Claims 1-7 and 16-21 are proper and therefore, maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Qing Chen whose telephone number is 571-270-1071. The Examiner can normally be reached on Monday through Friday from 9:00 AM to 5:00 PM ET.
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If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Wei Mui, can be reached at 571-272-3708. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Qing Chen/
Primary Examiner, Art Unit 2191