DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Information disclosure statement (IDS) submitted on 07/11/2025, 10/28/2025 and 11/12/2025 are considered by the examiner.
Applicant's duty of disclosure of material and information is not satisfied by presenting a patent examiner with references having over 100s of pages from which he is presumed to have been able, with his expertise and with adequate time, to have found the critical [material]. It ignores the real-world conditions under which examiners work. Examiner only searched few key words in those references.
Response to Arguments
Applicant's arguments filed on 11/12/2025 have been fully considered.
Examiner accepts applicant’s interpretation of – ‘mapping of capability’ as the most recent offset accessed 604 of Fig. 6 and the 112 rejections are withdrawn.
Applicant pointed out that - the published date of the subject matter in the LeMay reference were not later than the effective filing date for the application and are owned by or subject to an obligation of assignment to the same person (i.e., Intel Corporation).
Hence examiner has withdrawn the rejection made using LeMay as the prior art.
However, based on the new IDS filed, examiner identified new art filed on the same date as the instant application which triggered the new non-statutory double patenting rejection.
Non-Statutory Type Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper time wise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Langi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Omum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(1)(1) - 706.02(1)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patenVpatents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIN25, or PTO/AIN26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-l.isp
"A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by the earlier claim. ln re Longi-759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). " ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claims 1-24 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-24 of reference patent 12417099/(US 12417099 B2). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant applications are are matching in contents (while language is different) to reference claim 1-20 of reference patent 12417099/(US 12417099 B2).
Regarding instant apparatus claim 1, it matches in contents to the subset of reference apparatus claim 1 (app# 17/712,073, patent no:12417099).
Regarding instant apparatus claim 3, it matches in contents to the reference apparatus claim 2-3 (app# 17/712,073, patent no:12417099).
Regarding instant apparatus claim 4,5,6, they match in contents to the reference apparatus claim 4,5,6 (app# 17/712,073, patent no:12417099).
Instant claims 4,5,6 are similar to reference claims 4,5,6. In the instant claims applicant used most recent access being within the bounds and the reference claims mentioned the second, third etc. accesses are within the bounds.
Regarding instant apparatus claim 7, it matches in contents to the reference apparatus claim 7 (app# 17/712,073, patent no:12417099).
Regarding instant apparatus claim 8, it matches in contents to the reference apparatus claim 6 (app# 17/712,073, patent no:12417099).
Regarding instant method claim 9, it matches in contents to the subset of reference method claim 9 (app# 17/712,073, patent no:12417099).
Regarding instant method claim 11, it matches in contents to the reference method claim 10-11 (app# 17/712,073, patent no:12417099).
Regarding instant method claim 12, 13, 14, they match in contents to the combination of reference method claim 12, 13, 14 (app# 17/712,073, patent no:12417099).
Instant claims 12,13,14 are similar to reference claims 12,13,14. In the instant claims applicant used most recent access being within the bounds and the reference claims mentioned the second, third etc. accesses are within the bounds.
Regarding instant method claim 15, it matches in contents to the reference method claim 15 (app# 17/712,073, patent no:12417099).
Regarding instant method claim 16, it matches in contents to the reference method claim 16 (app# 17/712,073, patent no:12417099).
Regarding instant system claim 17, it matches in contents to the reference system claim 17 (app# 17/712,073, patent no:12417099).
Regarding instant system claim 19, it matches in contents to the device claim 18,19 (app# 17/712,073, patent no:12417099).
Regarding instant system claim 20,21,22, it matches in contents to the reference system claim 20,21,22 (app# 17/712,073, patent no:12417099).
Regarding instant system claim 23, it matches in contents to the reference system claim 23 (app# 17/712,073, patent no:12417099).
Regarding instant system claim 24, it matches in contents to the reference system claim 24 (app# 17/712,073, patent no:12417099).
Note that instant claims talk about a capability defined by an upper bound, a lower bound a validity field and an address field. The reference claims talk about first, second, third … capabilities each having a different set of fields. However, teachings applied to one capability is same as the other. The same concept of capability is instantiated multiple times and examiner does not find any difference in inventive concept between the two and this difference does not overcome the non-statutory double patenting issue.
Instant: app# 17/712072
Reference: patent 12417099/(US 12417099 B2), app# 17/712073
Claim 1
Claim 1
An apparatus comprising:
An apparatus comprising:
an execution circuit to execute an instruction that generates a memory access request for an element in memory via a capability;
an execution circuit to execute an instruction that generates a memory access request for an element in memory via a first capability;
a capability management circuit to check the capability for the memory access request, the capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an object to which the capability authorizes access;
a capability management circuit to check the first capability for the memory access request, the first capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a first object to which the first capability authorizes access;
a cache; and
a cache; and
a prefetch circuit to prefetch an additional element of the object from the memory to the cache based on the capability checked by the capability management circuit.
a prefetch circuit to: prefetch an additional element of the first object from the memory based on the first capability checked by the capability management circuit, determine if the additional element is a second capability comprising an address field of a second element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a second object to which the second capability authorizes access, and prefetch the second element from the memory to the cache based on the additional element being the second capability.
Claim 2
The apparatus of claim 1, wherein the prefetch circuit comprises a data structure to store a mapping of capabilities of the memory to their most recent access.
Claim 3
Claim 2
The apparatus of claim 2, wherein the prefetch circuit is to cause the prefetch of the additional element from the memory based on:
The apparatus of claim 1, wherein the prefetch circuit is to prefetch the additional element of the first object from the memory to the cache based on the first capability.
the mapping in the data structure for the capability indicating the additional element is not a most recent accessed element for the capability; and
Claim 3
the additional element being within the lower bound and the upper bound indicated by the capability for the object.
The apparatus of claim 1, wherein the prefetch circuit is to cause a prefetch of one or more further elements of the second object from the memory to the cache based on the one or more further elements being within the lower bound and the upper bound indicated by the second capability.
Claim 4
Claim 4
The apparatus of claim 2, wherein the prefetch circuit is to, in response to the prefetch of the additional element from the memory, update the mapping in the data structure for the capability to indicate the additional element is a most recent accessed element for the capability.
The apparatus of claim 3, wherein the one or more further elements of the second object are a plurality of further elements of the second object within the lower bound and the upper bound indicated by the second capability.
Claim 5
Claim 5
The apparatus of claim 2, wherein the prefetch circuit is to cause a prefetch of one or more further elements from the memory based on:
The apparatus of claim 3, wherein the prefetch circuit comprises a plurality of prefetch circuits, and the plurality of prefetch circuits are to prefetch the second element from the memory to the cache in parallel with the prefetch of the one or more further elements of the second object from the memory to the cache.
the mapping for the capability indicating the one or more further elements is not a most recent accessed element for the capability; and
the one or more further elements being within the lower bound and the upper bound indicated by the capability for the object.
Claim 6
Claim 6
The apparatus of claim 5, wherein the data structure is to store a mapping of capabilities in the memory to their most recent prefetched element, and stop the prefetch of the one or more further elements based on the mapping indicating a most recent prefetched element is a last element within the upper bound indicated by the capability for the object.
The apparatus of claim 1, wherein the prefetch circuit is to: prefetch a second additional element of the first object from the memory based on the first capability, determine if the second additional element is a third capability comprising an address field of a third element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a third object to which the third capability authorizes access, and prefetch the third element from the memory to the cache based on the second additional element being the third capability.
Claim 7
Claim 7
The apparatus of claim 1, wherein the prefetch circuit is to only prefetch the additional element of the object from the memory to the cache when the element in the memory is a second or greater access of the object by the execution circuit.
The apparatus of claim 6, wherein the prefetch circuit is to cause a prefetch of one or more further elements of the third object from the memory to the cache based on the one or more further elements being within the lower bound and the upper bound indicated by the third capability.
Claim 8
Claim 8
The apparatus of claim 1, wherein the prefetch circuit is to prefetch the additional element of the object from the memory to the cache based on the additional element being within the lower bound and the upper bound of the object indicated by the capability for the object.
The apparatus of claim 1, wherein the prefetch circuit is to prefetch the additional element of the first object from the memory based on the additional element being within the lower bound and the upper bound of the first object indicated by the first capability.
Claim 9
Claim 9
A method comprising:
A method comprising:
executing, by an execution circuit of a processor, an instruction that generates a memory access request for an element in memory via a capability;
executing, by an execution circuit of a processor, an instruction that generates a memory access request for an element in memory via a first capability;
checking, by a capability management circuit of the processor, the capability for the memory access request, the capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an object to which the capability authorizes access; and
checking, by a capability management circuit of the processor, the first capability for the memory access request, the first capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a first object to which the first capability authorizes access;
prefetching, by a prefetch circuit of the processor, an additional element of the object from the memory to a cache of the processor based on the capability checked by the capability management circuit.
prefetching, by a prefetch circuit of the processor, an additional element of the first object from the memory based on the first capability checked by the capability management circuit;
determining, by the processor, if the additional element is a second capability comprising an address field of a second element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a second object to which the second capability authorizes access; and
prefetching, by the prefetch circuit, the second element from the memory to a cache of the processor based on the additional element being the second capability.
Claim 10
The method of claim 9, further comprising storing, by the prefetch circuit in a data structure, a mapping of capabilities of the memory to their most recent access.
Claim 11
Claim 10
The method of claim 10, wherein the prefetching of the additional element from the memory is based on:
The method of claim 9, wherein the prefetching of the additional element comprises prefetching the additional element of the first object from the memory to the cache based on the first capability.
the mapping in the data structure for the capability indicating the additional element is not a most recent accessed element for the capability; and
Claim 11
the additional element being within the lower bound and the upper bound indicated by the capability for the object.
The method of claim 9, further comprising prefetching, by the prefetch circuit, one or more further elements of the second object from the memory to the cache based on the one or more further elements being within the lower bound and the upper bound indicated by the second capability.
Claim 12
Claim 12
The method of claim 10, further comprising, in response to the prefetch of the additional element from the memory, updating, by the prefetch circuit, the mapping in the data structure for the capability to indicate the additional element is a most recent accessed element for the capability.
The method of claim 11, wherein the one or more further elements of the second object are a plurality of further elements of the second object within the lower bound and the upper bound indicated by the second capability.
Claim 13
Claim 13
The method of claim 10, further comprising prefetching one or more further elements from the memory based on:
The method of claim 11, wherein the prefetch circuit comprises a plurality of prefetch circuits, and the plurality of prefetch circuits perform the prefetching of the second element from the memory to the cache in parallel with the prefetching of the one or more further elements of the second object from the memory to the cache.
the mapping for the capability indicating the one or more further elements is not a most recent accessed element for the capability; and
the one or more further elements being within the lower bound and the upper bound indicated by the capability for the object.
Claim 14
Claim 14
The method of claim 13, further comprising:
The method of claim 9, further comprising:
storing, by the prefetch circuit in the data structure, a mapping of capabilities in the memory to their most recent prefetched element; and
prefetching, by the prefetch circuit, a second additional element of the first object from the memory based on the first capability;
stopping the prefetch of the one or more further elements based on the mapping indicating a most recent prefetched element is a last element within the upper bound indicated by the capability for the object.
determining, by the processor, if the second additional element is a third capability comprising an address field of a third element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a third object to which the third capability authorizes access; and
prefetching, by the prefetch circuit, the third element from the memory to the cache based on the second additional element being the third capability.
Claim 15
Claim 15
The method of claim 9, wherein the prefetching of the additional element of the object from the memory to the cache is only when the element in the memory is a second or greater access of the object by the execution circuit.
The method of claim 14, further comprising prefetching, by the prefetch circuit, one or more further elements of the third object from the memory to the cache based on the one or more further elements being within the lower bound and the upper bound indicated by the third capability.
Claim 16
Claim 16
The method of claim 9, wherein the prefetching of the additional element of the object from the memory to the cache is based on the additional element being within the lower bound and the upper bound of the object indicated by the capability for the object.
The method of claim 9, wherein the prefetching of the additional element of the first object from the memory is based on the additional element being within the lower bound and the upper bound of the first object indicated by the first capability.
Claim 17
Claim 17
A system comprising:
A system comprising:
a memory;
a memory;
a processor comprising:
a processor comprising:
an execution circuit to execute an instruction that generates a memory access request for an element in the memory via a capability, and a cache separate from the memory;
an execution circuit to execute an instruction that generates a memory access request for an element in memory via a first capability, and a cache separate from the memory;
a capability management circuit to check the capability for the memory access request, the capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an object to which the capability authorizes access; and
a capability management circuit to check the first capability for the memory access request, the first capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a first object to which the first capability authorizes access; and
a prefetch circuit to:
a prefetch circuit to prefetch an additional element of the object from the memory to the cache based on the capability checked by the capability management circuit.
prefetch an additional element of the first object from the memory based on the first capability checked by the capability management circuit, determine if the additional element is a second capability comprising an address field of a second element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a second object to which the second capability authorizes access, and prefetch the second element from the memory to the cache based on the additional element being the second capability.
Claim 18
The system of claim 17, wherein the prefetch circuit comprises a data structure to store a mapping of capabilities of the memory to their most recent access.
Claim 19
Claim 18
The system of claim 18, wherein the prefetch circuit is to cause the prefetch of the additional element from the memory based on:
The system of claim 17, wherein the prefetch circuit is to prefetch the additional element of the first object from the memory to the cache based on the first capability.
the mapping in the data structure for the capability indicating the additional element is not a most recent accessed element for the capability; and
Claim 19
the additional element being within the lower bound and the upper bound indicated by the capability for the object.
The system of claim 17, wherein the prefetch circuit is to cause a prefetch of one or more further elements of the second object from the memory to the cache based on the one or more further elements being within the lower bound and the upper bound indicated by the second capability.
Claim 20
Claim 20
The system of claim 18, wherein the prefetch circuit is to, in response to the prefetch of the additional element from the memory, update the mapping in the data structure for the capability to indicate the additional element is a most recent accessed element for the capability.
The system of claim 19, wherein the one or more further elements of the second object are a plurality of further elements of the second object within the lower bound and the upper bound indicated by the second capability.
Claim 21
Claim 21
The system of claim 18, wherein the prefetch circuit is to cause a prefetch of one or more further elements from the memory based on:
The system of claim 19, wherein the prefetch circuit comprises a plurality of prefetch circuits, and the plurality of prefetch circuits are to prefetch the second element from the memory to the cache in parallel with the prefetch of the one or more further elements of the second object from the memory to the cache.
the mapping for the capability indicating the one or more further elements is not a most recent accessed element for the capability; and
the one or more further elements being within the lower bound and the upper bound indicated by the capability for the object.
Claim 22
Claim 22
The system of claim 21, wherein the data structure is to store a mapping of capabilities in the memory to their most recent prefetched element, and stop the prefetch of the one or more further elements based on the mapping indicating a most recent prefetched element is a last element within the upper bound indicated by the capability for the object.
The system of claim 17, wherein the prefetch circuit is to: prefetch a second additional element of the first object from the memory based on the first capability, determine if the second additional element is a third capability comprising an address field of a third element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a third object to which the third capability authorizes access, and prefetch the third element from the memory to the cache based on the second additional element being the third capability.
Claim 23
Claim 23
The system of claim 17, wherein the prefetch circuit is to only prefetch the additional element of the object from the memory to the cache when the element in the memory is a second or greater access of the object by the execution circuit.
The system of claim 22, wherein the prefetch circuit is to cause a prefetch of one or more further elements of the third object from the memory to the cache based on the one or more further elements being within the lower bound and the upper bound indicated by the third capability.
Claim 24
Claim 24
The system of claim 17, wherein the prefetch circuit is to prefetch the additional element of the object from the memory to the cache based on the additional element being within the lower bound and the upper bound of the object indicated by the capability for the object.
The system of claim 17, wherein the prefetch circuit is to prefetch the additional element of the first object from the memory based on the additional element being within the lower bound and the upper bound of the first object indicated by the first capability.
Potential Allowable Subject Matter
Claims 1, 3-9, 11-17 and 19-24 are currently not rejected in view of prior art on the grounds of 35 U.S.C 102/103, and could become allowable subject matter if the double patenting rejection is overcome.
Claims 2, 10 and 18 do not have double patenting issue but are dependent on claim that has non-statutory double patenting rejection with potential allowable subject matter and could become allowable if the independent claim overcomes double patenting rejection.
The following is an Examiner's statement of reasons for potential allowability:
Claim 1 states, ‘An apparatus comprising: an execution circuit to execute an instruction that generates a memory access request for an element in memory via a capability; a capability management circuit to check the capability for the memory access request, the capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an object to which the capability authorizes access; a cache; and a prefetch circuit to prefetch an additional element of the object from the memory to the cache based on the capability checked by the capability management circuit.’
Prior arts teach different claim elements as quoted below.
an execution circuit to execute an instruction that generates a memory access request for an element in memory via a capability; a capability management circuit to check the capability for the memory access request, the capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an object to which the capability authorizes access (HU, Wei-wu et al. (CN 101226468 A)[Hu]: abstract: teaches bounded memory access method. Teaches a register file comprising an upper bound address register for storing the effective address as the upper bound; and a lower bound address register for storing the effective address as the lower bound; The operational subassembly comprises a first determination module for determining the validity of the instruction operand address according to the upper bound address stored in the upper bound address register and/or the lower bound address stored in the lower bound address register, and further comprises a second determination module for determining the validity of the instruction address in the memory access instruction according to the upper bound address stored in the upper bound address register and/or the lower bound address stored in the lower bound address register. Determining validity implies having fields/locations to save/remember if the operand address and instruction addresses are valid or invalid); a cache (PODAIMA JASON EDWARD et al. (WO 2016195884 A1)[Podaima] Fig.2 block 232, Translation Caches ); and a prefetch circuit to prefetch an additional element of the object from the memory to the cache based on the capability checked by the capability management circuit (PODAIMA JASON EDWARD et al. (WO 2016195884 A1)[Podaima]: [0084-0091] teaches examining all existing prefetch requests in the pre-fetch engine 920 when pre-fetching is triggered for a given trigger address. If the trigger address of the newly triggered pre-fetch request falls within the pre-fetch window of any existing prefetch requests, the newly triggered pre-fetch request is immediately discarded.
When pre-fetching is triggered, the pre-fetch scheduler 924 generates a sequence descriptor describing a sequence of address translations that will be pre-fetched. The addresses in this sequence are generated based on the trigger address, a pre-fetch window size, and a stride length. FIG. 10 illustrates an exemplary pre-fetch window 1000 according to an aspect of the disclosure. The pre-fetch window size is programmable and defines an aligned address range containing the trigger address.
For a given pre-fetch request, translation requests are limited to addresses bound by the pre-fetch window 1000. Note that an exception to this is the "extended pre-fetch window" which generates requests above and below the window. Generating the translation requests at "stride length" intervals within the pre-fetch window 1000, the pre-fetch scheduler 924 generates translation requests for the addresses immediately above (higher address) and/or immediately below (lower address) the window boundary, i.e., regions 1030A-B.
FIG. 11 illustrates pre-fetch window size and stride length examples 1110 and 1120. In example 1110, the stride length is 16kB and the window size is 32kB. In example 1120, the stride length is 16kB and the window size is 64kB. Pre-fetch window 1210 illustrates selecting stride length regions by going "forward." The first translation request is issued for the region including the "window start," and each subsequent address requested is incremented by the stride length until the stride length region containing the "window end" is requested.).
So, Podama teaches checking/examining prefetch requests and uses prefetch window that involves prefetch address boundary.
However, in Podama, prefetch boundary is used to facilitate prefetch address translation and executing the prefetches and to know when to stop prefetching. It is not same or similar to instant claim where a lower bound and an upper bound indicate to which region the capability authorizes access and prefetch is controlled by that authorization.
No known prior arts taken alone or in combination teaches a prefetch circuit to prefetch an additional element of the object from the memory to the cache based on the capability checked by the capability management circuit where capability comprises an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an object to which the capability authorizes access.
Regarding claim 9, this is a method claim that corresponds to the apparatus claim 1 and contains the same potentially allowable claim limitation and hence is potentially allowable for the same reason.
Regarding claim 17, this is a system claim that corresponds to the apparatus claim 1 and contains the same potentially allowable claim limitation and hence is potentially allowable for the same reason.
Claims 2-8 are dependent on potentially allowable base claim 1 and hence are potentially allowable for the same reason.
Claims 10-16 are dependent on potentially allowable base claim 9 and hence are potentially allowable for the same reason.
Claims 18-24 are dependent on potentially allowable base claim 17 and hence are potentially allowable for the same reason.
Conclusion
The prior arts made of record and not relied upon that is considered pertinent to applicant's disclosure is recorded in pe2e_search_notes.pdf and is attached as OA.APPENDIX.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD S HASAN whose telephone number is (571)270-1737. The examiner can normally be reached on Mon-Fri 8-5.
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/M.S.H/Examiner, Art Unit 2138
/SHAWN X GU/
Primary Examiner, AU2138