Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 09/02/2025 have been fully considered but they are not persuasive. Applicant alleges that “None of Alben, Kang, Knapp or Morton, alone or combined, describe or suggest a microcontroller to trigger and control a structural test mode during in-field booting of an IC.” While the examiner agrees that Alben does not explicitly disclose “a microcontroller to trigger and control a structural test mode during in-field booting of an IC,” Alben absolutely teaches “a microcontroller to trigger and control a structural test mode” (see para. 27: A test manager may manage testing of the component(s) subject to test… The test manager 112 may then trigger the test on the component to be tested.). Furthermore, Alben strongly suggests “control a structural test mode during in-field booting of an IC.” (para. 5: fault testing within the present disclosure may leverage low power or sleep states—including power-on or power-off states—of components to perform testing while preserving the state integrity of the component.). However, it is not explicitly taught that a power-on state is the same as “in-field booting of an IC” or that the states in which testing is performed include “in field booting of an IC.” This deficiency is cured by new reference Jung (US 20150169333), as shown in the new rejection of claims 1, 10, and 14.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Alben (US 20210286693) in view of Jung (US 20150169333).
Regarding claim 14, Alben discloses:
A method comprising:
triggering, by a microcontroller, an integrated circuit (IC) to enter a structural test mode,… (para. 29: structural testing may be performed on the processing unit(s) 202, processing core(s), and/or components or subcomponents thereof. And para. 27: A test manager 112 may manage testing of the component(s) subject to test. And para. 18: During deployment each of the components of a system may not be in use at all times. During these idle periods… the component may be tested.)
the structural test mode including a memory built-in self-test (MBIST) mechanism and an automatic test pattern generation (ATPG) mechanism; (para. 25: the component(s) to be tested may undergo testing (e.g., using… automatic test pattern generation (ATPG), … memory BIST (MBIST))
configuring, by the microcontroller, the IC for MBIST operation; (para. 27: A test manager 112 may manage testing of the component(s) subject to test. Prior to testing, in some embodiments, the state of the component(s) to be tested may be reset.)
triggering, by the microcontroller, MBIST testing of the IC; (para. 27: A test manager 112 may manage testing of the component(s) subject to test. And para. 25: the component(s) to be tested may undergo testing (e.g., using… memory BIST (MBIST)
configuring, by the microcontroller, the IC for ATPG operation; (para. 27: A test manager 112 may manage testing of the component(s) subject to test. Prior to testing, in some embodiments, the state of the component(s) to be tested may be reset.)
triggering, by the microcontroller, ATPG testing of the IC; (para. 27: A test manager 112 may manage testing of the component(s) subject to test. And para. 25: the component(s) to be tested may undergo testing (e.g., using… automatic test pattern generation (ATPG)
and triggering, by the microcontroller, the IC to enter a functional mode. (para. 35: Upon completion of the test for a particular component(s), the state information… may be retrieved from the memory 214 and used to restore the state of the component(s)… As such the component(s) that were tested may be returned to a pre-test state- thereby preserving state integrity- and a clamp deactivator 118 may deactivate the clamp. By deactivating or removing the clamp, the component(s) that were tested may be returned to normal operation within the system.) The test manager triggers and configures the testing to be performed, the completion of this testing triggers the system to enter a functional mode. Accordingly, the test manager is considered to trigger the system to enter a functional mode.
However, Alben does not explicitly teach:
[Testing…] during in-field booting,
In the analogous art of circuit testing, Jung teaches:
[Testing…] during in-field booting, (claim 9: the BIOS is configured to perform power-on self test (POST) on the main memory and the storage device during the booting operation.)
It would have been obvious to one of ordinary skill in the art, having the teachings of Alben and Jung before them, before the effective filing date of the claimed invention, to integrate testing during the booting operation (taught by Jung) into the testing circuitry (taught by Alben), to allow for benefits such as speed and reliability (Jung, para. 7).
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Alben in view of Jung and Kang (US Publication No. 20050283697).
Regarding claim 1, Alben discloses:
An apparatus comprising: an integrated circuit (IC) having circuitry to operate in a structural test mode, (para. 29: Structural testing may be performed on the processing unit(s) 202, processing core(s), and/or components or subcomponents thereof.)
the structural test mode including a memory built-in self-test (MBIST) mechanism and an automatic test pattern generation (ATPG) mechanism; (para. 25: The component(s) to be tested may undergo testing (e.g., using… automatic test pattern generation (ATPG), … memory BIST (MBIST)).)
a microcontroller to trigger and control the structural test mode during in-field… [operation] of the IC. (para. 27: A test manager 112 may manage testing of the components subject to test. And para. 18: During deployment each of the components of a system may not be in use at all times. During these idle periods… the component may be tested.)
However, Alben does not explicitly disclose:
[Testing…] during in-field booting,
A programmable logic device (PLD) to support the ATPG mechanism.
Jung teaches:
[Testing…] during in-field booting, (claim 9: the BIOS is configured to perform power-on self test (POST) on the main memory and the storage device during the booting operation.)
It would have been obvious to one of ordinary skill in the art, having the teachings of Alben and Jung before them, before the effective filing date of the claimed invention, to integrate testing during the booting operation (taught by Jung) into the testing circuitry (taught by Alben), to allow for benefits such as speed and reliability (Jung, para. 7).
However, the combination of Alben and Jung does not explicitly disclose:
A programmable logic device (PLD) to support the ATPG mechanism.
In the analogous art of testing computer systems, Kang discloses:
A programmable logic device (PLD) to support the ATPG mechanism (The programmable device 233 can be implemented using a device such as a Programmable Logic Device (PLD)… The programmable device is programmed to receive the test program from the external server 300, generate the test pattern signal and expected signal, transmit the test pattern signal to the semiconductor device, receive the test result output from the semiconductor device, and compares the test result signal with the expected signal, thus testing the operation of the semiconductor device.)
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Jung, and Kang before them, before the effective filing date of the claimed invention, to incorporate a PLD to assist with ATPG (disclosed by Kang) into the testing circuitry (disclosed by the combination of Alben and Jung), to allow for benefits such as low cost (Kang, para. 49).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Alben in view of Jung and Knapp (US Patent No. 7454556).
Regarding claim 15, Alben teaches the method of claim 14.
Alben further teaches:
configuring of the IC for MBIST operation… (para. 27: A test manager 112 may manage testing of the component(s) subject to test. Prior to testing, in some embodiments, the state of the component(s) to be tested may be reset. And para. 25: the component(s) to be tested may undergo testing (e.g., using… memory BIST (MBIST))
However, Alben does not explicitly teach wherein:
The configuring of the IC for MBIST operation is through a joint test action group (JTAG) interface. (emphasis added)
In the analogous art of testing computer systems, Knapp teaches:
[configuring an] IC… through a joint test action group (JTAG) interface. (Fig. 4, programming host device 14 connected to component with JTAG support (FPGA) via JTAG interface. And col. 3, lines 60-66: The programming host 14—such as… a microcontroller… software running on the intelligent programming host 14 interacts with the programming control logic of the component with JTAG support to enable programming of its configuration.) The microcontroller disclosed by Alben is the programming host device, as Alben’s microcontroller resets (reprograms) components to be tested. It is well known in the art that a FPGA is a kind of IC.
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Jung, and Knapp before them, before the effective filing date of the claimed invention, to incorporate configuring an IC through a JTAG interface (disclosed by Knapp) into the MBIST and ATPG testing circuitry (disclosed by the combination of Alben and Jung), to allow for benefits such as efficient use of resources (Knapp, col. 4, lines 36-40).
Claims 2-4 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Alben in view of Jung, Kang, and Knapp.
Regarding claim 2, the combination of Alben, Jung, and Kang teaches the apparatus of claim 1.
Alben further teaches:
The microcontroller connected to the IC… (para. 27: A test manager 112 may manage testing of the components subject to test.)
However, Alben does not explicitly disclose wherein:
the microcontroller is connected to the IC through a plurality of control pins including a test mode pin and a reset pin.
Knapp teaches:
the microcontroller is connected to the IC through a plurality of control pins including a test mode pin and a reset pin. (Fig. 4, component with JTAG support 2 (FPGA) has a plurality of control pins including RP# (reset pin) and TMS (test mode select). Programming host device 14 is connected to the component with JTAG support 2 (FPGA) via these control pins. And col. 3, lines 60-66: The programming host 14—such as… a microcontroller… software running on the intelligent programming host 14 interacts with the programming control logic of the component with JTAG support to enable programming of its configuration.)
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Jung, Kang, and Knapp before them, before the effective filing date of the claimed invention, to incorporate connecting a microcontroller to an IC via control pins (disclosed by Knapp) into the MBIST and ATPG testing circuitry (disclosed by the combination of Alben, Jung, and Kang), to allow for benefits such as efficient use of resources (Knapp, col. 4, lines 36-40).
Regarding claim 3, the combination of Alben, Jung, Kang, and Knapp teaches the apparatus of claim 2.
Alben further teaches:
The microcontroller also connected to the IC… (para. 27: A test manager 112 may manage testing of the components subject to test.)
However, Alben does not explicitly disclose wherein:
The microcontroller is also connected to the IC through a joint test action group (JTAG) interface. (emphasis added)
Knapp teaches wherein:
The microcontroller is also connected to the IC through a joint test action group (JTAG) interface. (Fig. 4, programming host device 14 connected to component with JTAG support (FPGA) via JTAG interface. And col. 3, lines 60-66: The programming host 14—such as… a microcontroller… software running on the intelligent programming host 14 interacts with the programming control logic of the component with JTAG support to enable programming of its configuration.) It is well known in the art that an FPGA is a kind of IC.
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Jung, Kang, and Knapp before them, before the effective filing date of the claimed invention, to incorporate connecting a microcontroller to an IC through a JTAG interface (disclosed by Knapp) into the MBIST and ATPG testing circuitry (disclosed by the combination of Alben, Jung, and Kang), to allow for benefits such as efficient use of resources (Knapp, col. 4, lines 36-40).
Regarding claim 4, The combination of Alben, Jung, Knapp, and Kang teaches the apparatus of claim 3. Alben further teaches wherein:
The… [ATPG mechanism] … is also connected to the IC and… the microcontroller (para. 25: the component(s) to be tested may undergo testing (e.g., using… automatic test pattern generation (ATPG). And para. 27: a test manager 112 may manage testing of the component(s) subject to test.) The components to be tested must be connected to the ATPG mechanism so the ATPG testing may be performed. The test manager must be connected to the ATPG mechanism so it can manage testing.
Alben additionally teaches:
[programming the memory of the ATPG hardware (BIST hardware)] (para. 27: The test manager 112 may indicate a type of test to be conducted, the component(s) (or test components corresponding thereto) to be tested … The test information… may be stored in the memory 214. And para. 30: BIST hardware 228 may retrieve the test information from the location. Once retrieved, the test vectors may be applied to the component(s).)
However, Alben does not explicitly teach wherein:
[the ATPG mechanism includes] the PLD…
the PLD is also connected to the IC… through the JTAG interface (emphasis added)
the PLD is also connected to… the microcontroller… through the JTAG interface (emphasis added)
Kang discloses:
[the ATPG mechanism includes] the PLD (para. 48: The programmable device 233 can be implemented using a device such as a Programmable Logic Device (PLD)… The programmable device is programmed to receive the test program from the external server 300, generate the test pattern signal and expected signal, transmit the test pattern signal to the semiconductor device, receive the test result output from the semiconductor device, and compares the test result signal with the expected signal, thus testing the operation of the semiconductor device.)
It would be obvious to one of ordinary skill in the art, having the teachings of Alben and Kang before them, before the effective filing date of the claimed invention, to incorporate the ATPG mechanism being a PLD (disclosed by Kang) into the testing circuitry (disclosed by Alben), to allow for benefits such as low cost (Kang, para. 49).
However, the combination of Alben and Kang still does not explicitly teach wherein:
the PLD is also connected to the IC… through the JTAG interface (emphasis added)
the PLD is also connected to… the microcontroller… through the JTAG interface (emphasis added)
Knapp teaches:
the PLD is also connected to the IC… through the JTAG interface (emphasis added) (fig. 4: programming host device 14 supplies test data through TDI port of JTAG interface 4 to component with JTAG Support 2 (FPGA)) The PLD supplies test data to the device under test, and is therefore considered to be a programming host device. It is well known in the art that a FPGA is a kind of IC.
the PLD is also connected to… the microcontroller… through the JTAG interface (emphasis added) (Fig. 4, programming host device 14 connected to component with JTAG support (FPGA) via JTAG interface. And col. 3, lines 60-66: The programming host 14—such as… a microcontroller… software running on the intelligent programming host 14 interacts with the programming control logic of the component with JTAG support to enable programming of its configuration.) It is well known in the art that an FPGA is a kind of PLD.
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Jung, Kang, and Knapp before them, before the effective filing date of the claimed invention, to incorporate a configuring JTAG supported FPGAs through a JTAG interface (disclosed by Knapp) into the MBIST and ATPG testing circuitry for testing a JTAG supported IC (disclosed by the combination of Alben, Jung, and Kang), to allow for benefits such as efficient use of resources (Knapp, col. 4, lines 36-40).
Regarding claim 16, the combination of Alben, Jung, and Knapp teaches the method of claim 15.
Alben further teaches:
Further comprising configuring by the microcontroller… the ATPG mechanism. (para. 27: The test manager 112 may indicate a type of test to be conducted, the component(s) (or test components corresponding thereto) to be tested, a location of the test data, a location to store the results of the test, an expected result of the test for each component and/or other test information. Test information, with respect to the test system 200 of FIGS. 2A and 2B, may be stored in the memory 214. And para. 25: The component(s) to be tested may undergo testing (e.g., using… automatic test pattern generation (ATPG). And para. 30: the Online BIST hardware 228 [performing ATPG] may retrieve the test information from the location.)
However, Alben does not explicitly disclose wherein:
[the ATPG mechanism contains] a programmable logic device (PLD) to support the ATPG mechanism.
Kang discloses:
[the ATPG mechanism contains] a programmable logic device (PLD) to support the ATPG mechanism. (para. 48: The programmable device 233 can be implemented using a device, such as a Programmable Logic Device (PLD)… the programmable device 233 is programmed to receive the test program [the test information from Alben’s test manager]… generate the test pattern signal and expected signal [supporting the ATPG mechanism].)
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Jung, Knapp, and Kang before them, before the effective filing date of the claimed invention, to incorporate the ATPG mechanism being a PLD (disclosed by Kang) into the testing circuitry (disclosed by the combination of Alben, Jung, and Knapp), to allow for benefits such as low cost (Kang, para. 49).
Regarding claim 17, the combination of Alben, Jung, Kang, and Knapp teaches the method of claim 16. Alben teaches further comprising:
Configuring the IC for ATPG operation (para. 27: A test manager 112 may manage testing of the component(s) subject to test. Prior to testing, in some embodiments, the state of the component(s) to be tested may be reset. And para. 25: the component(s) to be tested may undergo testing (e.g., using… automatic test pattern generation (ATPG))
and the configuring of the [ATPG mechanism] … (para. 27: The test manager 112 may indicate a type of test to be conducted, the component(s) (or test components corresponding thereto) to be tested, a location of the test data, a location to store the results of the test, an expected result of the test for each component and/or other test information. Test information, with respect to the test system 200 of FIGS. 2A and 2B, may be stored in the memory 214. And para. 25: The component(s) to be tested may undergo testing (e.g., using… automatic test pattern generation (ATPG). And para. 30: the Online BIST hardware 228 [performing ATPG] may retrieve the test information from the location.)
However, Alben does not explicitly disclose wherein:
[the ATPG mechanism includes] the PLD;
The configuring of the IC for ATPG operation… [is] through the JTAG interface; (emphasis added)
The configuring of the PLD [is] through the JTAG interface. (emphasis added)
Kang discloses:
[the ATPG mechanism includes] the PLD (para. 48: The programmable device 233 can be implemented using a device such as a Programmable Logic Device (PLD)… The programmable device is programmed to receive the test program from the external server 300, generate the test pattern signal and expected signal, transmit the test pattern signal to the semiconductor device, receive the test result output from the semiconductor device, and compares the test result signal with the expected signal, thus testing the operation of the semiconductor device.)
It would be obvious to one of ordinary skill in the art, having the teachings of Alben and Kang before them, before the effective filing date of the claimed invention, to incorporate the ATPG mechanism being a PLD (disclosed by Kang) into the testing circuitry (disclosed by Alben), to allow for benefits such as low cost (Kang, para. 49).
However, the combination of Alben and Kang still does not explicitly disclose:
The configuring of the IC for ATPG operation… [is] through the JTAG interface; (emphasis added)
The configuring of the PLD [is] through the JTAG interface. (emphasis added)
Knapp teaches:
The configuring of the IC for ATPG operation… [is] through the JTAG interface; (Fig. 4, programming host device 14 connected to component with JTAG support (FPGA) via JTAG interface. And col. 3, lines 60-66: The programming host 14—such as… a microcontroller… software running on the intelligent programming host 14 interacts with the programming control logic of the component with JTAG support to enable programming of its configuration.) The microcontroller disclosed by Alben is the programming host device, as Alben’s microcontroller resets (reprograms) components to be tested. It is well known in the art that a FPGA is a kind of IC.
The configuring of the PLD [is] through the JTAG interface. (Fig. 4, programming host device 14 connected to component with JTAG support (FPGA) via JTAG interface. And col. 3, lines 60-66: The programming host 14—such as… a microcontroller… software running on the intelligent programming host 14 interacts with the programming control logic of the component with JTAG support to enable programming of its configuration.) It is well known in the art that an FPGA is a kind of PLD.
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Jung, Kang, and Knapp before them, before the effective filing date of the claimed invention, to incorporate configuring FPGAs through a JTAG interface (disclosed by Knapp) into the MBIST and ATPG testing circuitry (disclosed by Alben, Jung, and Kang), to allow for benefits such as efficient use of resources (Knapp, col. 4, lines 36-40).
Regarding claim 18, the combination of Alben, Jung, Kang, and Knapp teaches the method of claim 17. Alben teaches further comprising:
Triggering, by the microcontroller, an ATPG load operation. (para. 27: The test manager 112 may then trigger the test on the component(s) to be tested. And para. 25: the component(s) to be tested may undergo testing (e.g., using… automatic test pattern generation (ATPG). And para. 39: The method 300, at block B306, includes applying second data representative of a structural test vector to the region.) Applying the ATPG test vector is done by loading the test vector into the component to be tested, essentially an ATPG load operation.
Regarding claim 19, the combination of Alben, Jung, Kang, and Knapp teaches the method of claim 18. Alben teaches further comprising:
Triggering, by the microcontroller, an ATPG capture operation. (para. 27: The test manager 112 may then trigger the test on the component(s) to be tested. And para. 25: the component(s) to be tested may undergo testing (e.g., using… automatic test pattern generation (ATPG). And para. 40: the method 300, at block B308, includes receiving third data generated using the region and based at least in part on the region processing the second data.) Receiving the data generated based on the applied ATPG test vector is capturing the output, essentially a ATPG capture operation. This is considered to be triggered by the test manager because the test manager triggers the testing (method 300), and block B308 is part of method 300.
Regarding claim 20, the combination of Alben, Jung, Kang, and Knapp teaches the method of claim 19. Alben teaches further comprising:
Triggering, by the microcontroller, an ATPG unload operation. (para. 27: The test manager 112 may then trigger the test on the component(s) to be tested. And para. 25: the component(s) to be tested may undergo testing (e.g., using… automatic test pattern generation (ATPG). And para. 42: the method 300, at block B312, includes restoring the state of the region to the current state using the first data.) Restoring the state of the region to its original state must include unloading the applied test vectors, and is essentially an ATPG unload operation. This is considered to be triggered by the test manager because the test manager triggers the testing (method 300), and block B312 is part of method 300.
Claims 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Alben in view of Jung, Kang, Knapp, and Morton (US Publication No. 20150113344).
Regarding claim 5, the combination of Alben, Jung, Knapp, and Kang teaches the apparatus of claim 4. Alben further teaches wherein:
[the ATPG mechanism] is also connected to the IC (para. 39: the test manager 112 may apply, via the… Online BIST hardware, a test vector… to the component(s) undergoing testing. And para. 25: the component(s) to be tested may undergo testing (e.g., using… automatic test pattern generation (ATPG).) The BIST hardware (implementing ATPG testing) must be connected to the system (component under test) so the test vectors may be applied.
However, Alben does not explicitly teach:
[the ATPG mechanism includes] the PLD
The PLD is connected to the IC through a scan interface (emphasis added)
Kang discloses:
[the ATPG mechanism includes] the PLD (para. 48: The programmable device 233 can be implemented using a device such as a Programmable Logic Device (PLD)… The programmable device is programmed to receive the test program from the external server 300, generate the test pattern signal and expected signal, transmit the test pattern signal to the semiconductor device, receive the test result output from the semiconductor device, and compares the test result signal with the expected signal, thus testing the operation of the semiconductor device.)
It would be obvious to one of ordinary skill in the art, having the teachings of Alben and Kang before them, before the effective filing date of the claimed invention, to incorporate the ATPG mechanism being a PLD (disclosed by Kang) into the testing circuitry (disclosed by Alben), to allow for benefits such as low cost (Kang, para. 49).
However, the combination of Alben and Kang still does not explicitly disclose:
The PLD is connected to the IC through a scan interface (emphasis added)
In the analogous art of testing computer systems, Morton teaches:
The PLD is connected to the IC through a scan interface (emphasis added) (para. 49: The test vectors stored in the memory 56 of the tester 54 are applied by the tester 54 to the device under test. The response to each test vector is read out by the VLSI tester via the interface 64 and compared by a comparator 55 of the VLSI tester to an expected response stored in the memory 56. And para. 45: The VLSI tester 54 is used to apply scan test patterns via an interface 64.) Interface 64 is considered to be a scan interface because scan test patterns are input therein. Morton teaches connecting a tester (implemented as a PLD in Kang) to a device under test (IC) via a scan interface.
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Jung, Kang, Knapp, and Morton before them, before the effective filing date of the claimed invention, to incorporate a scan interface connecting a tester and device under test (disclosed by Morton) into the testing circuitry (disclosed by the combination of Alben, Jung, Kang, and Knapp), to allow for benefits such as fault detection (Morton, para. 18).
Regarding claim 6, the combination of Alben, Jung, Knapp, Kang, and Morton teaches the apparatus of claim 5. Alben further teaches wherein:
The [controls for the ATPG mechanism] is accessible by the microcontroller … (para. 27: the test manager 112 may indicate a type of test to be conducted, the component(s) (or test components corresponding thereto) to be tested… The test information… may be stored in the memory 214. And para. 25: the component(s) to be tested undergo testing (e.g., using… automatic test pattern generation (ATPG)). And para. 30: The Online BIST hardware 228 [performing ATPG testing] may retrieve the test information from the location. One received; the test vectors may be applied to the components [in accordance with the test information provided by the test manager]).
However, Alben does not explicitly teach wherein:
[the ATPG mechanism includes] the PLD;
The PLD includes a controller and a memory manager;
The controller is accessible by the microcontroller through the JTAG interface (emphasis added);
And is to trigger the memory manager to fetch one or more ATPG patterns from a memory.
Kang discloses:
[the ATPG mechanism includes] the PLD (para. 48: The programmable device 233 can be implemented using a device such as a Programmable Logic Device (PLD)… The programmable device is programmed to receive the test program from the external server 300, generate the test pattern signal and expected signal, transmit the test pattern signal to the semiconductor device, receive the test result output from the semiconductor device, and compares the test result signal with the expected signal, thus testing the operation of the semiconductor device.)
The PLD includes a controller (para. 49: the programmable device 233 may include therein a program for performing control to transmit a generated test pattern signal)
[the controller] is to trigger [the transmission of test patterns] (para. 49: the programmable device 233 may include therein a program for performing control to transmit a generated test pattern signal)
It would be obvious to one of ordinary skill in the art, having the teachings of Alben and Kang before them, before the effective filing date of the claimed invention, to incorporate the ATPG mechanism being a PLD (disclosed by Kang) into the testing circuitry (disclosed by Alben), to allow for benefits such as low cost (Kang, para. 49).
However, the combination of Alben and Kang still does not explicitly disclose:
The PLD includes a memory manager;
The controller is accessible by the microcontroller through the JTAG interface (emphasis added);
[transmission of test patterns includes] the memory manager to fetch one or more ATPG patterns from a memory.
Knapp teaches:
The controller is accessible by the microcontroller through the JTAG interface (emphasis added); (Fig. 4, programming host device 14 connected to component with JTAG support (FPGA) via JTAG interface. And col. 3, lines 60-66: The programming host 14—such as… a microcontroller… software running on the intelligent programming host 14 interacts with the programming control logic of the component with JTAG support to enable programming of its configuration.) It is well known in the art that an FPGA is a kind of PLD.
Alben teaches a test manager (microcontroller) accessing the memory (controls) of BIST hardware (implementing ATPG testing). Kang teaches ATPG testing implemented by a PLD containing a controller. In view of Knapp, the combination teaches: the test manager can access the controller via a JTAG interface.
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Kang, and Knapp before them, before the effective filing date of the claimed invention, to incorporate configuring the controls of a PLD with a microcontroller via a JTAG interface (disclosed by Knapp) into the MBIST and ATPG testing circuitry for testing a JTAG supported IC (disclosed by the combination of Alben and Kang), to allow for benefits such as efficient use of resources (Knapp, col. 4, lines 36-40).
However, the combination of Alben, Kang, and Knapp does not explicitly disclose:
The PLD includes a memory manager;
[transmission of test patterns includes] the memory manager to fetch one or more ATPG patterns from a memory.
Morton teaches:
The [tester] includes a memory manager; [transmission of test patterns includes] the memory manager to fetch one or more ATPG patterns from a memory. (para. 49: The test vectors stored in memory 56 of the tester are applied by the tester 54 to the device under test.) Morton teaches a change in functioning of the PLD (disclosed by Kang), so that the ATPG test patterns generated are stored in memory, and then later retrieved just prior to transmission by a memory manager.
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Jung, Kang, Knapp, and Morton before them, before the effective filing date of the claimed invention, to incorporate storing generated test patterns in memory to be retrieved directly prior to transmission (disclosed by Morton) into the testing circuitry (disclosed by the combination of Alben, Jung, Kang, and Knapp), to allow for benefits such as fault detection (Morton, para. 18).
Regarding claim 7, the combination of Alben, Jung, Kang, Knapp, and Morton teaches the apparatus of claim 6. Morton further teaches wherein:
The memory is within the [tester] (fig. 2, Memory 56 within VLSI testers 4).
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Knapp, and Morton before them, before the effective filing date of the claimed invention, to incorporate storing generated test patterns in memory to be retrieved directly prior to transmission (disclosed by Morton) into the testing circuitry (disclosed by the combination of Alben and Knapp), to allow for benefits such as fault detection (Morton, para. 18).
However, the combination of Alben, Knapp, and Morton does not explicitly teach:
[the tester is a] PLD
Kang teaches:
[the tester is a] PLD
(para. 48: The programmable device 233 can be implemented using a device such as a Programmable Logic Device (PLD)… The programmable device is programmed to receive the test program from the external server 300, generate the test pattern signal and expected signal, transmit the test pattern signal to the semiconductor device, receive the test result output from the semiconductor device, and compares the test result signal with the expected signal, thus testing the operation of the semiconductor device.)
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Jung, Kang, Knapp, and Morton before them, before the effective filing date of the claimed invention, to incorporate the tester being a PLD (disclosed by Kang) into the testing circuitry (disclosed by the combination of Alben, Jung, Knapp, and Morton), to allow for benefits such as low cost (Kang, para. 49).
Regarding claim 8, the combination of Alben, Kang, Knapp, and Morton teaches the apparatus of claim 7. Morton further teaches wherein:
The memory is a non-volatile memory connected to the [tester] (fig. 2, Memory 56 within, and therefore connected to, VLSI testers 4. And para. 97: The memory may be of any type suitable to the local technical environment… such as… magnetic memory devices.) It is well known in the art that magnetic memory is non-volatile.
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Knapp, and Morton before them, before the effective filing date of the claimed invention, to incorporate storing generated test patterns in non-volatile memory to be retrieved directly prior to transmission into the testing circuitry (disclosed by Morton) into the testing circuitry (disclosed by the combination of Alben and Knapp), to allow for benefits such as fault detection (Morton, para. 18).
However, the combination of Alben, Knapp, and Morton does not explicitly teach:
[the tester is] the PLD
Kang teaches:
[the tester is a] PLD (para. 48: The programmable device 233 can be implemented using a device such as a Programmable Logic Device (PLD)… The programmable device is programmed to receive the test program from the external server 300, generate the test pattern signal and expected signal, transmit the test pattern signal to the semiconductor device, receive the test result output from the semiconductor device, and compares the test result signal with the expected signal, thus testing the operation of the semiconductor device.)
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Jung, Kang, Knapp, and Morton before them, before the effective filing date of the claimed invention, to incorporate the tester being a PLD (disclosed by Kang) into the testing circuitry (disclosed by the combination of Alben, Jung, Knapp, and Morton), to allow for benefits such as low cost (Kang, para. 49).
Regarding claim 9, the combination of Alben, Jung, Kang, Knapp, and Morton teaches the apparatus of claim 8. Kang further teaches wherein:
The PLD also includes a… driver, a… sensor, and a comparator; the… driver is to provide the input pattern to the IC… the … sensor is to receive a corresponding output pattern from the IC… and the comparator is to compare the corresponding output pattern to the corresponding expected pattern. (para. 48: The programmable device 233 can be implemented using a device such as a Programmable Logic Device (PLD)… The programmable device is programmed to… transmit the test pattern signal to the semiconductor device, receive the test result output from the semiconductor device, and compares the test result signal with the expected signal, thus testing the operation of the semiconductor device.) The PLD performs the function of the driver, sensor, and comparator, effectively including them.
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Kang, and Knapp before them, before the effective filing date of the claimed invention, to incorporate the PLD containing a driver, sensor, and comparator (disclosed by Kang) into the testing circuitry (disclosed by the combination of Alben and Knapp), to allow for benefits such as low cost (Kang, para. 49).
However, the combination of Alben, Kang, and Knapp does not explicitly disclose:
Wherein the memory manager is to provide an input pattern to the scan driver and a corresponding expected pattern to the comparator,
[outputting test patterns and receiving corresponding output patterns via] the scan interface
Morton teaches:
Wherein the memory manager is to provide an input pattern to the scan driver and a corresponding expected pattern to the comparator, (para. 49: the test vectors stored in memory 56 of the tester 54 are applied by the tester 54 to the device under test. The response to each test vector is read out by the VLSI tester via the interface 64 and compared by a comparator 55 of the VLSI tester to an expected response stored in the memory 56.)
[outputting test patterns and receiving corresponding output patterns via] the scan interface (para. 49: the test vectors stored in memory 56 of the tester 54 are applied by the tester 54 to the device under test. The response to each test vector is read out by the VLSI tester via the interface 64 and compared by a comparator 55 of the VLSI tester to an expected response stored in the memory 56. And para. 45: The VLSI tester 54 is used to apply scan test patterns via an interface 64.) Interface 64 is considered to be a scan interface as scan test patterns are applied through it. Additionally, in light of Morton’s scan interface, the driver and sensor disclosed by Kang are considered to be a scan driver and a scan sensor.
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Jung, Knapp, Kang, and Morton before them, before the effective filing date of the claimed invention, to incorporate a memory controller and scan interface (disclosed by Morton) into the system for testing (disclosed by the combination of Alben, Jung, Kang, and Knapp), to allow for benefits such as fault detection (Morton, para. 18).
Claims 10, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Alben in view of Jung and Morton.
Regarding claim 10, the combination of Alben and Jung discloses:
An apparatus comprising:
…
A controller, connected to a microcontroller, (para. 27: the test manager 112 [microcontroller] may indicate a type of test to be conducted, the component(s) (or test components corresponding thereto) to be tested… The test information… may be stored in the memory 214. And para. 25: the component(s) to be tested undergo testing (e.g., using… automatic test pattern generation (ATPG)). And para. 30: The Online BIST hardware 228 [performing ATPG testing] may retrieve the test information from the location. Once received; the test vectors may be applied to the components [in accordance with the test information provided by the test manager]).
to trigger [transmitting test patterns] (para. 30: The Online BIST hardware 228 [performing ATPG testing] may retrieve the test information from the location. Once received; the test vectors may be applied to the components [in accordance with the test information provided by the test manager])
…
wherein the microcontroller is to trigger and control a structural test mode during in-field… [operation] of an IC; (para. 29: structural testing may be performed. And para. 27: A test manager 112 may manage testing of the components subject to test. And para. 18: During deployment each of the components of a system may not be in use at all times. During these idle periods… the component may be tested.)
However, Alben does not explicitly disclose:
a memory manager;
[transmitting test patterns includes] the memory manager to fetch one or more automatic test pattern generation (ATPG) patterns from a memory;
a scan driver;
a scan sensor;
and a comparator;
and wherein the memory manager is to provide an input pattern to the scan driver and a corresponding expected pattern to the comparator, the scan driver is to provide the input pattern to the IC through a scan interface, the scan sensor is to receive a corresponding output pattern from the IC through the scan interface, and the comparator is to compare the corresponding output pattern to the corresponding expected pattern.
[Testing…] during in-field booting,
In the analogous art of circuit testing, Jung teaches:
[Testing…] during in-field booting, (claim 9: the BIOS is configured to perform power-on self test (POST) on the main memory and the storage device during the booting operation.)
It would have been obvious to one of ordinary skill in the art, having the teachings of Alben and Jung before them, before the effective filing date of the claimed invention, to integrate testing during the booting operation (taught by Jung) into the testing circuitry (taught by Alben), to allow for benefits such as speed and reliability (Jung, para. 7).
However, the combination of Alben and Jung does not explicitly disclose:
a memory manager;
[transmitting test patterns includes] the memory manager to fetch one or more automatic test pattern generation (ATPG) patterns from a memory;
a scan driver;
a scan sensor;
and a comparator;
and wherein the memory manager is to provide an input pattern to the scan driver and a corresponding expected pattern to the comparator, the scan driver is to provide the input pattern to the IC through a scan interface, the scan sensor is to receive a corresponding output pattern from the IC through the scan interface, and the comparator is to compare the corresponding output pattern to the corresponding expected pattern.
Morton teaches:
a memory manager; (para. 49: The test vectors stored in memory 56 of the tester 54 are applied by the tester 54 to the device under test) The tester is considered to be a memory manager as it retrieves a ATPG pattern from memory.
[transmitting test patterns includes] the memory manager to fetch one or more automatic test pattern generation (ATPG) patterns from a memory; (para. 49: The test vectors stored in memory 56 of the tester 54 are applied by the tester 54 to the device under test) When Alben’s controller triggers the transmission of a test pattern, Morton’s memory manager fetches a test pattern from memory.
a scan driver; a scan sensor; and a comparator; and wherein the memory manager is to provide an input pattern to the scan driver and a corresponding expected pattern to the comparator, the scan driver is to provide the input pattern to the [system] through a scan interface, the scan sensor is to receive a corresponding output pattern from the [system] through the scan interface, and the comparator is to compare the corresponding output pattern to the corresponding expected pattern. (para. 49: The test vectors stored in the memory 56 of the tester 54 are applied by the tester 54 to the device under test. The response to each test vector is read out by the VLSI tester via the interface 64 and compared by a comparator 55 of the VLSI tester to an expected response stored in the memory 56. And para. 45: The VLSI tester 54 is used to apply scan test patterns via an interface 64.) Interface 64 is considered to be a scan interface because scan test patterns are input therein. The tester performs the function of the scan sensor and scan driver as it inputs test patterns and receives output through the scan interface.
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Jung, and Morton before them, before the effective filing date of the claimed invention, to incorporate reading out test patterns from memory and applying them to the DUT via a scan interface (disclosed by Morton) into the IC testing circuitry (disclosed by Alben and Jung), to allow for benefits such as fault detection (Morton, para. 18).
Regarding claim 12, the combination of Alben, Jung, and Morton teaches the apparatus of claim 10. Morton further teaches:
Further comprising the memory (fig. 2, memory 56)
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Jung, and Morton before them, before the effective filing date of the claimed invention, to incorporate reading out test patterns from memory and applying them to the DUT via a scan interface (disclosed by Morton) into the IC testing circuitry (disclosed by Alben and Jung), to allow for benefits such as fault detection (Morton, para. 18).
Regarding claim 13, the combination of Alben, Jung, and Morton discloses the apparatus of claim 10. Morton further teaches:
Wherein the memory is a non-volatile memory (para. 97: the memory may be… implemented using any suitable data storage technology, such as… magnetic memory devices.) It is well known in the art that magnetic memory devices are non-volatile.
connected to the apparatus. (para. 49: The test vectors stored in the memory 56 of the tester 54 are applied by the tester 54 to the device under test.) The tester is part of the apparatus, and must be connected to the memory so that the test vectors may be accessed. Therefore, the memory is connected to the apparatus.
It would be obvious to one of ordinary skill in the art, having the teachings of Alben, Jung, and Morton before them, before the effective filing date of the claimed invention, to incorporate reading out test patterns from non-volatile memory and applying them to the DUT via a scan interface (disclosed by Morton) into the IC testing circuitry (disclosed by Alben and Jung), to allow for benefits such as fault detection (Morton, para. 18).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Alben in view of Jung, Morton, and Knapp.
Regarding claim 11, the combination of Alben, Jung, and Morton teaches the apparatus of claim 10. Alben further teaches wherein:
The apparatus is connected to the microcontroller… (para. 27: A test manager 112 may manage testing of the components subject to test.) The components subject to test are considered to be part of the apparatus.
However, Alben does not explicitly teach wherein:
The apparatus is