DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Drawings
The drawings are further objected to under 37 CFR 1.83(a) because they fail to show the subject matter of claims 5-7, 12-14, 17-19, or 24-26. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d).
The drawings are further objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
Reference number 109 of Figure 1.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
The disclosure is objected to because of the following informalities:
[00521+]: The example embodiments suffer the same issues as the claim objections/rejections and should be fixed when appropriate.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5-7, 12-14, 17-19, and 24-26 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 5 recites the limitation “to deliver faults to a fault handler on a first stack” in line 2, but no reference in the specification is made to support this limitation. The specification does not appear to specify that the fault handler is to be ON the first stack. Paragraph [00408] states “[when ns = 0] a delivery of an event such as a page fault (#PF) would use a #PF handler 3003 the current (first) stack with no stack switch,” yet the relationship between the handler and the first stack is unclear.
Claims 6 and 7 are rejected for failing to alleviate the rejection of claim 5 above.
Claim 6 recites the limitation “to deliver faults from a fault handler to a second stack” in lines 1 and 2, but no reference in the specification is made to support this limitation. The specification suggests that the fault handler USES the second stack rather than deliver faults to the stack. Paragraph [00409] states “[when ns = 1] a delivery of a page fault would switch to a new (second) stack and the #PF handler 3007 would use that new stack,” which goes against what is written by the limitation.
Claim 7 is rejected for failing to alleviate the rejection of claim 6 above.
Claim 7 recites the limitation “the fault handler from the second stack” in line 1, but no reference in the specification is made to support this limitation. The specification suggests that the fault handler USES the second stack rather than the fault handler be on the stack. Paragraph [00409] states “[when ns = 1] a delivery of a page fault would switch to a new (second) stack and the #PF handler 3007 would use that new stack,” which goes against what is written by the limitation.
Claim 12 recites the limitation “to deliver faults to a fault handler of a first stack” in line 2, but no reference in the specification is made to support this limitation. The specification does not appear to specify that the fault handler is associated to the first stack. Paragraph [00408] states “[when ns = 0] a delivery of an event such as a page fault (#PF) would use a #PF handler 3003 the current (first) stack with no stack switch,” yet the relationship between the handler and the first stack is unclear.
Claims 13 and 14 are rejected for failing to alleviate the rejection of claim 5 above.
Regarding claims 13-14, the claims are rejected for the same reasons as claims 6-7, respectively.
Claim 17 recites the limitation “to deliver faults from a fault handler to a first stack” in line 2, but no reference in the specification is made to support this limitation. The specification does not specify that the OS is to deliver faults to the first stack. Paragraph [00408] states “[when ns = 0] a delivery of an event such as a page fault (#PF) would use a #PF handler 3003 the current (first) stack with no stack switch,” yet the relationship between the handler and the first stack is unclear.
Claims 18 and 19 are rejected for failing to alleviate the rejection of claim 5 above.
Regarding claims 18-19, the claims are rejected for the same reasons as claims 6-7, respectively.
Claim 24 recites the limitation “to deliver faults to a fault handler on a first stack” in line 2, but no reference in the specification is made to support this limitation. The specification does not appear to specify that the fault handler is to be ON the first stack. Paragraph [00408] states “[when ns = 0] a delivery of an event such as a page fault (#PF) would use a #PF handler 3003 the current (first) stack with no stack switch,” yet the relationship between the handler and the first stack is unclear.
Claims 25 and 26 are rejected for failing to alleviate the rejection of claim 5 above.
Claim 25 recites the limitation “to deliver faults to a fault handler on a second stack” in line 2, but no reference in the specification is made to support this limitation. The specification suggests that the fault handler USES the second stack rather than be ON the stack. Paragraph [00409] states “[when ns = 1] a delivery of a page fault would switch to a new (second) stack and the #PF handler 3007 would use that new stack,” which goes against what is written by the limitation.
Claim 26 is rejected for failing to alleviate the rejection of claim 25 above.
Claim 26 recites the limitation “the fault handler on the second stack” in lines 1-2, but no reference in the specification is made to support this limitation. The specification suggests that the fault handler USES the second stack rather than be ON the stack. Paragraph [00409] states “[when ns = 1] a delivery of a page fault would switch to a new (second) stack and the #PF handler 3007 would use that new stack,” which goes against what is written by the limitation.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7, 14, 19, and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation “the fault handler from the second stack”. There is insufficient antecedent basis for this limitation in the claim. It’s unclear if the fault handler mentioned in this claim is the same fault handler mentioned in the claim it depends on, or if it’s a new instance due to its association to the second stack. For the sake of examination, Examiner will interpret this limitation to be “a fault handler from the second stack”.
Claims 14, 19, and 26 are rejected for the same reasons above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4, 8-11, 15-16, and 20-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: Claim 1 is an apparatus claim. Claim 8 is a method claim. Claim 15 is a method claim. Claim 20 is a system claim. Therefore, claims 1-4, 8-11, 15-16, and 20-23 are directed to a process, machine, manufacture or composition of matter.
Regarding Claim 1:
Step 2A, Prong 1: The following limitations are directed to the abstract idea of a mental process [see MPEP 2106.04(a)(2) III. C.]. In particular, the claim recites mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion).
“…to indicate a new stack flag is to be set”
“…to set the new stack flag”
As drafted, under their broadest reasonable interpretation (BRI), in view of the specification, the above limitations cover concepts performed in the human mind (observation, evaluation, judgement, or opinion).
Step 2A, Prong 2: There are no additional elements in this claim that integrate the judicial exception into a practical application.
The following additional elements are recited at a high level of generality, i.e., as a generic system performing a generic computer function of decoding and executing instructions. Such elements amount to mere instructions to implement an abstract idea using generic computer elements [see MPEP 2106.05(f)] and therefore fails to integrate the judicial exception into a practical application.
“decoder circuitry to decode an instance of a single instruction, the single instruction to include a field for an opcode”
“execution circuitry to execute the decoded instance of the single instruction according to the opcode”
Step 2B: There are no additional elements in this claim that amount to significantly more than the judicial exception.
The following additional elements are recited at a high level of generality, i.e., as a generic system performing a generic computer function of decoding and executing instructions. Such elements amount to mere instructions to implement an abstract idea using generic computer elements [see MPEP 2106.05(f)] and therefore fails to amount to significantly more than the judicial exception.
“decoder circuitry to decode an instance of a single instruction, the single instruction to include a field for an opcode”
“execution circuitry to execute the decoded instance of the single instruction according to the opcode”
Regarding Claim 2:
Step 2A, Prong 1: The claim recites the same abstract idea as in claim 1.
Step 2A, Prong 2: There are no additional elements in this claim that integrate the judicial exception into a practical application.
The following additional elements are recited at a high level of generality, i.e., as a computer component storing data. Such elements amount to mere instructions to implement an abstract idea using computer elements [see MPEP 2106.05(f)]
and therefore fails to integrate the judicial exception into a practical application.
“the new stack flag is indicated by a field in a configuration model specific register”
Step 2B: There are no additional elements in this claim that amount to significantly more than the judicial exception.
The following additional elements are recited at a high level of generality, i.e., as a computer component storing data. Such elements amount to mere instructions to implement an abstract idea using computer elements [see MPEP 2106.05(f)]
and therefore fails to amount to significantly more than the judicial exception.
“the new stack flag is indicated by a field in a configuration model specific register”
Regarding Claim 3:
Step 2A, Prong 1: The claim recites the same abstract idea as in claim 1.
Step 2A, Prong 2: There are no additional elements in this claim that integrate the judicial exception into a practical application.
The following additional elements are recited at a high level of generality, i.e., as a computer component storing data. Such elements amount to mere instructions to implement an abstract idea using computer elements [see MPEP 2106.05(f)]
and therefore fails to integrate the judicial exception into a practical application.
“the new stack flag is indicated by a field in a model specific register”
Step 2B: There are no additional elements in this claim that amount to significantly more than the judicial exception.
The following additional elements are recited at a high level of generality, i.e., as a computer component storing data. Such elements amount to mere instructions to implement an abstract idea using computer elements [see MPEP 2106.05(f)]
and therefore fails to amount to significantly more than the judicial exception.
“the new stack flag is indicated by a field in a model specific register”
Regarding Claim 4:
Step 2A, Prong 1: The claim recites the same abstract idea as in claim 1.
Step 2A, Prong 2: There are no additional elements in this claim that integrate the judicial exception into a practical application.
The following additional elements are recited at a high level of generality, i.e., as a computer component storing data. Such elements amount to mere instructions to implement an abstract idea using computer elements [see MPEP 2106.05(f)]
and therefore fails to integrate the judicial exception into a practical application.
“the new stack flag is indicated by a field in a register”
Step 2B: There are no additional elements in this claim that amount to significantly more than the judicial exception.
The following additional elements are recited at a high level of generality, i.e., as a computer component storing data. Such elements amount to mere instructions to implement an abstract idea using computer elements [see MPEP 2106.05(f)]
and therefore fails to amount to significantly more than the judicial exception.
“the new stack flag is indicated by a field in a register”
Claims 8-11 recite a method similar to the apparatus of claims 1-4 respectively. Thus, claims 8-11 are rejected to the same reasons provided for claims 1-4, respectively.
Claims 15 and 16 recite a method similar to the apparatus of claims 1 and 3 respectively. The only differences are that claim 15 recites a further abstract idea of “translating a single instruction from a first instruction set architecture into one or more instructions of a second instruction set architecture”, which may be a mental process performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion) Thus, claims 15 and 16 are rejected for this reason in addition to the same reasons provided in claims 1 and 3, respectively.
Claims 20-23 recite system claims having similar limitation with apparatus claims 1-4, respectively. The only difference is that claim 20 includes the additional limitation of a “processor core”, which encompasses mere instructions implementing an abstract idea on a computer and merely uses a computer as a tool to perform an abstract idea [see MPEP 2106.05(f)] and therefore fails to integrate the abstract idea into a practical application and fails to amount to significantly more than the judicial exception. The claim also recites “memory to store the instance of the single instruction”, which encompasses adding an insignificant extra step to the judicial exception [see MPEP 2106.05(h)] and simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality to the judicial exception [see MPEP 2106.05(d)(II)(iv) and 2106.07(a)(III)] and therefore fails to integrate the abstract idea into a practical application and fails to amount to significantly more than the judicial exception. Thus, claims 20-23 are rejected for this reason in addition to the same reasons provided for claims 1-4, respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 8-11 and 20-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Christie (US 2002/0019902 A1) in view of Waterman et al. (The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.7).
Regarding claim 1, Christie teaches an apparatus (Fig. 1: Processor 10) comprising:
decoder circuitry to decode an instance of a single instruction ([0029]: To execute instructions, there must be a decoder located within the processor as decoding the instruction is required prior to execution),
execution circuitry (Fig. 1: Execution Core 14) to set the new stack flag ([0056] and Figs. 1 and 4: LME flag in control register 26, which when set (to 0), indicates a new stack is to be switched to upon an interrupt).
Christie does not teach the single instruction to include a field for an opcode to indicate a new stack flag is to be set nor that the execution circuitry is to execute the decoded instruction of the single instruction according to the opcode to set the new stack flag.
However, first note that the LME flag is in a control register (see paragraph [0031] and Figure 1, control register 26). Furthermore, Waterman has taught the single instruction to include a field for an opcode to indicate a (Pg. 8: The CSRRW and CSRRWI write to control registers. These instructions are capable of writing into these registers, which in one of these registers may include a flag bit. The instructions provided by Waterman can write into these registers and modify the flag bit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Christie to incorporate the teachings of Waterman to provide a way to solely modify the control registers. This would allow software to flexibly modify the control register with a singular instruction. In addition, this would aid developers in reviewing or debugging code by recognizing that the instruction is modifying a control register.
Regarding claim 2, Christie in view of Waterman teaches the apparatus of claim 1, wherein the new stack flag is indicated by a field in a configuration model specific register (Christie Fig. 1: Control Register 26: LME field interpreted as "flag". The configuration model specific register is a register within the x86 architecture and are control registers).
Regarding claim 3, Christie in view of Waterman teaches the apparatus of claim 1, wherein the new stack flag is indicated by a field in a model specific register (Christie Fig. 1: Control Register 26: LME field interpreted as "flag". The model specific register is a register within the x86 architecture and are control registers).
Regarding claim 4, Christie in view of Waterman teaches the apparatus of claim 1, wherein the new stack flag is indicated by a field in a register (Christie Fig. 1, Control Register 26: LME field interpreted as "flag").
Regarding claims 8-11, the claims recite a method which is similar to the apparatus of claims 1-4, respectively, and are therefore rejected on the same premises.
Regarding claims 20-23, Christie in view of Waterman teaches a processor core (Fig. 1, Processor 10) and memory to store the instance of the single instruction (Fig. 1, instruction cache 12) and recites a system which implements the apparatus according to claims 1-4, respectively, and are therefore rejected on the same premises.
Claim(s) 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Christie (US 2002/0019902 A1) in view of Waterman et al. (The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.7) and Coleman et al. (US 2017/0286118 A1).
Regarding claim 15, Christie teaches a method (abstract), capable of decoding the one or more instructions of the second instruction set architecture ([0029]: To execute instructions, there must be a decoder located within the processor as decoding the instruction is required prior to execution), and execution circuitry (Fig. 1: Execution Core 14) to set a new stack flag ([0056] and Figs. 1 and 4: LME flag in control register 26, which when set (to 0), indicates a new stack is to be switched to upon an interrupt).
Christie does not teach the single instruction having a field for an opcode, the opcode indicating that a new stack flag is to be set nor executing the decoded one or more instructions of the second instruction set architecture according to the opcode of the single instruction from the first instruction set architecture to set the new stack flag.
However, first note that the LME flag is in a control register (see paragraph [0031] and Figure 1, control register 26). Furthermore, Waterman has taught the single instruction having a field for an opcode, the opcode indicating that a (Pg. 8: The CSRRW and CSRRWI write to control registers. These instructions are capable of writing into these registers, which in one of these registers may include a flag bit. The instructions provided by Waterman can write into these registers and modify the flag bit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Christie to incorporate the teachings of Waterman to provide a way to solely modify the control registers. This would allow software to flexibly modify the control register with a singular instruction. In addition, this would aid developers in reviewing or debugging code by recognizing that the instruction is modifying a control register.
However, Christie and Waterman does not explicitly teach translating a single instruction from a first instruction set architecture into one or more instructions of a second instruction set architecture.
Coleman teaches translating a single instruction from a first instruction set architecture into one or more instructions of a second instruction set architecture ([0045]: The paragraph explains how instead of processing the fetch instruction directly, to instead modify it into a second instruction set).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Christie in view of Waterman to incorporate the teachings of Coleman to provide a way to translate an instance of a single instruction from a first instruction set to one or more instructions of a second instruction set architecture to then be sent to the processor. A common motivation for translating an instruction from a first instruction set to a second instruction set is that it allows one of ordinary skill in the art to create a simpler design based on the second instruction set. This simpler design would allow easier implementation of the hardware (e.g., a simpler decoder), would require less time to verify and debug the hardware, and an improvement in performance. In addition, it would allow the processor to accommodate non-native instructions to increase flexibility.
Regarding claim 16, Christie in view of Waterman and Coleman teaches the method of claim 15, wherein the new stack flag is indicated by a field in a model specific register (Christie Fig. 1: Control Register 26: LME field interpreted as "flag". The model specific register is a register within the x86 architecture and are control registers).
Allowable Subject Matter
Claims 5-7, 12-14, 17-19, and 24-26 are both objected to as being dependent upon a rejected base claim and rejected under 35 USC 112(a), but would be allowable if rewritten in independent form including all of the limitations of the base claim, any intervening claims, and overcome all 112(a) rejections without introducing new subject matter.
Response to Arguments
Applicant’s arguments, see Page 8, filed on August 18, 2025, with respect to the drawings objections have been considered fully and are mostly persuasive. Applicant has addressed most drawing objections by modification of drawings, modification of the specification, or indicating that reference numbers are in specification. However, the objection relating to reference number “109” has not been addressed. Therefore, the objection is maintained until the issue is addressed.
Applicant’s arguments, see Page 8, filed on August 18, 2025, with respect to the claim objections have been fully considered and are persuasive. Applicant has addressed all claim objections by amending claims to address the objections.
Applicant's arguments, see Page 8, filed on August 18, 2025, with respect to the rejection of claims 1-4, 8-11, 15-16, and 20-23 under 35 U.S.C. 101 have been fully considered but they are not persuasive.
Regarding arguments on page 8, lines 2-5, Applicant argues that the claimed subject matter is not a “mental process” since “human minds” do not use stacks.
See MPEP 2106 regarding patent subject matter eligibility. Applicant is claiming a flag to be set (i.e., setting a bit in a register), which is something that can be done in the human mind or with pen and paper. The concept of setting a bit of a register can be viewed as mentally decoding a string of numbers to indicate a “1” or a “0”, hence the “mental process” (See MPEP 2106.04(a)(2)(III), Paragraph 3). Therefore, the remarks in response to the claimed subject matter not being an abstract idea are considered not persuasive.
Regarding arguments on page 8, lines 7-11, Applicant argues that no “generic computer” can execute the particular instruction.
Applicant doesn’t go into depth as to what makes their decoder and execution circuitry different from a “generic” decoder and execution circuitry as they recite the elements at a high level, which doesn’t integrate the judicial exception into a practical application (see MPEP 2106.05(f)(2), Paragraphs 1-2). Therefore, the remarks regarding no “generic computer” can’t execute the particular instruction is considered not persuasive.
Applicant’s arguments, see Page 8, filed on August 18, 2025, with respect to the rejection of claims 5-7, 12-14, 17-19, and 24-26 under 35 U.S.C. 112(a) have been fully considered but they are not persuasive. Applicant attempted to address the issues by amending some of the claims rejected under 35 U.S.C. 112(a). However, the amended claims under the rejection (claims 6-7, 12-14, 17-19, and 25-26) do not alleviate the issues or makes the claims any clearer. Additionally, some claims with the rejection (claims 5 and 24) were not amended and therefore the rejection on the non-amended claims are maintained. See 112(a) rejections above.
Applicant’s arguments, see Page 9, filed on August 18, 2025, with respect to the rejection of claims 7, 14, 19, and 26 under 35 U.S.C. 112(b) have been fully considered but they are not persuasive. Applicant has amended the claims to provide clarity on “the operating system”. However, the amended claims bring light to new 112(b) rejections. See new 112(b) rejections above.
Applicant's arguments, see Page 9-10, filed on August 18, 2025, with respect to the rejection of claims 1-4, 8-11, 15-16, and 20-23 under 35 U.S.C. 103 have been fully considered but they are not persuasive.
Regarding arguments on page 9, lines 6-16, Applicant argues that the combination does not teach “execution circuitry to execute the decoded instance of the single instruction according to the opcode to set the new stack flag” due to asserting that the primary reference or secondary reference cited are not “relevant to the usage of a new stack”.
Examiner respectfully disagrees with this argument. First, applicant does not address the mapping directly, but rather broadly interpret the mapping from the specification of Christie to the claim language and pointing that the mapping isn’t relevant. Examiner agrees that in combination with other bits of the register, the “LME bit” does more than “stack switching” as described in the specification of Christie. This is why Examiner ONLY points out the ”LME bit” as the “new stack flag” because it’s the only relevant bit that when set (to 0), the OS is to switch stacks when an interrupt occurs, regardless of what the other bits are set to (see Fig. 4 and [0056] for reference). The claimed subject matter does not prohibit the use of the “new stack flag” in other configurations.
As for the combination, starting with Christie, the OS is to switch to a different stack when in 16 bit mode or 32 bit mode (i.e., LME set to 0) when an interrupt occurs. The concept of switching to a different stack can be considered a “new stack” as the OS does not continue to use the previous stack, known as the “old stack”, for the duration of the interrupt. Although Christie does not explicitly say how the bit is set, since the LME flag is in a control register, Examiner combines Waterman’s teachings of an instruction that modifies a control register. In short, the combination given describes an instruction that sets a bit (to 0) to indicate a stack switch when an interrupt occurs, i.e., a new stack flag. Therefore, the remarks regarding the relevancy of the prior art references are considered not persuasive.
Regarding arguments on page 10, lines 6-14, the arguments are similar to the previous arguments above and have been considered to be not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/E.A./Examiner, Art Unit 2183 /JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183