DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 1 recites the limitation "identified microthread’s save state”. There is insufficient antecedent basis for this limitation in the claim. For the purposes of prior art examination, the examiner is interpreting as "the identified microthread’s state”.
Claim 5 recites “the area”. There is insufficient antecedent basis for this for this limitation in the claim. Examiner is interpreting as “the particular area”.
Claim 11 recites the limitation "the identified microthread’s save state". There is insufficient antecedent basis for this limitation in the claim. For the purposes of prior art examination, the examiner is interpreting as "the identified microthread’s state".
Claim 15 recites the “particular area”. There is insufficient antecedent basis for this limitation in the claim. Examiner is interpreting claim 15 to be dependent on claim 13. Claims 16 and 17 also recite “the particular area”.
Claim 21 recites the limitation "identified microthread’s save state". There is insufficient antecedent basis for this limitation in the claim. Examiner is interpreting as “the identified microthread’s state”.
Claim 21 recites “executing the decoded instruction”. There is insufficient antecedent basis for this limitation in the claim. The claim states “decoding the one or more instructions of the second instruction set”. Examiner is interpreting as “executing the one or more decoded instructions”.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: hardware execution resource to execute in claim 11.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As described above, the disclosure does not provide adequate structure for the hardware execution resource. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Claims 12-19 are rejected for inheriting the same deficiency of claim 11.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim limitation of claim 11, “a hardware execution resource to execute the decoded instruction to read the identified microthread’s save state” invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. The specification states that execution is done by execution circuitry but there is no disclosure of any particular structure, either explicitly or inherently, to execute the decoded instruction. Therefore, claims 1 and 11 are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. Claim 12-19 are rejected for inheriting the deficiencies of claim 11 respectively.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Dependent claims are rejected for the same reason.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5,7-15,17-24, and 26 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5,7-15,17-24, and 26 of copending Application No. 17712124 in view of Elmoustapha et al. (US 2017/0269935 A1).
Claims 6,16, and 25 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 6,16, and 25 of copending Application No. 17712124 in view of Elmoustapha et al. (US 2017/0269935 A1) and in further view of Alexander et al. (US 11467833 B2).
Regarding claim 1 of the application, claim 1 of the reference application (No. 17712124) does not explicitly teach the opcode to indicate a read of a particular microthread's state as identified by the microthread identifier from the microthread state save area pointed to by the pointer; and a hardware execution resource to execute the decoded instruction to read the identified microthread's save state.
However, it does teach an apparatus comprising: decoder circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode and one or more fields to indicate a first source operand to store a pointer for a microthread state save area, and one or more fields to indicate a second source operand to store a microthread identifier, the opcode to indicate a context write of a particular microthread's state as identified by the microthread identifier from the microthread state save area pointed to by the pointer; wherein the context is to be written to the microthread state save area when transitioning from a microthread execution to a host mode and execution circuitry to execute the decoded instruction to write the identified microthread's save state.
Elmoustapha [0092] teaches these elements (the opcode to indicate a read of a particular microthread's state as identified by the microthread identifier from the microthread state save area pointed to by the pointer; and execution circuitry to execute the decoded instruction to read the identified microthread's save state) by describing a pipeline comprising of a decode unit and an execution cluster to both read and write instructions.
It would have been obvious to one of ordinary skill in the art to combine the teachings of the reference application with the teachings of Elmoustapha to have an apparatus that decodes and executes both read and write instructions to memory. A person of ordinary skill in the art would understand that systems capable of reading data from a memory or register are also designed to write data to that memory or register. Reading data from a register to the processor so that the processor can use or manipulate it and writing data from the processor back to save the results or update values are fundamental to data processing.
Claims 2-10 of the reference application are identical to claims 2-10 of the examining application and thus are rejected due to inheriting the deficiencies of claim 1.
Regarding claim 6 of the application, claim 6 of the reference application explicitly teaches the apparatus of claim 5, wherein the particular area is a general purpose register. But are dependent on two differing claims, one based on reading the identified microthread's save state, and the other on writing the identified microthread's save state. Elmoustapha teaches the apparatus of claim 5, however they do not teach wherein the particular area is a general purpose register. However, Alexander teaches the apparatus of claim 5, wherein the particular area is a general purpose register. (Col. 12, lines 5-6,30-33 & Col. 13 line 24-26: Alexander describes that each worker thread context has its own instance of the MRF (main register file) and that general purpose MRF comprises of particular registers specified by operands of the instructions.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Elmoustapha with the teachings of Alexander to have the particular area be a general purpose register, because registers can be read/written to faster.
Regarding claim 11 of the application, claim 11 of the reference application does not explicitly teach the opcode to indicate a read of a particular microthread's state as identified by the microthread identifier from the microthread state save area pointed to by the pointer; and a hardware execution resource to execute the decoded instruction to read the identified microthread's save state.
However, it does teach a system comprising: memory to store an instance of a single instruction; and an apparatus comprising: decoder circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode and one or more fields to indicate a first source operand to store a pointer for a microthread state
save area, and one or more fields to indicate a second source operand to store a microthread identifier, the opcode to indicate a write of a particular microthread's state as identified by the microthread identifier from the microthread state save area pointed to by the pointer, wherein the context is to be written to the microthread state save area when transitioning from a microthread execution to a host mode; and execution circuitry to execute the decoded instruction to write the identified microthread's save state.
Elmoustapha [0092] teaches these elements (the opcode to indicate a read of a particular microthread's state as identified by the microthread identifier from the microthread state save area pointed to by the pointer; and a hardware execution resource to execute the decoded instruction to read the identified microthread's save state) by describing a pipeline comprising of a decode unit and an execution cluster to read and write instructions.
It would have been obvious to one of ordinary skill in the art to combine the teachings of the reference application with the teachings of Elmoustapha to have an apparatus that decodes and executes both read and write instructions to memory. A person of ordinary skill in the art would understand that systems capable of reading data from a memory or register are also designed to write data to that memory or register. Reading data from a register to the processor so that the processor can use or manipulate it and writing data from the processor back to save the results or update values are fundamental to data processing.
Claims 12-20 of the reference application are identical to claims 12-20 of the examining application and thus are rejected due to inheriting the deficiencies of claim 11.
Regarding claim 16 of the application, claim 16 of the reference application explicitly teaches the system of claim 11, wherein the particular area is a general purpose register. But they are dependent on two differing claims, one based on reading the identified microthread's save state, and the other on writing the identified microthread's save state. Elmoustapha teaches the system of claim 11, however they do not teach wherein the particular area is a general purpose register. However, Alexander teaches the system of claim 11, wherein the particular area is a general purpose register. (Col. 12, lines 5-6,30-33 & Col. 13 line 24-26: Alexander describes that each worker thread context has its own instance of the MRF (main register file) and that general purpose MRF comprises of particular registers specified by operands of the instructions.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Elmoustapha with the teachings of Alexander to have the particular area be a general purpose register, because registers can be read/written to faster.
Regarding claim 21 of the application, claim 21 of the reference application does not explicitly teach the opcode to indicate a read of a particular microthread's state as identified by the microthread identifier from the microthread state save area pointed to by the pointer and executing the decoded instruction according to the opcode to read the identified microthread's save state.
However, it does teach a method comprising: translating an instance of a single instruction of a first instruction set to one or more instructions of a second instruction set, the single instruction to the single instruction to include fields for an opcode and one or more fields to indicate a first source operand to store a pointer for a microthread state save area, and one or more fields to indicate a second source operand to store a microthread identifier, the opcode to indicate a write of a particular microthread's state as identified by the microthread identifier from the microthread state save area pointed to by the pointer; wherein the context is to be written to the microthread state save area when transitioning from a microthread execution to a host mode; decoding the one or more instructions of the second instruction set; executing the decoded instruction according to the opcode to write the identified microthread's save state. Elmoustapha [0092] teaches these elements (the opcode to indicate a read of a particular microthread's state as identified by the microthread identifier from the microthread state save area pointed to by the pointer and executing the decoded instruction according to the opcode to read the identified microthread's save state.) by describing a pipeline comprising of a decode unit and an execution cluster to both read and write instructions.
It would have been obvious to one of ordinary skill in the art to combine the teachings of the reference application with the teachings of Elmoustapha to have an apparatus that decodes and executes both read and write instructions to memory. Reading data from a register to the processor so that the processor can use or manipulate it and writing data from the processor back to save the results or update values are fundamental to data processing.
Claims 22-26 of the reference application are identical to claims 22-26 of the examining application and thus are rejected due to inheriting the deficiencies of claim 21.
Regarding claim 25 of the application, claim 25 of the reference application explicitly teaches the method of claim 24, wherein the particular area is a general purpose register. But they are dependent on two differing claims, one based on reading the identified microthread's save state, and the other on writing the identified microthread's save state. Elmoustapha teaches the method of claim 24, however they do not teach wherein the particular area is a general purpose register. However, Alexander teaches the method of claim 24, wherein the particular area is a general purpose register. (Col. 12, lines 5-6,30-33 & Col. 13 line 24-26: Alexander describes that each worker thread context has its own instance of the MRF (main register file) and that general purpose MRF comprises of particular registers specified by operands of the instructions.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Elmoustapha with the teachings of Alexander to have the particular area be a general purpose register, because registers can be read/written to faster.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5,7-15,17-24, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Elmoustapha et al. (US 2017/0269935 A1, herein Elmoustapha) in view of Kang et al (US 2021/0141641 A1, herein Kang).
Regarding claim 1, Elmoustapha teaches an apparatus comprising: (Fig. 4B and [0093-95]) decoder circuitry to decode an instance of a single instruction (decode unit 440 [0095]), the single instruction to include fields for an opcode (FIG.3D and [0077]: fields 361-362 for encoding an opcode for a load-stride instruction ([0090])) and one or more fields to indicate a first source operand to store a pointer for a microthread state save area, ([0090]: a source2 field stores a pointer to an area/portion of memory storing save state for the thread/microthread (paragraph [0100])), and one or more fields to indicate a second source operand to store a microthread identifier ([0090]: a source3 field stores a stride length that is added to an offset for accessing memory and identifies and loads those elements to an area/portion of memory storing save state for the thread/microthread (paragraph [0100])), the opcode to indicate a read of a microthread's state as identified by the microthread identifier from the microthread state save area pointed to by the pointer; ([0090] the opcode for a load-stride instruction which uses the two source operands to load to an area/portion of memory storing save state) and execution circuitry to execute the decoded instruction to read the identified microthread's save state (Execution units 462 [0096] and “FIG. 1C illustrates another alternative embodiments of a data processing system capable of executing instructions to provide vector loads and/or stores with strides and masking functionality”).
Elmoustapha does not explicitly teach that context is to be written to the microthread state save area when transitioning from a microthread execution to a host mode.
Kang teaches storing context to memory when transitioning from a microthread execution to a host mode (Fig. 4, paragraph 52, preparing a thread and storing caused by a request from a host as a host mode, Paragraphs 73-75, the state while the thread is being processed by the storage before the new event is received as the microthread execution state, Alternately, Fig. 4, S115 as the microthread execution mode, S120 as the host mode).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the transitions of the states and store the context in the microthread state save area in the processor of Elmoustapha. One of ordinary skill in the art would be motivated to do so as this would allow processing of multiple threads for tasks and also have threads ready to be processed with the preparation in place, thus improving efficiency in the processing of the threads.
Regarding claim 2, Elmoustapha and Kang teach the apparatus of claim 1 wherein the first and second source operands are registers. ([0048] & [0090]: Elmoustapha teaches that the source operands in instructions can be registers. The source2 field in the instruction stores a pointer to an area/portion of memory storing the save state for the thread and the source3 field stores the stride and these fields would be stored in registers.)
Regarding claim 3, Elmoustapha and Kang teach the apparatus of claim 1, wherein the instance of the single instruction further comprises one or more fields to indicate a third source operand to store an enumeration of a particular area of the microthread's state as identified by the microthread identifier from the microthread state save area pointed to by the pointer. (Elmoustapha: in Figure 15 & [0132], a load with stride and mask instruction in decoded, and a mask is field is read. The mask field determines which elements to load into a destination register: one value (for example: 1) indicates the element has not been loaded from memory and a second value (for example: 0) indicates that the element does not need to be loaded or has already been loaded. The set of elements to be loaded, determined by the 1s in the mask field are considered as an enumerated list.)
Regarding claim 4, Elmoustapha and Kang teach the apparatus of claim 3 wherein the first, second, and third source operands are registers. ([0048] & [0090]: Elmoustapha teaches that the source operands in instructions can be registers. The source2 field in the instruction stores a pointer to an area/portion of memory storing the save state for the thread and the source3 field stores the stride and these fields would be stored in registers. The third operand is a mask, which is stored in a third register (the mask register, [0036]).
Regarding claim 5, Elmoustapha and Kang teaches the apparatus of claim 3, wherein the area comprises contents of a register stored in the microthread state save area. (Elmoustapha [0130] “…the corresponding data element is loaded from the memory and stored into a vector register having a plurality of data fields, a portion of which to store the loaded data elements.” In other words, the particular area is the vector register which comprises a plurality of data fields to store its contents (the loaded data elements).
Regarding claim 7, Elmoustapha and Kang teaches the apparatus of claim 5, wherein the particular area is a vector register. (Elmoustapha Fig. 15 & [0130] The particular area where the elements are loaded into is a vector destination register.)
Regarding claim 8, Elmoustapha and Kang teach the apparatus of claim 1, wherein the apparatus is a processor core. (Elmoustapha Fig. 4B, “shows processor core 490 [the apparatus] including a front end unit 430 [comprising a decode unit] coupled to an execution engine unit 450 [the hardware execution resource], and both are coupled to a memory unit 470.”).
Regarding claim 9, Elmoustapha and Kang teach the apparatus of claim 1, wherein the apparatus is an accelerator. Elmoustapha [0100]: The apparatus or processor core 490 may support multithreading to execute two or more parallel sets of threads to accelerate tasks, [0068]: the processor may also have out-of-order execution logic to optimize performance, and a fast scheduler to schedule micro-instructions two times faster.
Regarding claim 10, Elmoustapha and Kang teach the apparatus of claim 1, further comprising microcode. Elmoustapha [0095]: a processor core 490 that comprises an execution engine unit 450 and a decode unit 440. The decode unit may generate micro-code. This coupling implies composition within a (hardware execution) resource.
Regarding claim 11, Elmoustapha teaches A system comprising: (Fig. 4B) memory to store an instance of a single instruction; ([0093-0095] an instruction cache unit 434 can store instructions that can be executed by the processor core 490, an apparatus comprising: (Fig. 4B and [0093-95]) decoder circuitry to decode an instance of a single instruction (decode unit 440 [0095]), the single instruction to include fields for an opcode (FIG.3D and [0077]: fields 361-362 for encoding an opcode for a load-stride instruction ([0090])) and one or more fields to indicate a first source operand to store a pointer for a microthread state save area, ([0090]: a source2 field stores a pointer to an area/portion of memory storing save state for the thread/microthread (paragraph [0100])), and one or more fields to indicate a second source operand to store a microthread identifier, ([0090]: a source3 field stores a stride length that is added to an offset for accessing memory and identifies and loads those elements to an area/portion of memory storing save state for the thread/microthread (paragraph [0100])), the opcode to indicate a read of a microthread's state as identified by the microthread identifier from the microthread state save area pointed to by the pointer; ([0090] the opcode for a load-stride instruction which uses the two source operands to load to an area/portion of memory storing save state), and a hardware execution resource to execute the decoded instruction to read the identified microthread's save state. This element is interpreted under 35 U.S.C. 112(f) as a hardware execution circuit that executes the decoded instruction to read the identified microthread’s save state. (Execution units 462 [0096] and “FIG. 1C illustrates another alternative embodiments of a data processing system capable of executing instructions to provide vector loads and/or stores with strides and masking functionality”).
Elmoustapha does not explicitly teach that context is to be written to the microthread state save area when transitioning from a microthread execution to a host mode.
Kang teaches storing context to memory when transitioning from a microthread execution to a host mode (Fig. 4, paragraph 52, preparing a thread and storing caused by a request from a host as a host mode, Paragraphs 73-75, the state while the thread is being processed by the storage before the new event is received as the microthread execution state, Alternately, Fig. 4, S115 as the microthread execution mode, S120 as the host mode).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the transitions of the states and store the context in the microthread state save area in the processor of Elmoustapha. One of ordinary skill in the art would be motivated to do so as this would allow processing of multiple threads for tasks and also have threads ready to be processed with the preparation in place, thus improving efficiency in the processing of the threads.
Regarding claim 12, Elmoustapha and Kang teach the system of claim 11 wherein the first and second source operands are registers. (Elmoustapha [0048] & [0090]: Elmoustapha teaches that the source operands in instructions can be registers. The source2 field in the instruction stores a pointer to an area/portion of memory storing the save state for the thread and the source3 field stores the stride and these fields would be stored in registers.)
Regarding claim 13, Elmoustapha and Kang teaches the system of claim 11, wherein the instance of the single instruction further comprises one or more fields to indicate a third source operand to store an enumeration of a particular area of the particular microthread's state as identified by the microthread identifier from the microthread state save area pointed to by the pointer. (Elmoustapha in Figure 15 & [0132], a load with stride and mask instruction in decoded, and a mask is field is read. The mask field determines which elements to load into a destination register: one value (for example: 1) indicates the element has not been loaded from memory and a second value (for example: 0) indicates that the element does not need to be loaded or has already been loaded. The set of elements to be loaded, determined by the 1s in the mask field are considered as an enumerated list.)
Regarding claim 14, Elmoustapha and Kang teaches the system of claim 13 wherein the first, second, and third source operands are registers. ([0048] & [0090]: Elmoustapha teaches that the source operands in instructions can be registers. The source2 field in the instruction stores a pointer to an area/portion of memory storing the save state for the thread and the source3 field stores the stride and these fields would be stored in registers. The third operand is a mask, which is stored in a third register (the mask register, [0036]).
Regarding claim 15, Elmoustapha and Kang teaches the system of claim
Regarding claim 17, Elmoustapha and Kang teach the system of claim 15, wherein the particular area is a vector register. ((Fig. 15 & [0130] The particular area where the elements are loaded into is a vector destination register.)
Regarding claim 18, Elmoustapha and Kang teaches the system of claim 11, wherein the apparatus is a processor core. (Elmoustapha Fig. 4B, “shows processor core 490 [the apparatus] including a front end unit 430 [comprising a decode unit] coupled to an execution engine unit 450 [the hardware execution resource], and both are coupled to a memory unit 470.”)
Regarding claim 19, Elmoustapha and Kang teaches the system of claim 11, wherein the apparatus is an accelerator. (Elmoustapha [0100]: The apparatus or processor core 490 may support multithreading to execute two or more parallel sets of threads to accelerate tasks, [0068]: the processor may also have out-of-order execution logic to optimize performance, and a fast scheduler to schedule micro-instructions two times faster.
Regarding claim 20, Elmoustapha and Kang teach the system of claim 11, wherein the hardware execution resource comprises execution circuitry and microcode. Although the claim recites a hardware execution resource comprises execution circuitry and microcode, the prior art teaches [0095]: a processor core 490 that comprises an execution engine unit 450 and a decode unit 440. The decode unit may generate micro-code. This coupling implies composition within a (hardware execution) resource.
Regarding claim 21, Elmoustapha teaches a method comprising: translating an instance of a single instruction of a first instruction set to one or more instructions of a second instruction set, ; ([0147]: An instruction converter (using binary translation) may translate, an instruction to one or more instructions to be processed by the core) the single instruction to include fields for an opcode (FIG.3D and [0077]: fields 361-362 for encoding an opcode for a load-stride instruction ([0090])) and one or more fields to indicate a first source operand to store a pointer for a microthread state save area, ([0090]: a source2 field stores a pointer to an area/portion of memory storing save state for the thread/microthread (paragraph [0100])), and one or more fields to indicate a second source operand to store a microthread identifier, ([0090]: a source3 field stores a stride length that is added to an offset for accessing memory and identifies and loads those elements to an area/portion of memory storing save state for the thread/microthread (paragraph [0100])), the opcode to indicate a read of a particular microthread's state as identified by the microthread identifier from the microthread state save area pointed to by the pointer ([0090] the opcode for a load-stride instruction which uses the two source operands to load to an area/portion of memory storing save state), decoding the one or more instructions of the second instruction set; (decode unit 440 [0095]), executing the decoded instruction according to the opcode to read the identified microthread's save state. This element is interpreted under 35 U.S.C. 112(f) as a hardware execution circuit that executes the decoded instruction to read the identified microthread’s save state. (Execution units 462 [0096] and “FIG. 1C illustrates another alternative embodiments of a data processing system capable of executing instructions to provide vector loads and/or stores with strides and masking functionality”).
Elmoustapha does not explicitly teach that context is to be written to the microthread state save area when transitioning from a microthread execution to a host mode.
Kang teaches storing context to memory when transitioning from a microthread execution to a host mode (Fig. 4, paragraph 52, preparing a thread and storing caused by a request from a host as a host mode, Paragraphs 73-75, the state while the thread is being processed by the storage before the new event is received as the microthread execution state, Alternately, Fig. 4, S115 as the microthread execution mode, S120 as the host mode).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the transitions of the states and store the context in the microthread state save area in the processor of Elmoustapha. One of ordinary skill in the art would be motivated to do so as this would allow processing of multiple threads for tasks and also have threads ready to be processed with the preparation in place, thus improving efficiency in the processing of the threads.
Regarding claim 23, Elmoustapha and Kang teaches the method of claim 21, wherein the instance of the single instruction further comprises one or more fields to indicate a third source operand to store an enumeration of a particular area of the particular microthread's state as identified by the microthread identifier from the microthread state save area pointed to by the pointer. (Elmoustapha in Figure 15 & [0132], a load with stride and mask instruction in decoded, and a mask is field is read. The mask field determines which elements to load into a destination register: one value (for example: 1) indicates the element has not been loaded from memory and a second value (for example: 0) indicates that the element does not need to be loaded or has already been loaded. The set of elements to be loaded, determined by the 1s in the mask field are considered as an enumerated list.)
Regarding claim 24, Elmoustapha and Kang teaches the method of claim 23, wherein the particular area comprises contents of a register stored in the microthread state save area. (Elmoustapha [0130] “…the corresponding data element is loaded from the memory and stored into a vector register having a plurality of data fields, a portion of which to store the loaded data elements.” In other words, the particular area is the vector register which comprises a plurality of data fields to store its contents (the loaded data elements).
Regarding claim 26, Elmoustapha and Kang teaches the method of claim 23, wherein the particular area is a vector register. (Elmoustapha Fig. 15 & [0130] The particular area where the elements are loaded into is a vector destination register.)
Claims 6,16, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Elmoustapha and Kang in view of Alexander et al. (US 11467833 B2).
Regarding claim 6, although Elmoustapha and Kang teaches the apparatus of claim 5, they do not teach wherein the particular area is a general purpose register. However, Alexander teaches the apparatus of claim 5, wherein the particular area is a general purpose register. (Col. 12, lines 5-6,30-33 & Col. 13 line 24-26: Alexander describes that each worker thread context has its own instance of the MRF (main register file) and that general purpose MRF comprises of particular registers specified by operands of the instructions.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Elmoustapha and Kang with the teachings of Alexander to have the particular area be a general purpose register, because registers can be read/written to faster.
Regarding claim 16, although Elmoustapha and Kang teach the system of claim 15, they do not teach wherein the particular area is a general purpose register. However, Alexander teaches the system of claim 15, wherein the particular area is a general purpose register. (Col. 12, lines 5-6,30-33 & Col. 13 line 24-26: Alexander describes that each worker thread context has its own instance of the MRF (main register file) and that general purpose MRF comprises of particular registers specified by operands of the instructions.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Elmoustapha and Kang with the teachings of Alexander to have the particular area be a general purpose register, because registers can be read/written to faster.
Regarding claim 25, although Elmoustapha and Kang teaches the method of claim 24, they do not teach wherein the particular area is a general purpose register. However, Alexander teaches the system of claim 15, wherein the particular area is a general purpose register. (Col. 12, lines 5-6,30-33 & Col. 13 line 24-26: Alexander describes that each worker thread context has its own instance of the MRF (main register file) and that general purpose MRF comprises of particular registers specified by operands of the instructions.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Elmoustapha and Kang with the teachings of Alexander to have the particular area be a general purpose register, because registers can be read/written to faster.
Response to Arguments
The Applicant’s arguments, filed 10/13/2025, have been fully considered.
Regarding the rejection under 112(a), Applicant states that claim 11 has been amended to overcome the invocation of 35 USC 112(f). However, claim 11 has not been amended in a manner similar to claim 1.
Applicant’s argument, that Elmoustapha does not teach the limitations in the amended independent claims, is persuasive. Hence the rejection has been withdrawn. Upon further consideration, a new rejection has been made in view of Kang.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jyoti Mehta whose telephone number is (571) 270-3995. The examiner can normally be reached Mon-Thurs 8:00-6:00 EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached at (571) 272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183